K4E151611

K4E171611D SAMSUNG | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 35

Technical content

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D This is a family of 1,048,576 x 16 bit Extended Data Out CMOS DRAMs. Extended Data Out Mode offers high speed random access of memory cells within the same row, so called Hyper Page Mode. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-45, -5 0 or -6 0 ), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS -before- RAS refresh, RAS -only refresh and Hidden refresh capabilities. Furthermore, Self- refresh operation is available in L-version. This 1Mx16 EDO Mode DRAM family is fabricated using Samsung ′ s advanced CMOS pro- cess to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomp uter, personal computer and portable machines.

• Part Identification - K 4E171611D-J(T) (5V, 4K Ref.) - K 4E151611D-J(T) (5V, 1K Ref.) - K 4E171612D-J(T) (3.3V, 4K Ref.) - K 4E151612D-J(T) (3.3V, 1K Ref.)
• Extended Data Out Mode operation (Fast Page Mode with Extended Data Out)
• 2 CAS Byte/Word Read/Write operation
• CAS -before- RAS refresh capability
• RAS -only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in plastic SOJ 400mil and TSOP(II) packages
• Single +5V ±10% power supply (5V product)
• Single +3.3V ±0.3V power supply (3.3V product) Control Clocks VBB Generator Refresh Timer Refresh Control Refresh Counter Row Address Buffer Col. Address Buffer Row Decoder Column Decoder Lower Data out Buffer RAS UCAS LCAS W Vcc Vss DQ0 to DQ7 A0-A11 (A0 - A9) *1 A0 - A7 (A0 - A9) *1 Memory Array 1,048,576 x16 Cells SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 1M x 16Bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

FEATURES

FUNCTIONAL BLOCK DIAGRAM• Refresh Cycles Part NO. V CC Refresh cycle Refresh period Nor- L-ver K4E171611D 5V 4K 64ms 128msK4E171612D 3.3V K4E151611D 5V 1K 16ms K4E151612D 3.3V

• Performance Range Speed tRAC tCAC tRC tHPC Remark -45 45ns 13ns 69ns 16ns 5V/3.3V -5 0 50ns 15ns 84ns 20ns 5V/3.3V -6 0 60ns 17ns 104ns 25ns 5V/3.3V
• Active Power Dissipation Speed 3.3V 5V 4K 1K 4K 1K -45 360 540 550 825 -5 0 324 504 495 770 -6 0 288 468 440 715 Unit : mW S e n s e A m p s & I/O Upper Data in Buffer Upper Data out Buffer Lower Data in Buffer DQ 8 to DQ15 OE Note) *1 : 1K Refresh

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D V CC DQ0 DQ1 DQ2 DQ3 V CC DQ4 DQ5 DQ6 DQ7 N.C N.C N.C W RAS *A11(N.C) *A10(N.C) V CC V SS DQ15 DQ14 DQ13 DQ12 V SS DQ11 DQ10 DQ9 DQ8 N.C N.C LCAS UCAS OE V SS PIN CONFIGURATION (Top Views) Pin Name Pin Function A0 - A11 Address Inputs (4K Product) A0 - A9 Address Inputs (1K Product) DQ0 - 15 Data In/Out V SS Ground RAS Row Address Strobe UCAS Upper Column Address Strobe LCAS Lower Column Address Strobe W Read/Write Input OE Data Output Enable V CC Power(+5V) Power(+3.3V) N.C No Connection V CC DQ0 DQ1 DQ2 DQ3 V CC DQ4 DQ5 DQ6 DQ7 N.C N.C W RAS *A11(N.C) *A10(N.C) V CC V SS DQ15 DQ14 DQ13 DQ12 V SS DQ11 DQ10 DQ9 DQ8 N.C LCAS UCAS OE V SS *A10 and A11 are N.C for K 4E151611(2)D (5V/3.3V, 1K Ref. product) J : 400mil 42 SOJ T : 400mil 50(44) TSOP II

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D ABSOLUTE MAXIMUM RATINGS * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameter Symbol Rating Units 3.3V 5V Voltage on any pin relative to V SS V IN, V OUT -0.5 to +4.6 -1.0 to +7.0 V Voltage on V CC supply relative to V SS V CC -0.5 to +4.6 -1.0 to +7.0 V Storage Temperature Tstg -55 to +150 -55 to +150 °C Power Dissipation P D 1 1 W Short Circuit Output Current IOS Address 50 50 mA RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, T A = 0 to 70 °C) *1 : V CC +1.3V/15ns(3.3V), V CC +2.0V/20ns(5V), Pulse width is measured at V CC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at V SS Parameter Symbol 3.3V 5V Units Min Typ Max Min Typ Max Ground V SS 0 0 0 0 0 0 V Input High Voltage V IH 2.0 - V CC +0.3 *1 2.4 - V CC +1.0 *1 V Input Low Voltage V IL -0.3 *2 - 0.8 -1.0 *2 - 0.8 V DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.) Max Parameter Symbol Min Max Units 3.3V Input Leakage Current (Any input 0 ≤V IN ≤V IN +0.3V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V ≤V OUT ≤V CC ) IO(L) -5 5 uA Output High Voltage Level(I OH =-2mA) V OH 2.4 - V Output Low Voltage Level(I OL =2mA) V OL - 0.4 V Input Leakage Current (Any input 0 ≤V IN ≤V IN +0.5V, all other input pins not under test=0 Volt) II(L) -5 5 uA Output Leakage Current (Data out is disabled, 0V ≤V OUT ≤V CC ) IO(L) -5 5 uA Output High Voltage Level(I OH =-5mA) V OH 2.4 - V Output Low Voltage Level(I OL =4.2mA) V OL - 0.4 V

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D *Note : ICC1 , I CC3 , I CC4 and I CC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1 , I CC3 and I CC6, address can be changed maximum once while RAS =V IL . In I CC4 , address can be changed maximum once within one Hyper page mode cycle time, t HPC . DC AND OPERATING CHARACTERISTICS (Continued) ICC1 * : Operating Current ( RAS and UCAS , LCAS , Address cycling @t RC =min.) ICC2 : Standby Current ( RAS = UCAS = LCAS = W =V IH ) ICC3 * : RAS -only Refresh Current ( UCAS = LCAS =V IH , RAS , Address cycling @t RC =min.) ICC4 * : Hyper Page Mode Current ( RAS =V IL , UCAS or LCAS , Address cycling @t HPC =min.) ICC5 : Standby Current ( RAS = UCAS = LCAS = W =V CC -0.2V) ICC6 * : CAS -Before- RAS Refresh Current ( RAS , UCAS or LCAS cycling @t RC =min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(V IH )=V CC -0.2V, Input low voltage(V IL )=0.2V, UCAS , LCAS =0.2V, DQ=Don ′t care, T RC =31.25us(4K/L-ver), 125us(1K/L-ver) T RAS =T RAS min~300ns ICCS : Self Refresh Current RAS = UCAS = LCAS =V IL , W = OE =A0 ~ A11=V CC -0.2V or 0.2V, DQ0 ~ DQ15=V CC -0.2V, 0.2V or Open Symbol Power Speed Max Units K 4E171612D K 4E151612D K 4E171611D K 4E151611D ICC1 Don ′t care -45 -5 0 -6 0 100 150 140 130 100 150 140 130 mA mA mA ICC2 Normal L Don ′t care 1 mA mA ICC3 Don ′t care -45 -5 0 -6 0 100 150 140 130 100 150 140 130 mA mA mA ICC4 Don ′t care -45 -5 0 -6 0 110 100 110 100 110 100 110 100 mA mA mA ICC5 Normal L Don ′t care 0.5 200 0.5 200 200 200 mA uA ICC6 Don ′t care -45 -5 0 -6 0 100 150 140 130 110 150 140 130 mA mA mA ICC7 L Don ′t care 300 200 350 250 uA ICCS L Don ′t care 150 150 200 200 uA

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D CAPACITANCE (T A =25 °C, V CC =5V or 3.3V, f=1MHz) Parameter Symbol Min Max Units Input capacitance [A0 ~ A11] C IN1 - 5 pF Input capacitance [ RAS , UCAS , LCAS , W , OE ] C IN2 - 7 pF Output capacitance [DQ0 - DQ15] C DQ - 7 pF Parameter Symbol -45 -5 0 -6 0 Units Notes Min Max Min Max Min Max Random read or write cycle time tRC 79 84 104 ns Read-modify-write cycle time tRWC 105 115 140 ns Access time from RAS tRAC 45 50 60 ns 3,4,10 Access time from CAS tCAC 14 15 17 ns 3,4,5 Access time from column address tAA 23/*20 25 30 ns 3,10 CAS to output in Low-Z tCLZ 3 3 3 ns 3 Output buffer turn-off delay from CAS tCEZ 3 13 3 13 3 15 ns 6,19 OE to output in Low-Z tOLZ 3 3 3 ns 3 Transition time (rise and fall) tT 2 50 2 50 2 50 ns 2 RAS precharge time tRP 30 30 40 ns RAS pulse width tRAS 45 10K 50 10K 60 10K ns RAS hold time tRSH 13 13 17 ns CAS hold time tCSH 36 40 50 ns CAS pulse width tCAS 7 / *6.5 10K 8 10K 10 10K ns 18 RAS to CAS delay time tRCD 19 31 20 35 20 43 ns 4 RAS to column address delay time tRAD 14 22 15 25 15 30 ns 10 CAS to RAS precharge time tCRP 5 5 5 ns Row address set-up time tASR 0 0 0 ns Row address hold time tRAH 9 10 10 ns Column address set-up time tASC 0 0 0 ns 11 Column address hold time tCAH 7 8 10 ns 11 Column address to RAS lead time tRAL 23 25 30 ns Read command set-up time tRCS 0 0 0 ns Read command hold time referenced to CAS tRCH 0 0 0 ns 8 Read command hold time referenced to RAS tRRH 0 0 0 ns 8 Write command hold time tWCH 8 10 10 ns Write command pulse width tWP 8 10 10 ns Write command to RAS lead time tRWL 10 13 15 ns Write command to CAS lead time tCWL 7 8 10 ns 14 AC CHARACTERISTICS (0 °C ≤T A ≤70 °C, See note 1,2) * KM416C1204DT-45 (5V, 1K Refresh) only

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D AC CHARACTERISTICS (Continued) * KM416C1204DT-45 (5V, 1K Refresh) only Parameter Symbol -45 -5 0 -6 0 Units Notes Min Max Min Max Min Max Data set-up time tDS 0 0 0 ns 9,17 Data hold time tDH 7 8 10 ns 9,17 Refresh period (1K, Normal) tREF 16 16 16 ms Refresh period (4K, Normal) tREF 64 64 64 ms Refresh period (L-ver) tREF 128 128 128 ms Write command set-up time tWCS 0 0 0 ns 7 CAS to W delay time tCWD 28 32 36 ns 7,13 RAS to W delay time tRWD 59 67 79 ns 7 Column address W delay time tAWD 37 42 49 ns 7 CAS precharge to W delay time tCPWD 39 47 54 ns 7 CAS set-up time ( CAS -before- RAS refresh) tCSR 5 5 5 ns 15 CAS hold time ( CAS -before- RAS refresh) tCHR 10 10 10 ns 16 RAS to CAS precharge time tRPC 5 5 5 ns Access time from CAS precharge tCPA 25 28 35 ns 3 Hyper Page mode cycle time tHPC 18 20 25 ns 18 Hyper Page read-modify-write cycle time tHPRWC 39 47 56 ns 18 CAS precharge time (Hyper Page cycle) tCP 7 / * 6. 5 8 10 ns 12 RAS pulse width (Hyper Page cycle) tRASP 45 200K 50 200K 60 200K ns RAS hold time from CAS precharge tRHCP 27 30 35 ns OE access time tOEA 13 13 15 ns 3 OE to data delay tOED 10 13 15 ns Output buffer turn off delay time from OE tOEZ 3 13 3 13 3 15 ns 6 OE command hold time tOEH 10 13 15 ns Output data hold time tDOH 4 5 5 ns Output buffer turn off delay from RAS tREZ 3 13 3 13 3 15 ns 6,19 Output buffer turn off delay from W tWEZ 3 13 3 13 3 15 ns 6 W to data delay tWED 15 15 15 ns OE to CAS hold time tOCH 5 5 5 ns CAS hold time to OE tCHO 5 5 5 ns OE precharge time tOEP 5 5 5 ns W pulse width (Hyper Page Cycle) tWPE 5 5 5 ns RAS pulse width ( C -B- R self refresh) tRASS 100 100 100 us 20,21,22 RAS precharge time ( C -B- R self refresh) tRPS 79 90 110 ns 20,21,22 CAS hold time ( C -B- R self refresh) tCHS -50 -50 -50 ns 20,21,22

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D NOTES An initial pause of 200us is required after power-up followed by any 8 RAS -only refresh or CAS -before- RAS refresh cycles before proper device operation is achieved. Input voltage levels are Vih/Vil. V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Transition times are measured between V IH (min) and V IL (max) and are assumed to be 2ns for all inputs. Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF. Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . Assumes that t RCD ≥tRCD (max). This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V oh or V ol . tWCS , tRWD , tCWD , tAWD and t CPWD are non restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥tWCS (min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWD ≥tCWD (min), tRWD ≥tRWD (min), tAWD ≥tAWD (min) and tCPWD ≥tCPWD (min), then the cycle is a read- modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle and read-modify-write cycles. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the specified tRAD (max) limit, then access time is controlled by tAA . K4 E17(5) 16 11 (2) D Truth Table RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE H X X X X Hi-Z Hi-Z Standby L H H X X Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z - 10.

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tASC , t CAH are referenced to the earlier CAS falling edge. tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle. tCWD is referenced to the later CAS falling edge at word read-modify-write cycle. tCWL is specified from W falling edge to the earlier CAS rising edge. tCSR is referenced to the earlier CAS falling edge before RAS transition low. tCHR is referenced to the later CAS rising edge after RAS transition low. tCSR tCHR RAS LCAS UCAS 22. 13. 19. 12. 11. tDS, tDH is independently specified for lower byte DQ(0-7), upper byte DQ(8-15) tASC ≥6ns, assume t T =2.0ns. If RAS goes to high before CAS high going, the open circuit condition of the output is achieved by CAS high going. If CAS goes to high before RAS high going, the open circuit condition of the output is achieved by RAS high going. If tRASS ≥100us, then RAS precharge time must use tRPS instead of tRP . For RAS -only refresh and burst CAS -before- RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed within 64ms/16ms before and after self refresh, in order to meet refresh specification. For distributed CAS -before- RAS with 15.6us interval, CAS -before- RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification. 18. 16. 15. 14. 21. 20. 17.

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tCRP RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - DQ0 ~ DQ7 COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRALtASR tRAH tASC tCAH tCRP tAA tOEA tCAC tCLZ tRAC OPEN tCEZ tRCH Don ′t care Undefined LCAS V IH - V IL - tCRP tCSH tRSHtRCD tCAS tRAD tRRH V OH - V OL - DQ8 ~ DQ15 tCAC tCLZ tRAC OPEN DATA-OUT DATA-OUT tCEZ tOEZ tOEZ tRCS WORD READ CYCLE tOLZ

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D NOTE : D IN = OPEN LOWER BYTE READ CYCLE RAS V IH - V IL - LCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - DQ0 ~ DQ7 COLUMN ADDRESS ROW ADDRESS tRAS tRC tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP tAA tOEA tCAC tCLZ tRAC OPEN DATA-OUT tOEZ tCEZ tRRH tRCH Don ′t care Undefined tCRP tRPC UCAS V IH - V IL - OPEN V OH - V OL - DQ8 ~ DQ15 tRCS tOLZ

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D NOTE : D IN = OPEN UPPER BYTE READ CYCLE RAS V IH - V IL - LCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V OH - V OL - DQ0 ~ DQ7 COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP tAA tOEA tCAC tCLZ tRAC OPEN DATA-OUT tOEZ tCEZ tRRH tRCH Don ′t care Undefined UCAS V IH - V IL - OPEN V OH - V OL - DQ8 ~ DQ15 tCRP tRPC tRCS tOLZ

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP Don ′t care WORD WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - tWCS V IH - V IL - DQ0 ~ DQ7 tDS V IH - V IL - DQ8 ~ DQ15 tCRP tCSH tRSHtRCD tCAS tCRP tWCH tWP tDH DATA-IN tDS tDH DATA-IN

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tCRP RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tRP tRAL tRAD tASR tRAH tASC tCAH Don ′t care LOWER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - tWCS V IH - V IL - DQ0 ~ DQ7 tDS V IH - V IL - DQ8 ~ DQ15 tCRP tCSH tRSHtRCD tCAS tWCH tWP tDH DATA-IN tCRP

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP Don ′t care UPPER BYTE WRITE CYCLE ( EARLY WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - tWCS V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tWCH tWP tDS tDH DATA-IN tCRP

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCRP Don ′t care WORD WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tCRPtRSHtRCD tCAS tCRP tRWL tWP tCWL tDH tDH DATA-IN COLUMN ADDRESS tOEHtOED tDS tDS DATA-IN tCSH tCAH

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tRP tRAL tRAD tASR tRAH tASC tCAH Don ′t care LOWER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - tRWL V IH - V IL - DQ0 ~ DQ7 tDS V IH - V IL - DQ8 ~ DQ15 tCRP tCSH tRSHtRCD tCAS tCRP tWP tCWL tDH DATA-IN tCRP tRPC tOEH tOED

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDRESS tRAS tRC tCRP tRP tCSH tRSHtRCD tCAS tRAL tRAD tASR tRAH tASC tCAH tCRP Don ′t care UPPER BYTE WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D OUT = OPEN Undefined LCAS V IH - V IL - V IH - V IL - V IH - V IL - tCRP tRWL tWP tCWL tDS tDH DATA-IN tOEH tOED DQ0 ~ DQ7 DQ8 ~ DQ15 tCRP

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tRWL RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR. tRAS tRWC tRP tRSHtRCD tCAS tCSH tRAD tASR tRAH tASC tCAH tCRP Don ′t care WORD READ - MODIFY - WRITE CYCLE Undefined LCAS V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ7 V I/OH - V I/OL - DQ8 ~ DQ15 tWP tCWL tDS tDH tRSHtRCD tCAS tCRP tAWD tCWD tOEA tRWD tOED tOEZtRAC tAA tOEZtRAC tAA tDS tOED tDH VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tCAC tCLZ tCAC tCLZ tOLZ tOLZ

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tRWL RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR. tRAS tRWC tRP tCSH tRAD tASR tRAH tASC tCAH tCRP Don ′t care LOWER-BYTE READ - MODIFY - WRITE CYCLE Undefined LCAS V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 tWP tCWL tDS tDH tRSHtRCD tCAS tCRP tAWD tCWD tOEA tRWD tOED tOEZtRAC tAA VALID DATA-OUT VALID DATA-IN tRPC tCAC tCLZ OPEN tOLZ

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tRWL RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRAS tRWC tRP tRSHtRCD tCAS tCSH tRAD tASR tRAH tASC tCAH tCRP Don ′t care UPPER-BYTE READ - MODIFY - WRITE CYCLE Undefined LCAS V IH - V IL - V OH - V OL - DQ0 ~ DQ7 V I/OH - V I/OL - DQ8 ~ DQ15 tWP tCWL tAWD tCWD tOEA tRWD tOEZtRAC tAA tDS tOED tDH VALID DATA-OUT VALID DATA-IN tCRP tRPC tCAC tCLZ OPEN tOLZ

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tASC tOLZ tCLZ tOLZ tCLZ RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP tRCD tCRP Don ′t care HYPER PAGE MODE WORD READ CYCLE Undefined LCAS V IH - V IL - V OH - V OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 COLUMN ADDRESS tCAS tCAS tCAS tCAS tCP tCP tCP tREZ tHPC tHPC tHPC tRHCPtCSH tRCD tCRP tCAS tCAS tCAS tCAS tCP tCP tCP tRAD tRCS tOEA tRCH tRRH COLUMN ADDRESS COLUMN ADDR tOEZ tOEP tCHO tAA tCPA tAA tCAC VALID DATA-OUT tOEP tOEZtRAC tCAC tDOH VALID DATA-OUT VALID DATA-OUT tOCH tCPA tAA tCAC tCAC tCPA tOEZ VALID DATA-OUT VALID DATA-OUT VALID DATA-OUT tOEP tOEZtRAC tCAC VALID DATA-OUT VALID DATA-OUT tOEZ VALID DATA-OUT VALID DATA-OUT tDOH tOEA tASR tRAH tASC tCAH tASC tCAH tCAH tCAHtASC tRAL

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tOEA tOLZ tCLZ RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP tCRP Don ′t care HYPER PAGE MODE LOWER BYTE READ CYCLE Undefined LCAS V IH - V IL - V OH - V OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 COLUMN ADDRESS tREZ tRHCPtCSH tRCD tCAS tCAS tCAS tCAS tCP tCP tCP tRAD tRCS tRCH tRRH COLUMN ADDRESS COLUMN ADDR tOEZ tOEP tCHO tCPAtCAC VALID DATA-OUT tOEP tOEZtRAC tCAC tDOH VALID DATA-OUT VALID DATA-OUT tOCH tCPA tCAC tCAC tCPA tOEZ VALID DATA-OUT VALID DATA-OUT OPEN tRPC tASR tRAH tASC tCAH tASC tCAH tCAH tASC tCAHtASC tAA tHPC tHPC tHPC tAAtAA tAA tOEA tRAL

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR. tRASP tRP tRCD tASR tCRP Don ′t care HYPER PAGE MODE UPPER BYTE READ CYCLE Undefined LCAS V IH - V IL - V OH - V OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 COLUMN ADDRESS tCAS tCAS tCAS tCAS tCP tCP tCP tREZ tHPC tHPC tHPC tRHCPtCSH tCRP tRAH tASC tCAH tCAH tCAH tASC tCAH tRCS tOEA tRCH tRRH COLUMN ADDRESS COLUMN ADDR. tOEZ tOEP tCHO tCPAtCAC VALID DATA-OUT tOEP tOEZtRAC tCAC tOLZ tCLZ tDOH VALID DATA-OUT VALID DATA-OUT tOCH tCPA tCAC tCAC tCPA tOEZ VALID DATA-OUT VALID DATA-OUT OPEN tASC tRPC tRPC tRAD tASC tAAtAA tAA tOEA tRAL

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP tRCD tASR tCRP Don ′t care HYPER PAGE MODE WORD WRITE CYCLE ( EARLY WRITE ) Undefined LCAS V IH - V IL - V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tCRP tHPC tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tCAS tCP tCAS tCP tCAS tRSH tRCD tCRP tHPC tHPC tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH VALID DATA-IN VALID DATA-IN VALID DATA-IN tDH tDH tDHtDStDStDS NOTE : D OUT = OPEN tHPC tRAL

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP tASR tCRP Don ′t care HYPER PAGE MODE LOWER BYTE WRITE CYCLE ( EARLY WRITE ) Undefined LCAS V IH - V IL - V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tRPC tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tRCD tCRP tHPC tHPC tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCS tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH NOTE : D OUT = OPEN tRAL

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tWCS RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP tASR tCRP Don ′t care HYPER PAGE MODE UPPER BYTE WRITE CYCLE ( EARLY WRITE ) Undefined LCAS V IH - V IL - V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tRPC tRHCP tRAD tRAH tCAH tCAH tASC tCAHtASC VALID DATA-IN tDS COLUMN ADDRESS COLUMN ADDRESS tRCD tCRP tHPC tHPC tCAS tCP tCAS tCP tCAS tRSH tCSH tASC tWP tWCH tWP tWCS tWCH tWP tWCS tWCH VALID DATA-IN VALID DATA-IN tDH tDS tDH tDS tDH NOTE : D OUT = OPEN tRAL

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ7 ROW ADDR tCSH tRASP tRP tASR Don ′t care HYPER PAGE MODE WORD READ - MODIFY - WRITE CYCLE Undefined tRCD tCP tRAD tCAH tWP tDH COL. ADDR COL. ADDR tCAS tCAS tCRP tASC tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED tASC tCLZ tOEA tCAC tAA tDH tOED LCAS V IH - V IL - tRCD tCP tCAS tCAS tCRP tCRP tCRP V I/OH - V I/OL - DQ8 ~ DQ15 VALID DATA-OUT tDH tAA tRAC tCLZ tCAC VALID DATA-IN VALID DATA-OUT VALID DATA-IN tCLZ tCAC tAA tDH tOEZ tOED tDS tDS tDS tOED tOEZ tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS tHPRWC tRSH tRWL tRCS tRAH

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tASC RAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ7 ROW ADDR tCSH tRASP tRP tASR Don ′t care HYPER PAGE MODE LOWER BYTE READ - MODIFY - WRITE CYCLE Undefined tRAD tCAH tWP tDH COL. ADDR COL. ADDR tASC tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED tCLZ tOEA tCAC tAA tDH tOED tRWL tRCD tCP tCAS tCAS tCRP tCRP tCRP V I/OH - V I/OL - DQ8 ~ DQ15 tDS tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS tRPC tRSH OPEN LCAS V IH - V IL - UCAS V IH - V IL - tHPRWC tRCS tOLZ tOLZ tRAH

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tASC tCRP RAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - V I/OH - V I/OL - DQ0 ~ DQ7 ROW ADDR tCSH tRASP tRP tASR Don ′t care HYPER PAGE MODE UPPER BYTE READ - MODIFY - WRITE CYCLE Undefined tRAD tCAH tWP tDH COL. ADDR COL. ADDR tCAH tRAL tRCS tCWL tCWD tAWD tRWD tWP tCWD tAWD tCWL tAA tRAC tOEA tCLZ tCAC tOEZ tCPWD tOED tCLZ tOEA tCAC tAA tDH tOED tRWL tRCD tCP tCAS tCAS tCRP tCRP V I/OH - V I/OL - DQ8 ~ DQ15 tDS tOEZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN tDS tRPC tRSH OPEN LCAS V IH - V IL - UCAS V IH - V IL - tHPRWC tASC tRCS tRAH tOLZ tOLZ

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D HYPER PAGE READ AND WRITE MIXED CYCLE RAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - COLUMN ADDRESS ROW ADDR tRASP tRP Don ′t care Undefined V I/OH - V I/OL - DQ0 ~ DQ7 tWEZ tCP tHPC tHPC tHPC tRCD tRAH tASC tCAH tCAH tCAH tASC tCAH tRCHtRCS tRCS tRCH tASC COLUMN ADDRESS COL. ADDR VALID DATA-OUT tREZtAA tWCS VALID DATA-OUT VALID DATA-OUT VALID DATA-IN tRAC COL. ADDR tCAS tASR tCAStCAS tCAS tASC tCP tRCH tWCH tWPE tCLZ tCPA tWED tAA tWEZ tDS tDH tCAC tOEA tCP tHPC tHPC tCAS tCAStCAS tCAS tCP V I/OH - V I/OL - DQ8 ~ DQ15 tWEZ VALID DATA-OUT tREZtAA VALID DATA-OUT VALID DATA-OUT VALID DATA-IN tRAC tAA tWEZ tDS tDH tCAC tOEA LCAS V IH - V IL - UCAS V IH - V IL - tCP tHPC tCP READ( tCAC ) READ( tCPA ) WRITE READ( tAA ) tRAD tRHCP tRAL

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tCRP OPEN RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - ROW ADDR tRC tRP tASR tCRP RAS - ONLY REFRESH CYCLE LCAS V IH - V IL - tRAS tRAH NOTE : W , OE , D IN = Don ′t care D OUT = OPEN tRPC CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - UCAS V IH - V IL - tRC tRP LCAS V IH - V IL - tRAS tRPC tCP tRPC tCSR tCHR tCP tCSR tCHR tCEZ OPEN V OH - V OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 Don ′t care tRP Undefined

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tOEZ DATA-IN DATA-OUT tRP RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - ROW ADDRESS tRAS tRC tCHRtRCD tRSH tRAD tASR tRAH tASC tCRP Don ′t care HIDDEN REFRESH CYCLE ( READ ) Undefined LCAS V IH - V IL - V OH - V OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 tRSHtRCDtCRP tWRH COLUMN ADDRESS tOEA tRAS tRC tCHR tCAH tRCS tAA tRAC tCLZ tCAC DATA-OUT tCEZ OPEN OPEN tRP tREZ tWEZ tOLZ tRAL

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D tWCS tRP RAS V IH - V IL - UCAS V IH - V IL - A V IH - V IL - W V IH - V IL - OE V IH - V IL - ROW ADDRESS tRAS tRC tCHRtRCD tRSH tRAD tASR tRAH tASC tCRP Don ′t care HIDDEN REFRESH CYCLE ( WRITE ) Undefined LCAS V IH - V IL - V IH - V IL - DQ0 ~ DQ7 V IH - V IL - DQ8 ~ DQ15 tRSHtRCD tCRP tWRH COLUMN ADDRESS tRAS tRC tCHR tCAH tWRP tDS NOTE : D OUT = OPEN tWP tWCH DATA-IN tDH tDS DATA-IN tDH tRP

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D OPEN CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE , A = Don ′t care RAS V IH - V IL - UCAS V IH - V IL - tRPS LCAS V IH - V IL - tRASS tRPC tCP tRPC tCSR tCEZ OPEN V OH - V OL - DQ0 ~ DQ7 V OH - V OL - DQ8 ~ DQ15 tCHS tCP tCSR tCHS tRP Don ′t care Undefined

K4E171611D, K4E151611D CMOS DRAMK4E171612D, K4E151612D

42 SOJ 400mil

0 .4 0 0 ( 1 0 .1 6 ) 0 .4 3 5 ( 1 1 .0 6 ) 0 .4 4 5 ( 1 1 .3 0 ) 1.080 (27.43) 1.070 (27.19) MAX 1.091 (27.71) M A X 0 .1 4 8 ( 3 .7 6 ) 0.032 (0.81) 0.026 (0.66) 0.021 (0.53) 0.015 (0.38) 0.027 (0.69) 0.012 (0.30) 0.006 (0.15) 0 .3 6 0 ( 9 .1 5 ) 0 .3 8 0 ( 9 .6 5 ) MIN #42 Units : Inches (millimeters) 50(44) TSOP(II) 400mil Units : Inches (millimeters) MAX 0.047 (1.20) MIN 0.002 (0.05) 0.018 (0.45) 0.010 (0.25) 0.821 (20.85) 0.829 (21.05) 0.841 (21.35) MAX 0.010 (0.25) 0.004 (0.10) 0 .4 0 0 ( 1 0 .1 6 ) 0 .4 7 1 ( 1 1 .9 6 ) 0 .4 5 5 ( 1 1 .5 6 ) 0~8 0.030 (0.75) 0.018 (0.45) TYP 0.010 (0.25) O PACKAGE DIMENSION