K4D64163HF-TC60

K4D64163HF SAMSUNG | Alldatasheet

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Technical content

Revision 1.1 August 2002 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM Samsung Electronics reserves the right to change products or specification without notice.

Revision History

Revision 1.1 (August 6, 2002)

• Typo corrected Revision 1.0 (June 17, 2002)  Defined DC spec Revision 0.1 (May 20, 2002) - Target Spec  Typo corrected Revision 0.0 (April 30, 2002) - Target Spec  Defined Target Specification

The K4D64163H is 67,108,864 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 1.2GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.  3.3V + 5% power supply for device operation  2.5V + 5% power supply for I/O interface  SSTL_2 compatible inputs/outputs  4 banks operation  MRS cycle with address key programs -. Read latency 3 (clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave)  All inputs except data & DM are sampled at the positive going edge of the system clock  Differential clock input  No Wrtie-Interrupted by Read Function GENERAL DESCRIPTION

FEATURES

 2 DQS’s ( 1DQS / Byte )  Data I/O transactions on both edges of Data strobe  DLL aligns DQ and DQS transitions with Clock transition  Edge aligned data & data strobe output  Center aligned data & data strobe input  DM for write masking only  Auto & Self refresh  64ms refresh period (4K cycle)  66pin TSOP-II  Maximum clock frequency up to 300MHz  Maximum data rate up to 600Mbps/pin FOR 1M x 16Bit x 4 Bank DDR SDRAM 1M x 16Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL

ORDERING INFORMATION

Part NO. Max Freq. Max Data Rate Interface Package K4D64163HF-TC33 300MHz 600Mbps/pin SSTL_2 66 pin TSOP-II K4D64163HF-TC36 275MHz 550Mbps/pin K4D64163HF-TC40 250MHz 500Mbps/pin K4D64163HF-TC50 200MHz 400Mbps/pin K4D64163HF-TC60 166MHz 333Mbps/pin

PIN CONFIGURATION (Top View) PIN DESCRIPTION CK,CK Differential Clock Input BA 0, BA1 Bank Select Address CKE Clock Enable A 0 ~A11 Address Input CS Chip Select DQ 0 ~ DQ15 Data Input/Output RAS Row Address Strobe V DD Power CAS Column Address Strobe V SS Ground WE Write Enable V DDQ Power for DQ’s LDQS,UDQS Data Strobe V SSQ Ground for DQ’s LDM,UDM Data Mask NC No Connection

66 PIN TSOP(II)

(400mil x 875mil) (0.65 mm Pin Pitch) 66V DD DQ 0 VDDQ DQ 1 DQ 2 VSSQ DQ 3 DQ 4 VDDQ DQ 5 DQ 6 VSSQ BA 0 CS RAS CAS WE LDM VDDQ DQ 7 VDD AP/A10 BA 1 NC LDQS NC NC NC VDD VSS DQ 15 VSSQ DQ 14 DQ 13 VDDQ DQ 12 DQ 11 VSSQ DQ 10 DQ 9 VDDQ A11 CKE CK UDM V REF VSSQ DQ 8 VSS NC UDQS NC VSS CK NC NC

INPUT/OUTPUT FUNCTIONAL DESCRIPTION *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin. Symbol Type Function CK, CK*1 Input The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ ’s and DM’s that are sampled on both edges of the DQS. CKE Input Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS Input CS enables the command decoder when low and disabled the com- mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. CAS Input Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. WE Input Enables write operation and row precharge. Latches data in starting from CAS, WE active. LDQS,(U)DQS Input/Output Data Strobe : Output with read data, input with write data. Edge- aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. LDM,UDM Input Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. DM pins include dummy loading internally, to matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. DQ 0 ~ DQ15 Input/Output Data inputs/Outputs are multiplexed on the same pins. BA 0, BA1 Input Selects which bank is to be active. A0 ~ A11 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7. VDD /VSS Power Supply Power and ground for the input buffers and core logic. VDDQ /VSSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Power Supply Reference voltage for inputs, used for SSTL interface. NC/RFU No connection/ Reserved for future use This pin is recommended to be left "No connection" on the device

BLOCK DIAGRAM (1Mbit x 16I/O x 4 Bank) Bank Select Timing Register Address Register Refresh Counter Row Buffer Row DecoderCol. Buffer Data Input Register Serial to parallel 1Mx16 1Mx16 1Mx16 1Mx16 Sense AMP 2-bit prefetch Output Buffer I/O Control Column Decoder Latency & Burst Length Programming Register Strobe Gen. CK,CK ADDR LCKE CK,CK CKE CS RAS CAS WE LDM LDMiCK,CK LCAS LRAS LCBR LWE LWCBR LRAS LCBR CK, CK 32 16 LWE LDMi x16 DQi Data Strobe Intput Buffer DLL UDM

 Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. FUNCTIONAL DESCRIPTION Power up & Initialization Sequence Command 0 1234567891 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 tRP 2 Clock min. precharge ALL Banks 2nd Auto Refresh Mode Register Set Any Command tRFC 1st Auto Refresh tRFC EMRS MRS 2 Clock min. DLL Reset precharge ALL Banks tRP Inputs must be stable for 200us 200 Clock min. 2 Clock min. CK,CK

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS , RAS, CAS and WE (The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A 0 ~ A2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. MODE REGISTER SET(MRS) Address Bus Mode Register CAS Latency A 6 A 5 A 4 Latency 000R e s e r v e d 001R e s e r v e d 010R e s e r v e d 011 3 100R e s e r v e d 101R e s e r v e d 110R e s e r v e d 111R e s e r v e d Burst Length A 2 A 1 A 0 Burst Type Sequential Interleave 0 0 0 Reserve Reserve 001 2 2 010 4 4 011 8 8 1 0 0 Reserve Reserve 1 0 1 Reserve Reserve 1 1 0 Reserve Reserve 1 1 1 Reserve Reserve Burst Type A 3 Type

0 Sequential

1 Interleave* RFU(Reserved for future use)

should stay "0" during MRS cycle. MRS Cycle Command *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. CK, CK Precharge NOP NOPMRS NOPNOP 201 5 34 8 67 AnyNOP All Banks Command tRP tMRD =2 tCK BA 1 BA 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RFU 0 RFU DLL TM CAS Latency BT Burst Length BA 0 A n ~ A0 0M R S 1E M R S DLL A 8 DLL Reset 0N o 1Y e s Test Mode A 7 mode 0N o r m a l 1T e s t NOP

The extended mode register stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by assert- ing low on CS , RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS , RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes. A 0 DLL Enable

0 Enable

BA 0 A n ~ A0 0M R S 1E M R S EXTENDED MODE REGISTER SET(EMRS) Address Bus Extended *1 : RFU(Reserved for future use) should stay "0" during EMRS cycle. A 6 A 1 Output Driver Impedence Control

01 Weak

11 Matched

RFU 1 RFU D.I.C RFU D.I.C DLL BA 1 BA 0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode Register

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Note : POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to VSS =0V, TA=0 to 65°C) Parameter Symbol Min Typ Max Unit Note Device Supply voltage V DD 3.135 3.3 3.465 V 1 Output Supply voltage V DDQ 2.375 2.50 2.625 V 1 Reference voltage V REF 0.49*VDDQ -0 . 5 1 * V DDQ V2 Termination voltage Vtt V REF -0.04 V REF VREF +0.04 V 3 Input logic high voltage V IH(DC) VREF +0.15 - V DDQ +0.30 V 4 Input logic low voltage V IL(DC) -0.30 - V REF -0.15 V 5 Output logic high voltage V OH Vtt+0.76 - - V I OH =-15.2mA Output logic low voltage V OL - - Vtt-0.76 V I OL =+15.2mA Input leakage current I IL -5 - 5 uA 6 Output leakage current I OL -5 - 5 uA 6 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss V DD -1.0 ~ 3.6 V Voltage on VDD supply relative to Vss V DDQ -0.5 ~ 3.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 1.0 W Short circuit current I OS 50 mA 1. Under all conditions VDDQ must be less than or equal to VDD . 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ , VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. Note :

Note : 1. Measured with outputs open. 2. Refresh period is 64ms. Parameter Symbol Test Condition Version Unit Note Operating Current (One Bank Active) ICC1 Burst Lenth=2 tRC ≥ tRC (min) IOL =0mA, tCC = tCC (min) 210 200 190 170 160 mA 1 Precharge Standby Current in Power-down mode ICC2 P CKE ≤ VIL(max), tCC = tCC (min) 5m A Precharge Standby Current in Non Power-down mode ICC2 N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = tCC (min) 110 105 95 80 70 mA Active Standby Current power-down mode ICC3 P CKE ≤ VIL(max), tCC = tCC (min) 110 105 95 80 70 mA Active Standby Current in in Non Power-down mode ICC3 N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = tCC (min) 160 150 140 120 100 mA Operating Current ( Burst Mode) ICC4 tRC ≥ tRFC (min)tRC ≥ tRFC (min) Page Burst, All Banks activated. 390 370 350 320 300 mA Refresh Current I CC5 tRC ≥ tRFC (min) 210 200 190 180 170 mA 2 Self Refresh Current I CC6 CKE ≤ 0.2V 2 mA Recommended operating conditions Unless Otherwise Noted, TA =0 to 65°C) 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same Note : AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to VSS =0V, VDD =3.3V+ 5%, VDDQ =2.5V+ 5%,TA=0 to 65°C) Parameter Symbol Min Typ Max Unit Note Input High (Logic 1) Voltage; DQ V IH VREF +0.35 - - V Input Low (Logic 0) Voltage; DQ V IL -- V REF -0.35 V Clock Input Differential Voltage; CK and CK VID 0.7 - V DDQ +0.6 V 1 Clock Input Crossing Point Voltage; CK and CKVIX 0.5*VDDQ -0.2 - 0.5*V DDQ +0.2 V 2

R T=50Ω Output C LOAD =30pF (Fig. 1) Output Load Circuit Z0=50Ω VREF =0.5*VDDQ Vtt=0.5*VDDQ DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Symbol Value Unit Decoupling Capacitance between VDD and VSS C DC1 0.1 + 0.01 uF Decoupling Capacitance between VDDQ and VSSQ C DC2 0.1 + 0.01 uF 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip. Note : AC OPERATING TEST CONDITIONS (VDD =3.3V±5% , TA= 0 to 65°C) Parameter Value Unit Note Input reference voltage for CK(for single ended) 0.50*V DDQ V CK and CK signal maximum peak swing 1.5 V CK signal minimum slew rate 1.0 V/ns Input Levels(VIH/VIL)V REF +0.35/VREF -0.35 V Input timing measurement reference level V REF V Output timing measurement reference level V tt V Output load condition See Fig.1 CAPACITANCE (VDD =3.3V, TA= 25°C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance( CK, CK )C IN1 1.0 5.0 pF Input capacitance(A0~A 11, BA0~BA 1)C IN2 1.0 4.0 pF Input capacitance ( CKE, CS , RAS,CAS, WE ) C IN3 1.0 4.0 pF Data & DQS input/output capacitance(DQ0~DQ 31)C OUT 1.0 6.5 pF Input capacitance(DM0 ~ DM3) C IN4 1.0 6.5 pF

-33 -36 -40 -50 -60 Unit NoteMin Max Min Max Min Max Min Max Min Max QS-In setup time tWPRES 0-0-0-0-0- n s lock half period tHP tCLmin or tCHmin tCLmin or tCHmin tCLmin or tCHmin tCLmin or tCHmin tCLmin or tCHmin -n s 1 ata output hold time from DQStQH tHP-0.4 tHP-0.4 - tHP-0.4 - tHP- 0.45 -t H P - 0 . 5- n s 1 ote 1 : The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst ase output vaild window even then the clock duty cycle applied to the device is better than 45/55% A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax

AC CHARACTERISTICS (II) K4D64163HF-TC33 Frequency Cas Latency tRC tRFC tRAS tRCD tRP tRRD tDAL Unit 300MHz (3.0ns ) 3 17 20 11 6 6 2 9 tCK 275MHz ( 3.6ns ) 3 16 18 10 5 5 2 8 tCK 250MHz ( 4.0ns ) 3 14 16 9 5 5 2 8 tCK 200MHz ( 5.0ns ) 3 12 14 8 4 4 2 7 tCK 166MHz ( 6.0ns ) 3 10 12 7 3 3 2 6 tCK (Unit : Number of Clock) AC CHARACTERISTICS (I) Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM Parameter Symbol -33 -36 -40 -50 -60 Unit NoteMin Max Min Max Min Max Min Max Min Max Row cycle time tRC 1 7-1 6-1 4-1 2-1 0- tCK Refresh row cycle time tRFC 2 0-1 8-1 6-1 4-1 2- tCK Row active time tRAS 11 100K 10 100K 9 100K 8 100K 7 100K tCK RAS to CAS delay tRCD 6-5-5-4-3- tCK Row precharge time tRP 6-5-5-4-3- tCK Row active to Row active tRRD 2-2-2-2-2- tCK Last data in to Row precharge @Normal Precharge tWR 3-3-3-2-2- tCK 1 Last data in to Row precharge @Auto Precharge tWR_A 3-3-3-3-3- tCK 1 Last data in to Read commandtCDLR 2-2-2-2-2- tCK 1 Col. address to Col. address tCCD 1-1-1-1-1- tCK Mode register set cycle timetMRD 3-2-2-2-2- tCK Auto precharge write recovery + Precharge tDAL 9-8-8-7-6- tCK Exit self refresh to read com-tXSR 2 0 0-2 0 0-2 0 0-2 0 0-2 0 0- tCK Power down exit time tPDEX 2tCK +tIS - 2tCK +tIS - 1tCK +tIS - 1tCK +tIS - 1tCK +tIS - ns K4D64163HF-TC36 Frequency Cas Latency tRC tRFC tRAS tRCD tRP tRRD tDAL Unit 275MHz (3.6ns ) 3 16 18 10 5 5 2 8 tCK 250MHz ( 4.0ns ) 3 14 16 9 5 5 2 8 tCK 200MHz ( 5.0ns ) 3 12 14 8 4 4 2 7 tCK 166MHz ( 6.0ns ) 3 10 12 7 3 3 2 6 tCK K4D64163HF-TC40 Frequency Cas Latency tRC tRFC tRAS tRCD tRP tRRD tDAL Unit 250MHz ( 4.0ns ) 3 14 16 9 5 5 2 8 tCK 200MHz ( 5.0ns ) 3 12 14 8 4 4 2 7 tCK 166MHz ( 6.0ns ) 3 10 12 7 3 3 2 6 tCK

ACTIVEA ACTIVEB WRITEA WRITEB 13 14 15 16 17 18 19 20 21 BAa BAb Ca Cb BAa Ca 91 0 1 1 1 2 PRECH BAa Ra Normal Write Burst (@ BL=4) Multi Bank Interleaving Write Burst (@ BL=4) BAa Ra Ra BAb Rb Rb tRAS tRC tRP tRRD COMMAND DQS DQ WE DM CK, CK A10/AP ADDR (A0~A11) BA[1:0] ACTIVEA WRITEA Da0 Da1 Da2 Da3 Simplified Timing @ BL=4 Db0 Db1 Db3Da0 Da1 Da2 Da3 Db2 K4D64163HF-TC50 Frequency Cas Latency tRC tRFC tRAS tRCD tRP tRRD tDAL Unit 200MHz ( 5.0ns ) 3 12 14 8 4 4 2 7 tCK 166MHz ( 6.0ns ) 3 10 12 7 3 3 2 6 tCK K4D64163HF-TC60 Frequency Cas Latency tRC tRFC tRAS tRCD tRP tRRD tDAL Unit 166MHz ( 6.0ns ) 3 10 12 7 3 3 2 6 tCK

PACKAGE DIMENSIONS (66pin TSOP-II) Units : Millimeters 22.22±0.10 0.125 (0.80) 10.16±0.10 0×~8× #1 #33 #66 #34 (1.50) (1.50) 0.65±0.08 1.00±0.10 1.20MAX 11.76±0.20 (10×)(10×) +0.075 -0.035 (0.80)

0.10 MAX

0.075 MAX[]

0.05 MIN

(10×) (10×) (R0.15) 0.210±0.05 0.665±0.05 (R0 .15) (4×) (R0.25) (R0 .25) 0.45~0.75 0.25TYP NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY