K4D553238F-GC33

K4D553238F SAMSUNG | Alldatasheet

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256M GDDR SDRAM K4D553238F-GC - 1 - Rev 1.3 (Mar. 2005) 256Mbit GDDR SDRAM Revision 1.3 March 2005 Samsung Electronics reserves the right to change products or specification without notice. INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

256M GDDR SDRAM K4D553238F-GC - 2 - Rev 1.3 (Mar. 2005)

Revision History

Revision 1.3(March 11, 2005)

• Typo corrected Revision 1.2(February 23, 2005)
• Typo corrected Revision 1.1 (December 29, 2004)
• Typo corrected Revision 1.0 (November 11, 2004)
• Defined DC specification
• Changed AC spec format Revision 0.0 (September 7, 2004) - Target Spec
• Defined target specification

256M GDDR SDRAM K4D553238F-GC - 3 - Rev 1.3 (Mar. 2005) The K4D553238F is 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 32 bits, fabricated with SAMSUNG ’s high performance CMOS technology. Sync hronous features with Data Strobe allow extremely high performance up to 2.8GB/ s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programma ble latencies allow the device to be useful for a variety of high performance memory system applications.

• 2.5V ± 5% power supply for device operation
• 2.5V ± 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs -. Read latency 4, 5 and 6 (clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock
• Differential clock input GENERAL DESCRIPTION

FEATURES

• No Wrtie-Interrupted by Read Function
• 4 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 350MHz
• Maximum data rate up to 700Mbps/pin FOR 2M x 32Bit x 4 Bank DDR SDRAM 2M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL

ORDERING INFORMATION

• K4D553238F-VC is the Lead Free package part number. Part NO. Max Freq. Max Data Rate Interface Package K4D553238F-GC2A 350MHz 700Mbps/pin SSTL_2 144-Ball FBGAK4D553238F-GC33 300MHz 600Mbps/pin K4D553238F-GC36 275MHz 550Mbps/pin

256M GDDR SDRAM K4D553238F-GC - 4 - Rev 1.3 (Mar. 2005) PIN CONFIGURATION (Top View) PIN DESCRIPTION CK,CK Differential Clock Input BA 0, BA1 Bank Select Address CKE Clock Enable A 0 ~A11 Address Input CS Chip Select DQ 0 ~ DQ31 Data Input/Output RAS Row Address Strobe V DD Power CAS Column Address Strobe V SS Ground WE Write Enable V DDQ Power for DQ’s DQS Data Strobe V SSQ Ground for DQ’s DM Data Mask NC No Connection RFU Reserved for Future Use MCL Must Connect Low DQS0 VSS RFU1 Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSS Thermal VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSSVSSVSSVSS VSS RFU 2A5 DQ4 DQ6 DQ7 DQ17 DQ19 DQS2 DQ21 DQ22 CAS RAS CS DM0 VDDQ DQ5 VDDQ DQ16 DQ18 DM2 DQ20 DQ23 WE NC NC NC VDD VDDQ VDDQ NC VDDQ VDDQ VDD NC BA0 BA1 DQ3 VDDQ DQ31 DQ1 A10 VDD VDD VDD DQ2 VDDQ VDD A11 DQ0 VDDQ VDD DQ29 DQ30 DQ28 VDDQ NC VSS VDDQ VDDQ NC VDDQ VDDQ VDD CK A8/AP DM3 VDDQ DQ26 VDDQ DQ15 DQ13 DM1 DQ11 DQ9 NC CK CKE DQS3 DQ27 DQ25 DQ24 DQ14 DQ12 DQS1 DQ10 DQ8 NC VREF 23456789 1 0 1 1 1 2 1 3 B C D E F G H J K L M N NOTE: 1. RFU1 is reserved for A12 2. RFU2 is reserved for BA2 3. VSS Thermal balls are optional MCL

256M GDDR SDRAM K4D553238F-GC - 5 - Rev 1.3 (Mar. 2005) INPUT/OUTPUT FUNCTIONAL DESCRIPTION *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin. Symbol Type Function CK, CK*1 Input The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ ’s and DM’s that are sampled on both edges of the DQS. CKE Input Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS Input CS enables the command decoder when low and disabled the com- mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. CAS Input Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. WE Input Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQS0 ~ DQS3 Input/Output Data input and output are synchronized with both edge of DQS. DQS0 for DQ0 ~ DQ7, DQS1 for DQ8 ~ DQ15, DQS2 for DQ16 ~ DQ23, DQS3 for DQ24 ~ DQ31. DM0 ~ DM3 Input Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM0 for DQ0 ~ DQ7, DM1 for DQ8 ~ DQ15, DM2 for DQ16 ~ DQ23, DM3 for DQ24 ~ DQ31. DQ0 ~ DQ31 Input/Output Data inputs/Outputs are multiplexed on the same pins. BA0, BA1 Input Selects which bank is to be active. A0 ~ A11 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7, CA9 Column address CA8 is used for auto precharge. VDD/VSS Power Supply Power and ground for the input buffers and core logic. VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Power Supply Reference voltage for inputs, used for SSTL interface. NC/RFU No connection/ Reserved for future use This pin is recommended to be left "No connection" on the device MCL Must Connect Low Must connect low

256M GDDR SDRAM K4D553238F-GC - 6 - Rev 1.3 (Mar. 2005) BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank) Bank Select Timing Register Address Register Refresh Counter Row Buffer Row DecoderCol. Buffer Data Input Register Serial to parallel 2Mx32 2Mx32 2Mx32 2Mx32 Sense AMP 2-bit prefetch Output Buffer I/O Control Column Decoder Latency & Burst Length Programming Register Strobe Gen. CK,CK ADDR LCKE CK,CK CKE CS RAS CAS WE DMi LDMiCK,CK LCAS LRAS LCBR LWE LWCBR LRAS LCBR CK, CK 64 32 LWE LDMi x32 DQi Data Strobe Intput Buffer DLL (DQS0~DQS3)

256M GDDR SDRAM K4D553238F-GC - 7 - Rev 1.3 (Mar. 2005)

• Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL (Minimum 20 clock cycles are recommended prior to MRS command, however not mandatory just in case tMRD met) *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order FUNCTIONAL DESCRIPTION Power up & Initialization Sequence Command tRP tMRD precharge ALL Banks 2nd Auto Refresh Mode Register Set Any Command tRFC 1st Auto Refresh tRFC EMRS MRS tMRD. DLL Reset precharge ALL Banks tRP Inputs must be stable for 200us 200 Clock min. tMRD CK,CK * When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL. ~~~~ ~~~~ ~~~~ ~~~~

256M GDDR SDRAM K4D553238F-GC - 8 - Rev 1.3 (Mar. 2005) The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. T he mode register is written by asserting low on CS , RAS, CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements du ring operation as long as all banks are in the idle state. The mode register is divided into various fi elds depending on functionality. The burst length uses A 0 ~ A 2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. MODE REGISTER SET(MRS) Address Bus Mode Register CAS Latency A6 A5 A4 Latency 000R e s e r v e d 001R e s e r v e d 010R e s e r v e d 011 3 100 4 101R e s e r v e d 110R e s e r v e d 111R e s e r v e d Burst Length A2 A1 A0 Burst Type Sequential Interleave 0 0 0 Reserved Reserved 001 2 2 010 4 4 011 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved Burst Type A3 Type

0 Sequential

1 Interleave

• RFU(Reserved for future use) should stay "0" during MRS cycle. MRS Cycle Command *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. CK, CK Precharge NOP NOPMRS NOPNOP 201 6 1 2 10 11 AnyNOP All Banks Command tRP tMRD=4 tCK BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RFU 0 RFU DLL TM CAS Latency BT Burst Length BA0 An ~ A0 0M R S 1E M R S DLL A8 DLL Reset 0N o 1Y e s Test Mode A7 mode

0 Normal

~~~

0 Enable

1 Disable

Figure 7. Extended Mode Register set *1 : RFU(Reserved for future use) should stay "0" during EMRS cycle.

00 N/A Do not use

01 Weak 60%

10 N/A Do not use

11 Full 100%

256M GDDR SDRAM K4D553238F-GC - 10 - Rev 1.3 (Mar. 2005) Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Note : ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss V DD -1.0 ~ 3.6 V Voltage on VDD supply relative to Vss V DDQ -0.5 ~ 3.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 3.3 W Short circuit current I OS 50 mA POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C) Parameter Symbol Min Typ Max Unit Note Device Supply voltage V DD 2.375 2.5 2.625 V 1 Output Supply voltage V DDQ 2.375 2.5 2.625 V 1 Reference voltage V REF 0.49*VDDQ - 0.51*V DDQ V2 Termination voltage Vtt V REF-0.04 V REF VREF+0.04 V 3 Input logic high voltage V IH(DC) VREF+0.15 - V DDQ+0.30 V 4 Input logic low voltage V IL(DC) -0.30 - V REF-0.15 V 5 Output logic high voltage V OH Vtt+0.76 - - V I OH=-15.2mA, 7 Output logic low voltage V OL - - Vtt-0.76 V I OL=+15.2mA, 7 Input leakage current I IL -5 - 5 uA 6 Output leakage current I OL -5 - 5 uA 6 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. 7. Output logic high voltage and low voltage is depend on output channel condition. Note :

256M GDDR SDRAM K4D553238F-GC - 11 - Rev 1.3 (Mar. 2005) DC CHARACTERISTICS Note : 1. Measured with outputs open. 2. Refresh period is 32ms. Parameter Symbol Test Condition Version Unit Note -2A -33 -36 Operating Current (One Bank Active) ICC1 Burst Lenth=2 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) 340 310 290 mA Precharge Standby Current in Power-down mode ICC2P CKE ≤ VIL(max), tCC= tCC(min) 15 15 15 mA Precharge Standby Current in Non Power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) 75 70 65 mA Active Standby Current power-down mode ICC3P CKE ≤ VIL(max), tCC= tCC(min) 70 65 60 mA Active Standby Current in Non Power-down mode ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) 240 220 210 mA Operating Current ( Burst Mode) ICC4 IOL=0mA ,tCC= tCC(min), Page Burst, All Banks activated. 400 370 360 mA Refresh Current I CC5 tRC ≥ tRFC(min) 380 340 320 mA 1 Self Refresh Current I CC6 CKE ≤ 0.2V 10 10 10 mA Operating Current (4Bank interleaving) ICC7 Burst Length=4 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) 620 560 530 mA Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C) 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same Note : AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C) Parameter Symbol Min Typ Max Unit Note Input High (Logic 1) Voltage ;DQ V IH VREF+0.35 - - V Input Low (Logic 0) Voltage; DQ V IL -- V REF-0.35 V Clock Input Differential Voltage; CK and CK VID 0.7 - V DDQ+0.6 V 1 Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2 - 0.5*V DDQ+0.2 V 2

256M GDDR SDRAM K4D553238F-GC - 12 - Rev 1.3 (Mar. 2005) RT=50Ω Output CLOAD=30pF (Fig. 1) Output Load Circuit Z0=50Ω VREF =0.5*VDDQ Vtt=0.5*VDDQ DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Symbol Value Unit Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01 uF Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip. Note : AC OPERATING TEST CONDITIONS (TA= 0 to 65°C) Note 1 : In case of differential clocks(CK and CK ), input reference voltage for clock is a CK and CK’s crossing point. Parameter Value Unit Note Input reference voltage for CK(for single ended) 0.50*V DDQ V1 CK and CK signal maximum peak swing 1.5 V CK signal minimum slew rate 1.0 V/ns Input Levels(VIH/VIL)V REF+0.4/VREF-0.4 V Input timing measurement reference level V REF V Output timing measurement reference level V tt V Output load condition See Fig.1 CAPACITANCE (TA= 25°C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance( CK, CK )C IN1 1.0 5.0 pF Input capacitance(A0~A11, BA0~BA1)C IN2 1.0 4.0 pF Input capacitance ( CKE, CS, RAS,CAS, WE ) CIN3 1.0 4.0 pF Data & DQS input/output capacitance(DQ0~DQ31)C OUT 1.0 6.5 pF Input capacitance(DM0 ~ DM3) C IN4 1.0 6.5 pF

256M GDDR SDRAM K4D553238F-GC - 13 - Rev 1.3 (Mar. 2005) 13 4 6 7 tCL tCK CK, CK DQS DQ CS DM tIS tIH tDS tDH tRPSTtRPRE Db0 Db1 tDQSS tDQSH tDQSL tCH Qa1 Qa2 COMMAND READA WRITEB tDQSQ tWPRES tWPREH tDQSCK tAC Simplified Timing @ BL=2, CL=4 AC CHARACTERISTICS *1. The cycle to cycle jitter over 1~6 cycle short term jitter. Parameter Symbol -2A -33 -36 Unit NoteMin Max Min Max Min Max CK cycle time CL=3 tCK - 4 - 10 - 10 ns CL=4 2.86 3.3 3.6 ns Data strobe edge to Dout edge tDQSQ - 0.35 - 0.35 - 0.40 ns 1 DQS-In setup time tWPRES 0 - 0 - 0 - ns DQS-in hold time tWPREH 0.35 - 0.35 - 0.35 - tCK Address and Control input setup tIS 0.8 - 0.8 - 0.9 - ns Address and Control input hold tIH 0.8 - 0.8 - 0.9 - ns DQ and DM setup time to DQS tDS 0.35 - 0.35 - 0.40 - ns DQ and DM hold time to DQS tDH 0.35 - 0.35 - 0.40 - ns Clock half period tHP tCLmin or tCHmin tCLmin or tCHmin tCLmin or tCHmin -n s 1 Data Hold skew factor tQHS - 0.4 - 0.4 - 0.45 ns Data output hold time from DQS tQH tHP-tQHS - tHP-tQHS - tHP-tQHS - ns 1 Jitter over 1~6 clock cycle error tJ*1 - 75 - 85 - 95 ps Cycle to cyde duty cycle error tDCERR - 75 - 85 - 95 ps Rise and fall times of CK tR, tF - 600 - 700 - 700 ps

256M GDDR SDRAM K4D553238F-GC - 14 - Rev 1.3 (Mar. 2005) Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax tQH Timing (CL4, BL2) tHP CK, CK DQS DQ CS 2501 COMMAND READA tQH Qa0 tDQSQ(max) tDQSQ(max) 3 4 Qa1 VALID NOP NOP NOP NOP NOP NOP VALID tIS tIS CK, CK CKE Command Exit Powr Down mode Enter Power Down mode (Read or Write operation must not be in progress) 3tCK Power Down Timing

256M GDDR SDRAM K4D553238F-GC - 15 - Rev 1.3 (Mar. 2005) AC CHARACTERISTICS (I) Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM 2. The number of clock of tRP is restricted by the number of clock of tRAS and tRP 3. The number of clock of tWR_A is fixed. It can’t be changed by tCK 4. tRCDWR is equal to tRCDRD-2tCK and the number of clock can not be lower than 2tCK. 5. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer unconditionally. Parameter Symbol -2A -33 -36 Unit NoteMin Max Min Max Min Max Row cycle time tRC 42.9 - 42.9 - 46.8 - ns 2,5 Refresh row cycle time tRFC 48.6 - 49.5 - 54 - ns 5 Row active time tRAS 28.6 100K 29.7 100K 32.4 100K ns 5 RAS to CAS delay for Read tRCDRD 13.2 - 13.2 - 14.4 - ns 5 RAS to CAS delay for Write tRCDWR 6.6 - 6.6 - 7.2 - ns 4 Row precharge time tRP 13.2 - 13.2 - 14.4 - ns 5 Row active to Row active tRRD 9.9 - 9.9 - 10.8 - ns 5 Last data in to Row precharge tWR 14.3 - 16.5 - 18 - ns 5 Last data in to Row precharge @Auto Precharge tWR_A 5 - 5 - 5 - tCK 3 Auto precharge write recovery + Precharge tDAL 10 - 9 - 9 - tCK 3,5 Last data in to Read command tCDLR 2 - 2 - 2 - tCK 1 Col. address to Col. address tCCD 1 - 1 - 1 - tCK Mode register set cycle time tMRD 2 - 2 - 2 - tCK Exit self refresh to read command tXSR 200 - 200 - 200 - tCK Power down exit time tPDEX 3tCK+ tIS - 3tCK+ tIS - 3tCK+ tIS -n s Refresh interval time tREF 7.8 - 7.8 - 7.8 - us AC CHARACTERISTICS (II) K4D553238F-GC2A Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit 350MHz ( 2.86ns ) 4 15 17 10 5 3 5 4 10 tCK 300MHz ( 3.3ns ) 4 13 15 9 4 2 4 3 9 tCK 275MHz ( 3.6ns ) 4 13 15 9 4 2 4 3 9 tCK K4D553238F-GC33 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit 300MHz ( 3.3ns ) 4 13 15 9 4 2 4 3 9 tCK 275MHz ( 3.6ns ) 4 13 15 9 4 2 4 3 9 tCK K4D553238F-GC36 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit 275MHz ( 3.6ns ) 4 13 15 9 4 2 4 3 9 tCK

256M GDDR SDRAM K4D553238F-GC - 16 - Rev 1.3 (Mar. 2005) 012345678 BAa Ra Ra tRCD ACTIVEA ACTIVEB WRITEA WRITEB 13 14 15 16 17 18 19 20 21 BAa BAb Ca Cb BAa Ca 91 0 1 1 1 2 PRECH BAa Ra Normal Write Burst (@ BL=4) Multi Bank Interleaving Write Burst (@ BL=4) BAa Ra Ra BAb Rb Rb tRAS tRC tRP tRRD COMMAND DQS DQ WE DM CK, CK A8/AP ADDR (A0~A7, BA[1:0] A9,A10) ACTIVEA WRITEA Da0 Da1 Da2 Da3 Simplified Timing(2) @ BL=4 Db0 Db1 Db3Da0 Da1 Da2 Da3 Db2

256M GDDR SDRAM K4D553238F-GC - 17 - Rev 1.3 (Mar. 2005) PACKAGE DIMENSIONS (144-Ball FBGA) Unit : mm 12.0 12.0 0.80.8 0.35 ± 0.05

1.40 Max

<Top View> <Bottom View> 0.45 ± 0.05 0.8x11=8.8 0.40 0.8x11=8.8 0.40 B C D E F G H J K L M N 13 12 11 10 9 8 7 6 5 4 3 2 A1 INDEX MARK A1 INDEX MARK0.10 Max