K4D263238M-QC45

K4D263238M SAMSUNG | Alldatasheet

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Technical content

Revision 1.3 August 2001 1M x 32Bit x 4 Banks with Bi-directional Data Strobe and DLL Double Data Rate Synchronous RAM Samsung Electronics reserves the right to change products or specification without notice.

Revision History

Revision 1.3 (August 2, 2001)

• Removed K4D263238M-QC40 with VDD&VDDQ=2.8V
• Changed VDD&VDDQ of K4D263238M-QC45 from 2.8V to 2.5V.
• Changed tCK(max) from 7ns to 10ns. Revision 1.2 (July 12, 2001)
• Corrected CAS latency of K4D263238M-QC45 from CL3 to CL4
• The specification for the 222MHz/250MHz is preliminary one. Revision 1.1 (March 5, 2000)
• Added K4D263238M-QC40 with VDD&VDDQ=2.8V
• Changed VDD/VDDQ of K4D263238M-QC45 from 2.5V to 2.8V. Accordingly, DC current characteristics values have been changed. - Changed CAS latency of K4D263238M-QC45 from CL4 to CL3.
• Changed tWPREH of K4D263238M-QC50 from 0.3tCK to 0.25tCK

Revision 1.0 (December 13, 2000)

• Defined capacitance values
• Chagned tRCDWR of K4D263238M-QC60 from 1tCK to 2tCK Revision 0.5 (December 8, 2000)
• Changed AC input level from Vref + 0.31V to Vref + 0.35V
• Changed tRC/tRFC/tRAS/tRP/tRCDRD/tRCDWR from ns unit based from clock unit based. Revision 0.4 (November 29, 2000) - Preliminary
• Removed K4D263238M-QC40
• Several AC parameters of K4D263238M-QC45 have been changed - Changed tDQSCK & tAC from 0.6ns to 0.7ns - Corrected tDAL from 5tCK to 6tCK
• Several AC parameters of K4D263238M-QC50 have been changed - Changed tQH from tHP-0.6ns to tHP-0.45ns. - Changed tDQSCK & tAC from 0.6ns to 0.7ns - Corrected tDAL from 5tCK to 6tCK
• Several AC parameters of K4D263238M-QC55 have been changed - Changed tDQSCK & tAC from 0.6ns to 0.75ns - Corrected tRCDWR from 5.5ns to 11ns. Corrected tDAL from 5tCK to 6tCK
• Changed tQH of K4D263238M-QC60 from tHP-0.75ns to tHP-0.5ns
• Add DC Characteristics value
• Define V IH (max) / V IL (min) as a note in Power & DC operating Condition table
• Changed refresh cycle time from 16ms to 32ms.Accordingly, tREF has been changed from 3.9us to 7.8us.
• Changed I IL ,I OL test condition from 0V < V IN < V DD +0.3V to 0V < V IN < V DD . Revision 0.3 (June 8, 2000)
• Removed Block Write function Revision 0.2 (April 10, 2000)
• Separated tRCD into tRCDRD and tRCDWR - tRCDRD: Row to Column delay for READ - tRCDWR: Row to Column delay at WRITE Revision 0.1 (March 16, 2000)
• Define the spec based on Vdd&Vddq=2.5V
• Maximum target frequency upto 250MHz@CL4
• Removed Write Interrupt by Read function Revision 0.0 (December 27, 1999) - Target Spec
• Defined Target Specification

The K4D263238 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNG ′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 1.8GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.

• 2.5V ± 5% power supply
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs -. Read latency 3 ,4 (clock) -. Burst length (2, 4, 8 and Full page) -. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive going edge of the system clock
• Differential clock input
• No Write Interrupted by Read function GENERAL DESCRIPTION

FEATURES

• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32 ms refresh period ( 4 K cycle)
• 100pin TQFP package
• Maximum clock frequency up to 222MHz
• Maximum data rate up to 444Mbps/pin FOR 1M x 32Bit x 4 Bank DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL

ORDERING INFORMATION

Part NO. Max Freq. Max Data Rate Interface Package K4D263238M-QC45 222MHz 444Mbps/pin SSTL_2 100 TQFP K4D263238M-QC50 200MHz 400Mbps/pin K4D263238M-QC55 183MHz 366Mbps/pin K4D263238M-QC60 166MHz 333Mbps/pin

PIN CONFIGURATION (Top View) PIN DESCRIPTION CK, CK Differential Clock Input BA 0 , BA 1 Bank Select Address CKE Clock Enable A 0 ~A 1 1 Address Input CS Chip Select DQ 0 ~ DQ 31 Data Input/Output RAS Row Address Strobe V DD Power CAS Column Address Strobe V SS Ground WE Write Enable V DDQ Power for DQ ′s DQS Data Strobe V SSQ Ground for DQ ′s DMi Data Mask MCL Must Connect Low RFU Reserved for Future Use DQ29 VSSQ DQ30 DQ31 VSS VDDQ N.C N.C N.C N.C N.C VSSQ RFU DQS VDDQ VDD DQ0 DQ1 VSSQ DQ2 100 D Q 3 V D D Q D Q 4 D Q 5 V S S Q D Q 6 D Q 7 V D D Q D Q 1 6 D Q 1 7 V S S Q D Q 1 8 D Q 1 9 V D D Q V D D V S S D Q 2 0 D Q 2 1 V S S Q D Q 2 2 D Q 2 3 V D D Q D M 0 D M 2 W E C A S R A S C S B A 0 B A 1 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 VSS N.C N.C N.C N.C N.C N.C N.C A11 A10 VDD

100 Pin TQFP

0.65 mm pin Pitch D Q 2 8 V D D Q D Q 2 7 D Q 2 6 V S S Q D Q 2 5 D Q 2 4 V D D Q D Q 1 5 D Q 1 4 V S S Q D Q 1 3 D Q 1 2 V D D Q V S S V D D D Q 1 1 D Q 1 0 V S S Q D Q 9 D Q 8 V D D Q V R E F D M 3 D M 1 C K C K C K E M C L A 8 ( A P ) 8 0 7 9 7 8 7 7 7 6 7 5 7 4 7 3 7 2 7 1 7 0 6 9 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 5 2 5 1

INPUT/OUTPUT FUNCTIONAL DESCRIPTION *1 : The timing reference point for the differential clocking is the cross point of CK and CK . For any applications using the single ended clocking, apply V REF to CK pin. Symbol Type Function CK, CK *1 Input The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ ′s and DM ′s that are sampled on both edges of the DQS. CKE Input Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS Input CS enables the command decoder when low and disabled the com- mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. CAS Input Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. WE Input Enables write operation and row precharge. Latches data in starting from CAS , WE active. DQS Input/Output Data input and output are synchronized with both edge of DQS. DM 0 ~ DM 3 Input Data In mask. Data In is masked by DM Latency=0 when DM is high in burst write. DM 0 for DQ 0 ~ DQ 7, DM 1 for DQ 8 ~ DQ 15, DM 2 for DQ 16 ~ DQ 23, DM 3 for DQ 24 ~ DQ 31. DQ 0 ~ DQ 31 Input/Output Data inputs/Outputs are multiplexed on the same pins. BA 0 , BA 1 Input Selects which bank is to be active. A 0 ~ A 1 1 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA 0 ~ RA 1 1 , Column addresses : CA 0 ~ CA 7 . Column address CA 8 is used for auto precharge. V DD /V SS Power Supply Power and ground for the input buffers and core logic. V DDQ /V SSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. V REF Power Supply Reference voltage for inputs, used for SSTL interface. MCL Must Connect Low Must connect Low

BLOCK DIAGRAM (1Mbit x 32I/O x 4 Bank) Bank Select Timing Register Address Register Refresh Counter Row Buffer Row DecoderCol. Buffer Data Input Register Serial to parallel 1M x32 1M x32 1M x32 1M x32 Sense AMP 2-bit prefetch Output Buffer I/O Control Column Decoder Latency & Burst Length Programming Register Strobe Gen. CK, CK ADD R LCKE CK, CK CKE CS RAS CAS WE DMi LDMiCK, CK LCAS LRAS LCBR LWE LWCBR LRAS LCBR CK, CK 64 32 LWE LDMi x32 DQi Data Strobe Intput Buffer DLL

• Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK, CK ), apply NOP and take CKE to be high. 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. * 1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. FUNCTIONAL DESCRIPTION Power up & Initialization Sequence Command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 tRP 2 Clock min. precharge ALL Banks 2nd Auto Refresh Mode Register Set Any Command tRFC 1st Auto Refresh tRFC EMRS MRS 2 Clock min. DLL Reset precharge ALL Banks tRP CK CK Inputs must be stable for 200 us 200 Clock min. 2 Clock min.

The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. The mode register is written by asserting low on CS , RAS , CAS and WE (The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A 0 ~ A 11 and BA 0 , BA 1 in the same cycle as CS , RAS , CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on functionality. The burst length uses A 0 ~ A 2 , addressing mode uses A 3 , CAS latency(read latency from column address) uses A 4 ~ A 6 . A 7 is used for test mode. A 8 is used for DLL reset. A 7, A 8 , BA 0 and BA 1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. MODE REGISTER SET(MRS) Address Bus Mode CAS Latency A 6 A 5 A 4 Latency 0 0 0 Reserve d 0 0 1 Reserve d 0 1 0 Reserved 0 1 1 3 1 0 0 4 1 0 1 Reserve d 1 1 0 Reserve d 1 1 1 Reserve d Burst Length A 2 A 1 A 0 Burst Type Sequential Interleave 0 0 0 Reserve Reserve 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserve Reserve 1 0 1 Reserve Reserve 1 1 0 Reserve Reserve 1 1 1 Full page Reserve Burst Type A 3 Type

0 Sequential

1 Interleave

• RFU(Reserved for future use) should stay "0" during MRS cycle. MRS Cycle Command *1: MRS can be issued only at all banks precharge state. *2: Minimum tRP is required to issue MRS command. CK, CK Precharge NOP NOPMRS NOPNOP 20 1 53 4 86 7 AnyNOP All Banks Command t RP tMRD =2 t CK BA 1 BA 0 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 RFU 0 RFU DLL TM CAS Latency BT Burst Length BA 0 A n ~ A 0

0 MRS

1 EMRS

1 Yes

0 Normal

1 Test

except A0,A1,A6 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.

0 Enable

1 Disable

Figure 7. Extend Mode Register set

Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN , V OUT -0.5 ~ 3.6 V Voltage on V DD supply relative to Vss V DD -1.0 ~ 3.6 V Voltage on V DD supply relative to Vss V DDQ -0.5 ~ 3.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 2.0 W Short circuit current IOS 50 mA Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Note : POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to V SS =0V, T A =0 to 65 °C) Parameter Symbol Min Typ Max Unit Note Device Supply voltage V DD 2.375 2.50 2.625 V 1 Output Supply voltage V DDQ 2.375 2.50 2.625 V 1 Reference voltage V REF 0.49*V DDQ - 0.51*V DDQ V 2 Termination voltage Vtt V REF -0.04 V REF V REF +0.04 V 3 Input logic high voltage V IH V REF +0.15 - V DDQ +0.30 V 4 Input logic low voltage V IL -0.30 - V REF -0.15 V 5 Output logic high voltage V OH Vtt+0.76 - - V I OH =-15.2mA Output logic low voltage V OL - - Vtt-0.76 V I OL =+15.2mA Input leakage current I IL -5 - 5 uA 6 Output leakage current IOL -5 - 5 uA 6 1. Under all conditions V DDQ must be less than or equal to V DD . 2. V REF is expected to equal 0.50*V DDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the V REF may not exceed + 2% of the DC value. Thus, from 0.50*V DDQ , V REF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. V tt of the transmitting device must track V REF of the receiving device. 4. V IH (max.)= V DDQ +1.5V for a pulse and it which can not be greater than 1/3 of the cycle rate. 5. V IL (min.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V ≤ V IN ≤ V DD is acceptable. For all other pins that are not under test V IN =0V. Note :

Note: 1. Measured with outputs open. 2. Refresh period is 32ms. Parameter Sym- bol Test Condition Version Unit Note -45* -50 -55 -60 Operating Current (One Bank Active) ICC1 Burst Lenth=2 tRC ≥ tRC (min) IOL =0mA, tCC = tCC (min) 310 260 260 260 mA 1 Precharge Standby Current in Power-down mode ICC2 P CKE ≤ V IL (max), tCC = tCC (min) 90 80 mA Precharge Standby Current in Non Power-down mode ICC2 N CKE ≥ V IH (min), CS ≥ V IH (min), tCC = tCC (min). 155 135 130 125 mA Active Standby Current power-down mode ICC3 P CKE ≤ V IL (max), tCC = tCC (min) 105 95 mA Active Standby Current in in Non Power-down mode ICC3 N CKE ≥ VIH(min), CS ≥ VIH(min), tCC = t CC (min) . 190 160 150 140 mA Operating Current ( Burst Mode) ICC4 I OL =0mA , tCC = tCC (min), Page Burst, All Banks activated. 660 550 500 460 mA Refresh Current ICC5 tRC ≥ tRFC (min) 380 330 320 320 mA 2 Self Refresh Current ICC6 CKE ≤ 0.2V 5 4 mA Recommended operating conditions Unless Otherwise Noted, T A =0 to 65 °C) AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to V SS =0V, V DD / V DDQ =2.5V + 5% , T A =0 to 65 °C) Parameter Symbol Min Typ Max Unit Note Input High (Logic 1) Voltage; DQ V IH V REF +0.35 - - V Input Low (Logic 0) Voltage; DQ V IL - - V REF -0.35 V Clock Input Differential Voltage; CK and CK V ID 0.7 - V DDQ +0.6 V 1 Clock Input Crossing Point Voltage; CK and CK V IX 0.5*V DDQ -0.2 - 0.5*V DDQ +0.2 V 2 1. V ID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of V IX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same Note :

AC OPERATING TEST CONDITIONS ( V DD / V DDQ =2.5V + 5% , T A = 0 to 65 °C) Parameter Value Unit Note Input reference voltage for CK(for single ended) 0.50*V DDQ V CK and CK signal maximum peak swing 1.5 V CK signal minimum slew rate 1.0 V/ns Input Levels(V IH /V IL ) V REF +0.35/V REF -0.35 V Input timing measurement reference level V REF V Output timing measurement reference level V tt V Output load condition See Fig.1 R T =50 Ω Output C LOAD =30pF (Fig. 1) Output Load Circuit Z0=50 Ω V REF =0.5*V DDQ V tt =0.5*V DDQ DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Symbol Value Unit Decoupling Capacitance between V DD and V SS C DC1 0.1 + 0.01 uF Decoupling Capacitance between V DDQ and V SSQ C DC2 0.1 + 0.01 uF 1. V DD and V DDQ pins are separated each other. All V DD pins are connected in chip. All V DDQ pins are connected in chip. 2. V SS and V SSQ pins are separated each other All V SS pins are connected in chip. All V SSQ pins are connected in chip. Note : CAPACITANCE (V DD =2.5V, T A = 25 °C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance( CK, CK ) C IN1 1.0 5.0 pF Input capacitance(A 0 ~A 10 , BA 0 ~BA 1 ) C IN2 1.0 4.0 pF Input capacitance ( CKE, CS , RAS , CAS , WE ) C IN3 1.0 4.0 pF Data & DQS input/output capacitance(DQ 0 ~DQ 31 ) C OUT 1.0 6.0 pF Input capacitance(DM0 ~ DM3) C IN4 1.0 6.0 pF

CK, CK DQS DQ CS DM 2 5 tIS tIH tDS tDH 0 1 tRPSTtRPRE Db0 Db1 tDQSS tDQSH tCH Da1 Da2 tWPST COMMAND READA WRITEB tDQSQ t WPRES tWPREH tDQSCK tAC AC CHARACTERISTICS Simplified Timing @ BL=2, CL=3 Parameter Symbol -45* -50 -55 -60 Unit NoteMin Max Min Max Min Max Min Max CK cycle time CL=3 tCK - 10 5.0 10 5.5 10 6.0 10 ns CL=4 4.5 ns Data strobe edge to Dout edge tDQSQ - +0.45 - +0.45 - +0.5 - +0.5 ns 1 DQS-In setup time tWPRES 0 - 0 - 0 - 0 - ns DQS-in hold time tWPREH 0.25 - 0.25 - 0.25 - 0.25 - tCK Address and Control input setup tIS 1.0 - 1.0 - 1.1 - 1.1 - ns Address and Control input hold tIH 1.0 - 1.0 - 1.1 - 1.1 - ns DQ and DM setup time to DQS tDS 0.45 - 0.45 - 0.5 - 0.5 - ns DQ and DM hold time to DQS tDH 0.45 - 0.45 - 0.5 - 0.5 - ns Clock half period tHP tCLmin or tCHmin tCLmin or tCHmin tCLmin or tCHmin tCLmin or tCHmin - ns 1 Data output hold time from DQS tQH tHP-0.45 - tHP-0.45 - tHP-0.5 - tHP-0.5 - ns 1

Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case output valid window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is defined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax tQH Timing (CL3, BL2) 1 3 4 tHP CK, CK DQS DQ CS 2 50 1 COMMAND READA tQH Da0 tDQSQ(max) tDQSQ(max) Da1

AC CHARACTERISTICS (I) Note :1 For normal write operation, even numbers of Din are to be written inside DRAM Parameter Symbol -45* -50 -55 -60 Unit NoteMin Max Min Max Min Max Min Max Row cycle time tRC 13 - 12 - 12 - 10 - tCK Refresh row cycle time tRFC 15 - 14 - 14 - 12 - tCK Row active time tRAS 9 100K 8 100K 8 100K 7 100K tCK RAS to CAS delay for Read tRCDRD 4 - 4 - 4 - 3 - tCK RAS to CAS delay for Write tRCDWR 2 2 2 - 2 - tCK Row precharge time tRP 4 - 4 - 4 - 3 - tCK Row active to Row active tRRD 2 - 2 - 2 - 2 - tCK Last data in to Row precharge tWR 2 - 2 - 2 - 2 - tCK 1 Last data in to Read com- mand tCDLR 2 - 2 - 2 - 2 - tCK 1 Col. address to Col. address tCCD 1 - 1 - 1 - 1 - tCK Mode register set cycle time tMRD 2 - 2 - 2 - 2 - tCK Auto precharge write recovery + Precharge tDAL 6 - 6 - 6 - 5 - tCK Exit self refresh to read com- tXSR 200 - 200 - 200 - 200 - tCK Power down exit time tPDEX 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - 1tCK+tIS - ns Refresh interval time tREF 7.8 - 7.8 - 7.8 - 7.8 - us

AC CHARACTERISTICS (II) K4D263238M-QC45* Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD Unit 222MHz ( 4.5ns ) 4 13 15 9 4 2 4 2 tCK 200MHz ( 5.0ns ) 3 12 14 8 4 2 4 2 tCK 183MHz ( 5.5ns ) 3 12 14 8 4 2 4 2 tCK 166MHz ( 6.0ns ) 3 10 12 7 3 2 3 2 tCK 143MHz ( 7.0ns ) 3 9 11 6 3 2 3 2 tCK K4D263238M-QC50 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD Unit 200MHz ( 5.0ns ) 3 12 14 8 4 2 4 2 tCK 183MHz ( 5.5ns ) 3 12 14 8 4 2 4 2 tCK 166MHz ( 6.0ns ) 3 10 12 7 3 2 3 2 tCK 143MHz ( 7.0ns ) 3 9 11 6 3 2 3 2 tCK K4D263238M-QC55 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD Unit 183MHz ( 5.5ns ) 3 12 14 8 4 2 4 2 tCK 166MHz ( 6.0ns ) 3 10 12 7 3 2 3 2 tCK 143MHz ( 7.0ns ) 3 9 11 6 3 2 3 2 tCK K4D263238M-QC60 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD Unit 166MHz ( 6.0ns ) 3 10 12 7 3 2 3 2 tCK 143MHz ( 7.0ns ) 3 9 11 6 3 2 3 2 tCK (Unit : Number of Clock)

ACTIVEA ACTIVEB WRITEA WRITEB Db0 Db1 Db3 13 14 15 16 17 18 19 20 21 BAa BAb Ca Cb BAa Ca 9 10 11 12 PRECH BAa Ra Da0 Da1 Da2 Da3 Normal Write Burst (@ BL=4) Multi Bank Interleaving Write Burst (@ BL=4) BAa Ra Ra BAb Rb Rb Db2 tRAS tRC tRP tRRD COMMAND DQS DQ WE DM CK, CK A8/AP ADDR (A0~A7, BA[1:0] A9~,A11) ACTIVEA WRITEA Da0 Da1 Da2 Da3 Simplified Timing(2) @ BL=4, CL=3

0.825 0 .5 7 5 0.65

0.13 MAX

PACKAGE DIMENSIONS (TQFP) Dimensions in Millimeters

0.10 MAX

0 ~ 7 ° 17.20 ± 0.20 14.00 ± 0.10 23.20 ± 0.20 1.00 ± 0.10

1.20 MAX *

0.05 MIN

0.80 ± 0.20 0.09~0.20 #100 0.30 ± 0.08 20.00 ± 0.10