K4D261638

K4D261638F SAMSUNG | Alldatasheet

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128M GDDR SDRAM K4D261638F 128Mbit GDDR SDRAM Revision 1.2 January 2004 2M x 16Bit x 4 Banks Graphic Double Data Rate Samsung Electronics reserves the right to change products or specification without notice. Synchronous DRAM

128M GDDR SDRAM K4D261638F

Revision History

Revision 1.2 (January 30, 2004)

• Changed tWR & tWR_A of K4D261638F-TC25/2A/33/36 from 3tCK to 4tCK
• Changed tRC of K4D261638F-TC25 from 17tCK to 18tCK
• Changed tRC of K4D261638F-TC2A/33/36 from 15tCK to 16tCK
• Changed tRAS of K4D261638F-TC25 from 12tCK to 13tCK.
• Changed tRAS of K4D261638F-TC2A/33/36 from 10tCK to 11tCK.
• Changed tDAL of K4D261638F-TC25/2A/33/36 from 8tCK to 9tCK Revision 1.1 (January 7, 2004)
• Added K4D261638F-TC25 in the spec. Revision 1.0 (December 5, 2003) Revision 0.9 (October 14, 2003) - Preliminary Spec
• Defined DC spec Revision 0.1 (October 2, 2003) - Target Spec
• Added Lead free package part number in the datasheet Revision 0.0 (August 6, 2003) - Target Spec
• Defined Target Specification

128M GDDR SDRAM K4D261638F The K4D261638F is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG ’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 1.6GB/s/ chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and program mable latencies allow the device to be useful for a variety of high performance memory system applications.

• 2.5V + 5% power supply for device operation
• 2.5V + 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs -. Read latency 3, 4 and 5(clock) -. Burst length (2, 4 and 8) -. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function GENERAL DESCRIPTION

FEATURES

• 2 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 66pin TSOP-II
• Maximum clock frequency up to 400MHz
• Maximum data rate up to 800Mbps/pin FOR 2M x 16Bit x 4 Bank DDR SDRAM 2M x 16Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL

ORDERING INFORMATION

K4D261638F-LC is the Lead Free package part number. For the K4D261638F-TC25/2A, VDD & VDDQ = 2.8V+0.1V Part NO. Max Freq. Max Data Rate Interface Package K4D261638F-TC25 400MHz 800Mbps/pin SSTL_2 66pin TSOP-II K4D261638F-TC2A 350MHz 700Mbps/pin K4D261638F-TC33 300MHz 600Mbps/pin K4D261638F-TC36 275MHz 550Mbps/pin K4D261638F-TC40 250MHz 500Mbps/pin K4D261638F-TC50 200MHz 400Mbps/pin

128M GDDR SDRAM K4D261638F PIN CONFIGURATION (Top View) PIN DESCRIPTION CK,CK Differential Clock Input BA 0, BA1 Bank Select Address CKE Clock Enable A 0 ~A11 Address Input CS Chip Select DQ 0 ~ DQ15 Data Input/Output RAS Row Address Strobe V DD Power CAS Column Address Strobe V SS Ground WE Write Enable V DDQ Power for DQ’s L(U)DQS Data Strobe V SSQ Ground for DQ’s L(U)DM Data Mask NC No Connection RFU Reserved for Future Use

66 PIN TSOP(II)

(400mil x 875mil) (0.65 mm Pin Pitch) 66V DD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ BA0 CS RAS CAS WE LDM VDDQ DQ7 VDD AP/A10 BA1 NC LDQS NC NC NC VDD VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ A11 CKE CK UDM V REF VSSQ DQ8 VSS NC UDQS NC VSS CK NC NC

128M GDDR SDRAM K4D261638F INPUT/OUTPUT FUNCTIONAL DESCRIPTION *1 : The timing reference point for the differential clocking is the cross point of CK and CK. For any applications using the single ended clocking, apply VREF to CK pin. Symbol Type Function CK, CK*1 Input The differential system clock Input. All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are sampled on both edges of the DQS. CKE Input Activates the CK signal when high and deactivates the CK signal when low. By deactivating the clock, CKE low indicates the Power down mode or Self refresh mode. CS Input CS enables the command decoder when low and disabled the com- mand decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS Input Latches row addresses on the positive going edge of the CK with RAS low. Enables row access & precharge. CAS Input Latches column addresses on the positive going edge of the CK with CAS low. Enables column access. WE Input Enables write operation and row precharge. Latches data in starting from CAS, WE active. LDQS,UDQS Input/Output Data input and output are synchronized with both edge of DQS. For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on DQ8-DQ15. LDM,UDM Input Data in Mask. Data In is masked by DM Latency=0 when DM is high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons to the data on DQ8-DQ15. DQ 0 ~ DQ15 Input/Output Data inputs/Outputs are multiplexed on the same pins. BA0, BA1 Input Selects which bank is to be active. A0 ~ A11 Input Row/Column addresses are multiplexed on the same pins. Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA8. VDD/VSS Power Supply Power and ground for the input buffers and core logic. VDDQ/VSSQ Power Supply Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Power Supply Reference voltage for inputs, used for SSTL interface. NC/RFU No connection/ Reserved for future use This pin is recommended to be left "No connection" on the device

128M GDDR SDRAM K4D261638F BLOCK DIAGRAM (2Mbit x 16I/O x 4 Bank) Bank Select Timing Register Address Register Refresh Counter Row Buffer Row DecoderCol. Buffer Data Input Register Serial to parallel 2Mx16 2Mx16 2Mx16 2Mx16 Sense AMP 2-bit prefetch Output Buffer I/O Control Column Decoder Latency & Burst Length Programming Register Strobe Gen. CK,CK ADDR LCKE CK,CK CKE CS RAS CAS WE LDM LDMiCK,CK LCAS LRAS LCBR LWE LWCBR LRAS LCBR CK, CK 32 16 LWE LDMi x16 DQi Data Strobe Intput Buffer DLL UDM

128M GDDR SDRAM K4D261638F

• Power-Up Sequence DDR SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and keep CKE at low state (All other inputs may be undefined) - Apply VDD before VDDQ . - Apply VDDQ before VREF & VTT 2. Start clock and maintain stable condition for minimum 200us. 3. The minimum of 200us after stable power and clock(CK,CK ), apply NOP and take CKE to be high . 4. Issue precharge command for all banks of the device. 5. Issue a EMRS command to enable DLL *1 6. Issue a MRS command to reset DLL. The additional 200 clock cycles are required to lock the DLL. *1,2 7. Issue precharge command for all banks of the device. 8. Issue at least 2 or more auto-refresh commands. 9. Issue a mode register set command with A8 to low to initialize the mode register. *1 The additional 200cycles of clock input is required to lock the DLL after enabling DLL. *2 Sequence of 6&7 is regardless of the order. FUNCTIONAL DESCRIPTION Power up & Initialization Sequence Command 0 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 9 tRP 2 Clock min. precharge ALL Banks 2nd Auto Refresh Mode Register Set Any Command tRFC 1st Auto Refresh tRFC EMRS MRS 2 Clock min. DLL Reset precharge ALL Banks tRP Inputs must be stable for 200us 200 Clock min. 2 Clock min. CK,CK * When the operating frequency is changed, DLL reset should be required again. After DLL reset again, the minimum 200 cycles of clock input is needed to lock the DLL.

128M GDDR SDRAM K4D261638F The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs CAS latency, addressing mode, burst length, test mode, DLL reset and vari ous vendor specific options to make DDR SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after EMRS setting for proper operation. Th e mode register is written by asserting low on CS , RAS , CAS and WE(The DDR SDRAM should be in active mode with CKE already high prior to writing into the mode register). The state of address pins A0 ~ A11 and BA0, BA1 in the same cycle as CS, RAS, CAS and WE going low is written in the mode register. Minimum two clock cycles are requested to complete the write operation in the mode register. The mode register contents can be changed using the same command an d clock cycle requirements during operati on as long as all banks are in the idle state. The mode register is divided into various fiel ds depending on functionality. The burst length uses A 0 ~ A 2, addressing mode uses A3, CAS latency(read latency from column address) uses A4 ~ A6. A7 is used for test mode. A8 is used for DLL reset. A7,A8, BA0 and BA1 must be set to low for normal MRS operation. Refer to the table for specific codes for various burst length, addressing modes and CAS latencies. MODE REGISTER SET(MRS) Address Bus Mode Register CAS Latency A6 A5 A4 Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 011 3 100 4 101 5 1 1 0 Reserved 1 1 1 Reserved Burst Length A2 A1 A0 Burst Type Sequential Interleave 0 0 0 Reserve Reserve 001 2 2 010 4 4 011 8 8 1 0 0 Reserve Reserve 1 0 1 Reserve Reserve 1 1 0 Reserve Reserve 1 1 1 Reserve Reserve Burst Type A3 Type

0 Sequential

1 Interleave

• RFU(Reserved for future use) should stay "0" during MRS cycle. MRS Cycle Command *1 : MRS can be issued only at all banks precharge state. *2 : Minimum tRP is required to issue MRS command. CK, CK Precharge NOP NOPMRS NOPNOP 201 5 34 8 67 AnyNOP All Banks Command tRP tMRD=2 tCK BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RFU 0 RFU DLL TM CAS Latency BT Burst Length BA0 An ~ A0 0M R S 1E M R S DLL A8 DLL Reset 0N o 1Y e s Test Mode A7 mode 0N o r m a l 1T e s t NOP

128M GDDR SDRAM K4D261638F The extended mode register stores the data for enabl ing or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore the extened mode register must be written after power up for enabling or disabling DLL. The extended mode register is written by assert- ing low on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register). The state of address pins A0, A2 ~ A5, A7 ~ A11 and BA1 in the same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. A1 and A6 are used for setting driver strength to norma l, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and cl ock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address pins except A0,A1,A6 and BA0 must be set to low for pr oper EMRS operation. Refer to the table for specific codes. A0 DLL Enable

0 Enable

1 Disable

BA0 An ~ A0 0M R S 1E M R S EXTENDED MODE REGISTER SET(EMRS) Address Bus Extended *1 : RFU(Reserved for future use) should stay "0" during EMRS cycle. A6 A1 Output Driver Impedence Control

01 Weak

11 Matched

RFU 1 RFU D.I.C RFU D.I.C DLL BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Mode Register

128M GDDR SDRAM K4D261638F Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. Note : POWER & DC OPERATING CONDITIONS(SSTL_2 In/Out) Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 65°C) Parameter Symbol Min Typ Max Unit Note Device Supply voltage V DD 2.375 2.50 2.625 V 1, 7 Output Supply voltage V DDQ 2.375 2.50 2.625 V 1, 7 Reference voltage V REF 0.49*VDDQ - 0.51*V DDQ V2 Termination voltage Vtt V REF-0.04 V REF VREF+0.04 V 3 Input logic high voltage V IH(DC) VREF+0.15 - V DDQ+0.30 V 4 Input logic low voltage V IL(DC) -0.30 - V REF-0.15 V 5 Output logic high voltage V OH Vtt+0.76 - - V I OH=-15.2mA Output logic low voltage V OL - - Vtt-0.76 V I OL=+15.2mA Input leakage current I IL -5 - 5 uA 6 Output leakage current I OL -5 - 5 uA 6 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss V IN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss V DD -1.0 ~ 3.6 V Voltage on VDD supply relative to Vss V DDQ -0.5 ~ 3.6 V Storage temperature T STG -55 ~ +150 °C Power dissipation P D 2.0 W Short circuit current I OS 50 mA 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VREF is expected to equal 0.50*VDDQ of the transmitting device and to track variations in the DC level of the same. Peak to peak noise on the VREF may not exceed + 2% of the DC value. Thus, from 0.50*VDDQ, VREF is allowed + 25mV for DC error and an additional + 25mV for AC noise. 3. Vtt of the transmitting device must track VREF of the receiving device. 4. VIH(max.)= VDDQ +1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. VIL(mim.)= -1.5V for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. For any pin under test input of 0V < VIN < VDD is acceptable. For all other pins that are not under test VIN=0V. 7. For the K4D261638F-TC25/2A, VDD & VDDQ = 2.8V+0.1V Note :

128M GDDR SDRAM K4D261638F DC CHARACTERISTICS Note : 1. Measured with outputs open. 2. Refresh period is 32ms. Parameter Symbol Test Condition Version Unit Note Operating Current (One Bank Active) ICC1 Burst Lenth=2 tRC ≥ tRC(min) IOL=0mA, tCC= tCC(min) TBD 210 190 180 170 150 mA 1 Precharge Standby Current in Power-down mode ICC2P CKE ≤ VIL(max), tCC= tCC(min) TBD 60 45 mA Precharge Standby Current in Non Power-down mode ICC2N CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) T B D 9 07 57 06 56 0 m A Active Standby Current power-down mode ICC3P CKE ≤ VIL(max), tCC= tCC(min) T B D 7 56 56 05 55 0 m A Active Standby Current in in Non Power-down mode ICC3N CKE ≥ VIH(min), CS ≥ VIH(min), tCC= tCC(min) TBD 135 100 100 95 90 mA Operating Current ( Burst Mode) ICC4 tRC ≥ tRFC(min)tRC ≥ tRFC(min) Page Burst, All Banks activated. TBD 400 290 275 260 245 mA Refresh Current I CC5 tRC ≥ tRFC(min) TBD 245 210 200 195 190 mA 2 Self Refresh Current I CC6 CKE ≤ 0.2V 4 mA Recommended operating conditions Unless Otherwise Noted, TA=0 to 65°C) 1. VID is the magnitude of the difference between the input level on CK and the input level on CK 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same 3. For the K4D261638F-TC25/2A, VDD & VDDQ = 2.8V+0.1V. Note : AC INPUT OPERATING CONDITIONS Recommended operating conditions(Voltage referenced to VSS=0V, VDD=2.5V+ 5%, VDDQ=2.5V+ 5%,TA=0 to 65°C) Parameter Symbol Min Typ Max Unit Note Input High (Logic 1) Voltage; DQ V IH VREF+0.35 - - V Input Low (Logic 0) Voltage; DQ V IL -- V REF-0.35 V Clock Input Differential Voltage; CK and CK VID 0.7 - V DDQ+0.6 V 1 Clock Input Crossing Point Voltage; CK and CK VIX 0.5*VDDQ-0.2 - 0.5*V DDQ+0.2 V 2

128M GDDR SDRAM K4D261638F RT=50Ω Output CLOAD=30pF (Fig. 1) Output Load Circuit Z0=50Ω VREF =0.5*VDDQ Vtt=0.5*VDDQ DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Symbol Value Unit Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01 uF Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip. Note : AC OPERATING TEST CONDITIONS (VDD=2.5V±5%, TA= 0 to 65°C) 1.For the K4D261638F-TC25/2A, VDD & VDDQ = 2.8V+0.1V. Parameter Value Unit Note Input reference voltage for CK(for single ended) 0.50*V DDQ V CK and CK signal maximum peak swing 1.5 V CK signal minimum slew rate 1.0 V/ns Input Levels(VIH/VIL)V REF+0.35/VREF-0.35 V Input timing measurement reference level V REF V Output timing measurement reference level V tt V Output load condition See Fig.1 CAPACITANCE (VDD=2.5V, TA= 25°C, f=1MHz) Parameter Symbol Min Max Unit Input capacitance( CK, CK )C IN1 1.0 5.0 pF Input capacitance(A0~A11, BA0~BA1)C IN2 1.0 4.0 pF Input capacitance ( CKE, CS, RAS,CAS, WE ) CIN3 1.0 4.0 pF Data & DQS input/output capacitance(DQ0~DQ15)C OUT 1.0 6.5 pF Input capacitance(DM0 ~ DM3) C IN4 1.0 6.5 pF

128M GDDR SDRAM K4D261638F AC CHARACTERISTICS - 1 Parameter Symbol -25 -2A -33 Unit NoteMin Max Min Max Min Max CK cycle time CL=3 tCK ns CL=4 - 2.86 3.3 ns CL=5 2.5 ns Data strobe edge to Dout edge tDQSQ - 0.35 - 0.35 - 0.35 ns 1 DQS-In setup time tWPRES 0-0-0- n s DQS-in hold time tWPREH 0.35 - 0.35 - 0.35 - tCK Address and Control input setup tIS 0.8 - 0.9 - 0.9 - ns Address and Control input hold tIH 0.8 - 0.9 - 0.9 - ns DQ and DM setup time to DQS tDS 0.35 - 0.35 - 0.35 - ns DQ and DM hold time to DQS tDH 0.35 - 0.35 - 0.35 - ns Clock half period tHP tCLmin or tCHmin tCLmin or tCHmin tCLmin or tCHmin -n s 1 Data output hold time from DQS tQH tHP-0.4 - tHP-0.35 - tHP-0.35 - ns 1 Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artifi cially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax

128M GDDR SDRAM K4D261638F AC CHARACTERISTICS - 2 Parameter Symbol -36 -40 -50 Unit NoteMin Max Min Max Min Max CK cycle time CL=3 tCK 4.0 5.0 ns CL=4 3.6 - - ns CL=5 - - - ns Data strobe edge to Dout edge tDQSQ - 0.40 - 0.4 - 0.45 ns 1 DQS-In setup time tWPRES 0-0-0- n s DQS-in hold time tWPREH 0.35 - 0.35 - 0.3 - tCK Address and Control input setup tIS 0.9 - 0.9 - 1.0 - ns Address and Control input hold tIH 0.9 - 0.9 - 1.0 - ns DQ and DM setup time to DQS tDS 0.40 - 0.4 - 0.45 - ns DQ and DM hold time to DQS tDH 0.40 - 0.4 - 0.45 - ns Clock half period tHP tCLmin or tCHmin tCLmin or tCHmin tCLmin or tCHmin -n s 1 Data output hold time from DQS tQH tHP-0.4 - tHP-0.4 - tHP-0.45 - ns 1 Note 1 : - The JEDEC DDR specification currently defines the output data valid window(tDV) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - The previously used definition of tDV(=0.35tCK) artifi cially penalizes system timing budgets by assuming the worst case output vaild window even then the clock duty cycle applied to the device is better than 45/55% - A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle variation and replaces tDV - tQHmin = tHP-X where . tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL) . X=A frequency dependent timing allowance account for tDQSQmax

128M GDDR SDRAM K4D261638F AC CHARACTERISTICS (II - 1) K4D261638F-TC25 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit 400MHz (2.5ns) 5 18 19 13 6 4 5 4 9 tCK 350MHz ( 2.86ns ) 4 16 17 11 5 3 5 3 9 tCK 300MHz ( 3.3ns ) 4 16 17 11 5 3 5 3 9 tCK 275MHz ( 3.6ns ) 4 16 17 11 4 2 5 3 9 tCK 250MHz ( 4.0ns ) 3 13 15 9 4 2 4 3 7 tCK 200MHz ( 5.0ns ) 3 12 14 8 4 2 4 3 7 tCK (Unit : Number of Clock) AC CHARACTERISTICS (I - 1) Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM Parameter Symbol -25 -2A -33 Unit NoteMin Max Min Max Min Max Row cycle time tRC 18 - 16 - 16 - tCK Refresh row cycle time tRFC 19 - 17 - 17 - tCK Row active time tRAS 13 100K 11 100K 11 100K tCK RAS to CAS delay for Read tRCDRD 6 - 5 - 5 - tCK RAS to CAS delay for Write tRCDWR 4 - 3 - 3 - tCK Row precharge time tRP 5 - 5 - 5 - tCK Row active to Row active tRRD 4 - 3 - 3 - tCK Last data in to Row precharge @Normal Pre- charge tWR 4-4-4- tCK 1 Last data in to Row precharge @Auto Pre- charge tWR_A 4-4-4- tCK 1 Last data in to Read command tCDLR 3 - 3 - 3 -t C K 1 Col. address to Col. address tCCD 1 - 1 - 1 - tCK Mode register set cycle time tMRD 2 - 2 - 2 - tCK Auto precharge write recovery + Precharge tDAL 9 - 9 - 9 - tCK Exit self refresh to read command tXSR 200 200 - 200 - tCK Power down exit time tPDEX 3tCK +tIS 3tCK +tIS - 3tCK +tIS -n s Refresh interval time tREF 7.8 7.8 - 7.8 - us K4D261638F-TC33 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit 300MHz ( 3.3ns ) 4 16 17 11 5 3 5 3 9 tCK 275MHz ( 3.6ns ) 4 16 17 11 4 2 5 3 9 tCK 250MHz ( 4.0ns ) 3 13 15 9 4 2 4 3 7 tCK 200MHz ( 5.0ns ) 3 12 14 8 4 2 4 3 7 tCK K4D261638F-TC2A Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit 350MHz ( 2.86ns ) 4 16 17 11 5 3 5 3 9 tCK 300MHz ( 3.3ns ) 4 16 17 11 5 3 5 3 9 tCK 275MHz ( 3.6ns ) 4 16 17 11 4 2 5 3 9 tCK 250MHz ( 4.0ns ) 3 13 15 9 4 2 4 3 7 tCK 200MHz ( 5.0ns ) 3 12 14 8 4 2 4 3 7 tCK

128M GDDR SDRAM K4D261638F AC CHARACTERISTICS (II - 2) K4D261638F-TC36 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit 275MHz ( 3.6ns ) 4 16 17 11 4 2 5 3 9 tCK 250MHz ( 4.0ns ) 3 13 15 9 4 2 4 3 7 tCK 200MHz ( 5.0ns ) 3 12 14 8 4 2 4 3 7 tCK (Unit : Number of Clock) AC CHARACTERISTICS (I - 2) Note : 1. For normal write operation, even numbers of Din are to be written inside DRAM Parameter Symbol -36 -40 -50 Unit NoteMin Max Min Max Min Max Row cycle time tRC 16 - 13 - 12 - tCK Refresh row cycle time tRFC 17 - 15 - 14 - tCK Row active time tRAS 11 100K 9 100K 8 100K tCK RAS to CAS delay for Read tRCDRD 4 - 4 - 4 - tCK RAS to CAS delay for Write tRCDWR 2 - 2 - 2 - tCK Row precharge time tRP 5 - 4 - 4 - tCK Row active to Row active tRRD 3 - 3 - 3 - tCK Last data in to Row precharge @Normal Pre- charge tWR 4 -3-3- t C K 1 Last data in to Row precharge @Auto Pre- charge tWR_A 4 -3-3- t C K 1 Last data in to Read command tCDLR 2 - 2 - 2 - tCK 1 Col. address to Col. address tCCD 1 - 1 - 1 - tCK Mode register set cycle time tMRD 2 - 2 - 2 - tCK Auto precharge write recovery + Precharge tDAL 9 - 7 - 7 - tCK Exit self refresh to read command tXSR 200 - 200 - 200 - tCK Power down exit time tPDEX 3tCK +tIS - 3tCK +tIS - 3tCK +tIS -n s Refresh interval time tREF 7.8 - 7.8 - 7.8 - us K4D261638F-TC50 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit 200MHz ( 5.0ns ) 3 12 14 8 4 2 4 3 7 tCK K4D261638F-TC40 Frequency Cas Latency tRC tRFC tRAS tRCDRD tRCDWR tRP tRRD tDAL Unit 250MHz ( 4.0ns ) 3 13 15 9 4 2 4 3 7 tCK 200MHz ( 5.0ns ) 3 12 14 8 4 2 4 3 7 tCK

128M GDDR SDRAM K4D261638F Simplified Timing @ BL=4 Normal Write Burst (@ BL=4) Multi Bank Interleaving Write Burst (@ BL=4) 012345678 13 14 15 16 17 18 19 20 2191 0 1 1 1 2 22 COM DQS DQ WE DM CK, CK A8/AP ADDR (A0~A7 BA[1:0] D a 0D a 1D a 2D a 3 Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3 ACT_A WR_A PRECH ACT_A WR_A ACT_B WR_B tRCD tRAS tRP tRC tRRD BAa BAa BAa BAa BAa BAb BAb Rb RbCa Cb RaRa Ra Ca Ra ,A9~A11)

128M GDDR SDRAM K4D261638F PACKAGE DIMENSIONS (66pin TSOP-II) Units : Millimeters 22.22±0.10 0.125 (0.80) 10.16±0.10 0×~8× #1 #33 #66 #34 (1.50) (1.50) 0.65±0.08 1.00±0.10 1.20MAX 11.76±0.20 (10×)(10×) +0.075 -0.035 (0.80)

0.10 MAX

0.075 MAX[]

0.05 MIN

(10×) (10×) (R0.15) 0.210±0.05 0.665±0.05 (R0.1 (4×) (R0.25) (R0 .25) 0.45~0.75 0.25TYP NOTE 1. ( ) IS REFERENCE 2. [ ] IS ASS’Y OUT QUALITY