K4B1G1646D-HCF7

K4B1G0446D SAMSUNG | Alldatasheet

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Page 1 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D 1Gb D-die DDR3 SDRAM Specification 82 / 100 FBGA with Lead-Free & Halogen-Free (RoHS Compliant) CAUTION : * This document includes some items still under discussion in JEDEC. * Therefore, those may be changed without pre-notice based on JEDEC progress. * And it’s highly recommended not to send the spec without Samsung’s permission. * Samsung Electronics reserves the right to change products or specification without notice. INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER- WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL- OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

Page 2 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D

Revision History

Revision Month Year History

1.0 March 2008 - First release

1.1 August 2008 - Changed Current Specification

• Corrected Typo

Page 3 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D Table Contents

Page 4 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D

Page 5 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D

• JEDEC standard 1.5V ± 0.075V Power Supply
• V DDQ = 1.5V ± 0.075V
• 400 MHz f CK for 800Mb/sec/pin, 533MHz fCK for 1066Mb/sec/pin, 667MHz fCK for 1333Mb/sec/pin, 800MHz fCK for 1600Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency(posted CAS): 6, 7, 8, 9, 10
• Programmable Additive Latency: 0, CL-2 or CL-1 clock
• Programmable CAS Write Latency (CWL) = 5 (DDR3-800), 6 (DDR3-1066), 7 (DDR3-1333) and 8 (DDR3-1600)
• 8-bit pre-fetch
• Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or write [either On the fly using A12 or MRS]
• Bi-directional Differential Data-Strobe
• Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
• On Die Termination using ODT pin
• Average Refresh Period 7.8us at lower than T CASE 85°C, 3.9us at 85°C < TCASE < 95 °C
• Asynchronous Reset
• Package : 82 balls FBGA - x4/x8 (with 4 support balls) 100 balls FBGA - x16 (with 4 support balls)
• All of Lead-Free products are compliant for RoHS
• All of products are Halogen-free The 1Gb DDR3 SDRAM D-die is organized as a 32Mbit x 4 I/Os x 8banks, 16Mbit x 8 I/Os x 8banks or 8Mbit x 16 I/Os x 8 banks device. This syn- chronous device achieves high speed double-data-rate transfer rates of up to 1600Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM fea- tures such as posted CAS, Programmable CWL, Internal (Self) Calibra- tion, On Die Termination using ODT pin and Asynchronous Reset . All of the control and address inputs are synchronized with a pair of exter- nally supplied differential clocks. Inputs are latched at the crosspoint of dif- ferential clocks (CK rising and CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash- ion. The address bus is used to convey row, column, and bank address information in a RAS /CAS multiplexing style. The DDR3 device operates The 1Gb DDR3 D-die device is avai lable in 82ball FBGAs(x4/x8) and 100ball FBGA(x16) Note : 1. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. Note : This data sheet is an abstract of full DDR3 specification and does not cover the common features which are described in “DDR3 SDRAM Device Operation & Timing Diagram”. [ Table 1 ] Samsung 1Gb DDR3 D-die ordering information table Note : 1. Speed bin is in order of CL-tRCD-tRP. 2. x4/x8/x16 Package - including 4 support balls Organization DDR3-800 (6-6-6) DDR3-1066 (7-7-7) DDR3-1333 (9-9-9) DDR3-1600 Package 256Mx4 K4B1G0446D-HCF7 K4B1G0446D-HCF8 K4B1G0446D-HCH9 TBD 82 FBGA 128Mx8 K4B1G0846D-HCF7 K4B1G0846D-HCF8 K4B1G0846D-HCH9 TBD 82 FBGA 64Mx16 K4B1G1646D-HCF7 K4B1G1646D-HCF8 K4B1G1646D-HCH9 TBD 100 FBGA [ Table 2 ] 1Gb DDR3 D-die Speed bins Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit tCK(min) 2.5 1.875 1.5 TBD ns CAS Latency 6 7 9 TBD nCK tRCD(min) 15 13.125 13.5 TBD ns tRP(min) 15 13.125 13.5 TBD ns tRAS(min) 37.5 37.5 36 TBD ns tRC(min) 52.5 50.625 49.5 TBD ns

1.0 Ordering Information

2.0 Key Features

Page 6 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D 3.1 x4 Package Pinout (Top view) : 82ball FBGA Package(78balls + 4 balls of support balls) Note : Green NC balls (A1, A11, N1 and N11) indicate mechanical support balls with no internal connection. 1 2 3 4 5 6 7 8 9 10 11 A NC VSS VDD NC NC VSS VDD NC A B VSS VSSQ DQ0 DM VSSQ VDDQ B C VDDQ DQ2 DQS DQ1 DQ3 VSSQ C D VSSQ NC DQS VDD VSS VSSQ D E VREFDQ VDDQ NC NC NC VDDQ E F NC VSS RAS CK VSS NC F G ODT VDD CAS CK VDD CKE G H NC CS WE A10/AP ZQ NC H J VSS BA0 BA2 NC VREFCA VSS J K VDD A3 A0 A12/BC BA1 VDD K L VSS A5 A2 A1 A4 VSS L M VDD A7 A9 A11 A6 VDD M N NC VSS RESET A13 NC A8 VSS NC N Populated ball Ball not populated Ball Locations (x4) Top view (See the balls through the package) 1234 89 567 A B C D E F G H J K L N M 10 11

3.0 Package pinout/Mechanical Dimension & Addressing

Page 7 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D Note : Green NC balls (A1, A11, N1 and N11) indicate mechanical support balls with no internal connection. 1 2 3 4 5 6 7 8 9 10 11 A NC VSS VDD NC NU/TDQS VSS VDD NC A B VSS VSSQ DQ0 DM/TDQS VSSQ VDDQ B C VDDQ DQ2 DQS DQ1 DQ3 VSSQ C D VSSQ DQ6 DQS VDD VSS VSSQ D E VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ E F NC VSS RAS CK VSS NC F G ODT VDD CAS CK VDD CKE G H NC CS WE A10/AP ZQ NC H J VSS BA0 BA2 NC VREFCA VSS J K VDD A3 A0 A12/BC BA1 VDD K L VSS A5 A2 A1 A4 VSS L M VDD A7 A9 A11 A6 VDD M N NC VSS RESET A13 NC A8 VSS NC N Populated ball Ball not populated Ball Locations (x8) Top view (See the balls through the package) 1234 89 567 A B C D E F G H J K L N M 10 11 3.2 x8 Package Pinout (Top view) : 82ball FBGA Package(78balls + 4 balls of support balls)

Page 8 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D Note : Green NC balls (A1, A11, T1 and T11) indicate mechanical support balls with no internal connection. 1 2 3 4 5 6 7 8 9 10 11 A NC VDDQ DQU5 DQU7 DQU4 VDDQ VSS NC A B VSSQ VDD VSS DQSU DQU6 VSSQ B C VDDQ DQU3 DQU1 DQSU DQU2 VDDQ C D VSSQ VDDQ DMU DQU0 VSSQ VDD D E VSS VSSQ DQL0 DML VSSQ VDDQ E F VDDQ DQL2 DQSL DQL1 DQL3 VSSQ F G VSSQ DQL6 DQSL VDD VSS VSSQ G H VREFDQ VDDQ DQL4 DQL7 DQL5 VDDQ H J NC VSS RAS CK VSS NC J K ODT VDD CAS CK VDD CKE K L NC CS WE A10/AP ZQ NC L M VSS BA0 BA2 NC VREFCA VSS M N VDD A3 A0 A12/BC BA1 VDD N P VSS A5 A2 A1 A4 VSS P R VDD A7 A9 A11 A6 VDD R T NC VSS RESET NC NC A8 VSS NC T Populated ball Ball not populated Ball Locations (x16) Top view (See the balls through the package) 1234 89 567 A B C D E F G H J K L N M 10 11 P R T 3.3 x16 Package Pinout (Top view) : 100ball FBGA Package(96balls + 4 balls of support balls)

Page 9 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D A B C D E F G H M N 9.00 ± 0.10 0.80 x 12 = 9.60 0.80 x 10 = 8.00 4.000.80 4.80 82 - ∅0.45 Solder ball

0.2 ABM

(Datum B) (Datum A) 0.10MAX 1.10 ± 0.10 #A1 1 0 8765432111 9 1.60 9.00 ± 0.10 11.00 ± 0.10 MOLDING AREA 0.35 ± 0.05 #A1 INDEX MARK B A BOTTOM VIEW TOP VIEW 11.00 ± 0.10 J K L 0.80 0.80 (Post Reflow ∅0.50 ± 0.05) (0.95) (1.90)

3.4 FBGA Package Dimension (x4/x8)

Units : Millimeters

Page 10 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D A B C D E F G H J L M N P R T 9.00 ± 0.10 4.000.80 6.00(Datum B) (Datum A) 0.10MAX 1.10 ± 0.10 #A1 1 0 8765432111 9 1.60 9.00 ± 0.10 13.30 ± 0.10 0.35 ± 0.05 #A1 INDEX MARK TOP VIEW 13.30 ± 0.10 K 0.80 x 15 = 12.00 0.80 x 10 = 8.00 B A0.80 0.40 100 - ∅0.45 Solder ball MOLDING AREA(Post Reflow ∅0.50 ± 0.05) (0.95) (1.90) BOTTOM VIEW

3.5 FBGA Package Dimension (x16)

Units : Millimeters

Page 11 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 3 ] Input/Output function description Symbol Type Function CK, CK Input Clock: CK and CK are differential clock inputs. All address and c ontrol input signals are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK CKE Input Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CK E is asynchronous for self refresh exit. After V REFCA has become stable during the power on and initialization sequence, it must be maintained during all operations (including Self- Refresh). CKE must be maintained high throughout r ead and write accesses. Input buffers, excluding CK, CK , ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during Self -Refresh. CS Input Chip Select: All commands are masked when CS is registered HIGH. CS provides for external Rank selection on systems with multiple Ranks. CS is considered part of the command code. ODT Input On Die Termination: ODT (registered HIGH) enables termination resi stance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, DQS and DM/TDQS, NU/TDQS (When TDQS is enabled via Mode Register A11=1 in MR1) signal for x8 configurations. The ODT pin will be ignored if the Mode Register (MR1) is pro- grammed to disable ODT. RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered. DM (DMU), (DML) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH coinci- dent with that input data during a Write access. DM is sa mpled on both edges of DQS. For x8 device, the function of DM or TDQS/TDQS is enabled by Mode Register A11 setting in MR1. BA0 - BA2 Input Bank Address Inputs: BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines if the mode register or extended mode register is to be accessed during a MRS cycle. A0 - A13 Input Address Inputs: Provided the row address for Active commands and the column address for Read/Write commands to select one location out of the memory array in the respective bank. (A10/AP and A12/BC have additional functions, see below) The address inputs also provide the op-code during Mode Register Set commands. A10 / AP Input Autoprecharge: A10 is sampled during Read/Write commands to determine whether Autoprecharge should be per- formed to the accessed bank after the Read/Write operation. (HIGH:Autoprecharge; LOW: No Autoprecharge) A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). if only one bank is to be precharged, the bank is selected by bank addresses. A12 / BC Input Burst Chop: A12 is sampled during Read and Write commands to determine if burst chop(on-the-fly) will be per- formed. (HIGH : no burst chop, LOW : burst chopped). See command truth table for details RESET Input Active Low Asynchronous Reset: Reset is active when RESET is LOW, and inactive when RESET is HIGH. RESET must be HIGH during normal operation. RESET is a CMOS rail to rail signal with DC high and low at 80% and DQ Input/Output Data Input/ Output: Bi-directional data bus. DQS, (DQS) Input/Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. For the x16, DQSL: corresponds to the data on DQL0-DQL7; DQSU corresponds to the data on DQU0-DQU7. The data strobe DQS, DQSL and DQSU are paired with differential signals DQS, DQSL and DQSU, respectively, to provide dif- ferential pair signaling to the system during reads and writes. DDR3 SDRAM supports differential data strobe only and does not support single-ended. TDQS, (TDQS) Output Termination Data Strobe: TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in MR1, DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/T DQS will provide the data mask function and TDQS is not used. x4/ x16 DRAMs must disable the TDQS function via mode register A11=0 in MR1. NC No Connect: No internal electrical connection is present. VDDQ Supply DQ Power Supply: 1.5V +/- 0.075V VSSQ Supply DQ Ground VDD Supply Power Supply: 1.5V +/- 0.075V VSS Supply Ground VREFDQ Supply Reference voltage for DQ VREFCA Supply Reference voltage for CA ZQ Supply Reference Pin for ZQ calibration Note : Input only pins (BA0-BA2, A0-A12, RAS, CAS, WE, CS, CKE, ODT and RESET) do not supply termination.

4.0 Input/Output Functional Description

Page 12 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D 1Gb Configuration 256Mb x 4 128Mb x 8 64Mb x 16 # of Bank 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A 10/AP A 10/AP A 10/AP Row Address A 0 - A13 A0 - A13 A0 - A12 Column Address A 0 - A9,A11 A0 - A9 A 0 - A9 BC switch on the fly A 12/BC A12/BC A12/BC Page size *1 1 KB 1 KB 2 KB Note 1 : Page size is the number of bytes of data delivered from the array to the internal sense amplifiers when an ACTIVE command is registered. Page size is per bank, calculated as follows: page size = 2 COLBITS * ORG÷8 where, COLBITS = the number of column address bits, ORG = the number of I/O (DQ) bits

5.0 DDR3 SDRAM Addressing

Configuration 512Mb x 4 256Mb x 8 128Mb x 16 # of Bank 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A 10/AP A 10/AP A 10/AP Row Address A 0 - A14 A0 - A14 A0 - A13 Column Address A 0 - A9,A11 A0 - A9 A 0 - A9 BC switch on the fly A 12/BC A12/BC A12/BC Page size *1 1 KB 1 KB 2 KB 4Gb Configuration 1Gb x 4 512Mb x 8 256Mb x 16 # of Bank 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A 10/AP A 10/AP A 10/AP Row Address A 0 - A15 A0 - A15 A0 - A14 Column Address A 0 - A9,A11 A0 - A9 A 0 - A9 BC switch on the fly A 12/BC A12/BC A12/BC Page size *1 1 KB 1 KB 2 KB 8Gb Configuration 2Gb x 4 1Gb x 8 512Mb x 16 # of Bank 8 8 8 Bank Address BA0 - BA2 BA0 - BA2 BA0 - BA2 Auto precharge A 10/AP A 10/AP A 10/AP Row Address A 0 - A15 A0 - A15 A0 - A15 Column Address A 0 - A9,A11,A13 A0 - A9,A11 A0 - A9 BC switch on the fly A 12/BC A12/BC A12/BC Page size *1 2 KB 2 KB 2 KB

Page 13 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D

6.1 Absolute Maximum DC Ratings

[ Table 4 ] Absolute Maximum DC Ratings Note : 1. Stresses greater than those listed under “Absolute Maximum Rati ngs” may cause permanent damage to the device. This is a stre ss rating only and functional operation of the device at these or any other condit ions above those indicated in the operational sections of this s pecification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard. 3. VDD and VDDQ must be within 300mV of each other at all times;and V REF must be not greater than 0.6 x V DDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. Symbol Parameter Rating Units Notes VDD Voltage on VDD pin relative to Vss -0.4 V ~ 1.975 V V 1,3 VDDQ Voltage on V DDQ pin relative to Vss -0.4 V ~ 1.975 V V 1,3 VIN, VOUT Voltage on any pin relative to Vss -0.4 V ~ 1.975 V V 1 TSTG Storage Temperature -55 to +100 °C 1, 2

7.0 AC & DC Operating Conditions

7.1 Recommended DC operating Conditions (SSTL_1.5) [ Table 6 ] Recommended DC Operating Conditions Note : 1. Under all conditions VDDQ must be less than or equal to VDD. 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together. Symbol Parameter Rating Units Notes Min. Typ. Max. VDD Supply Voltage 1.425 1.5 1.575 V 1,2 VDDQ Supply Voltage for Output 1.425 1.5 1.575 V 1,2 [ Table 5 ] Temperature Range Note : 1. Operating Temperature TOPER is the case surface temperature on the center/top side of the DRAM. For measurement c onditions, please refer to the JEDEC document JESD51-2. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, t he DRAM case tem- perature must be maintained between 0-85°C under all operating conditions 3. Some applications require operation of the Extended Temperature Range between 85 °C and 95°C case temperature. Full specifications are guaran- teed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore r educing the refresh interval tREFI to 3.9us. It is also possibl e to specify a component with 1X refresh (tREFI to 7.8us) in the Extended Temperature Range. b) If Self-Refresh operation is required in the Extended Temper ature Range, then it is mandatory to either use the Manual Sel f-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b) Symbol Parameter rating Unit Notes TOPER Operating Temperature Range 0 to 95 °C 1, 2, 3

6.2 DRAM Component Operating Temperature Range

6.0 Absolute Maximum Ratings

Page 14 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 7 ] Single Ended AC and DC input levels for Command and Address Note : 1. For input only pins except RESET, VREF = VREFCA(DC) 2. See 9.6 "Overshoot and Undershoot specifications" 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV) 4. For reference : approx. VDD/2 ± 15mV Symbol Parameter DDR3-800/1066 DDR3-1333/1600 Unit Notes Min. Max. Min. Max. VIH.CA(DC) DC input logic high VREF + 100 V DD VREF + 100 V DD mV 1 VIL.CA(DC) DC input logic low VSS VREF - 100 V SS VREF - 100 mV 1 VIH.CA(AC) AC input logic high VREF + 175 - VREF + 175 -m V 1 , 2 VIL.CA(AC) AC input logic low - VREF - 175 - VREF - 175 mV 1,2 VIH.CA(AC150) AC input logic high - - VREF+150 -m V 1 , 2 VIL.CA(AC150) AC input logic lowM - - - VREF-150 mV 1,2 VREFCA(DC) Reference Voltage for ADD, CMD inuts 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V3 , 4

8.0 AC & DC Input Measurement Levels

8.1 AC and DC Logic input levels for single-ended signals

[ Table 8 ] Single Ended AC and DC input levels for DQ and DM Note : 1. For input only pins except RESET, VREF = VREFDQ(DC) 2. See "Overshoot and Undershoot specifications" 3. The AC peak noise on VREF may not allow VREF to deviate from VREF(DC) by more than ± 1% VDD (for reference : approx. ± 15mV) 4. For reference : approx. VDD/2 ± 15mV 5. Single ended swing requirement for DQS - DQS is 350mV (peak to peak). Differential swing for DQS - DQS is 700mV (peak to peak). Symbol Parameter DDR3-800/1066 DDR3-1333/1600 Unit Notes Min. Max. Min. Max. VIH.DQ(DC) DC input logic high VREF + 100 V DD VREF + 100 V DD mV 1 VIL.DQ(DC) DC input logic low VSS VREF - 100 V SS VREF - 100 mV 1 VIH.DQ(AC) AC input logic high VREF + 175 - VREF + 150 - mV 1,2,5 VIL.DQ(AC) AC input logic low - VREF - 175 - VREF - 150 mV 1,2,5 VREFDQ(DC) I/O Reference Voltage(DQ) 0.49*VDD 0.51*VDD 0.49*VDD 0.51*VDD V3 , 4

VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). thermore VREF(t) may temporarily deviate from VREF(DC) by no more than ± 1% VDD. Figure 1. Illustration of VREF(DC) tolerance and VREF ac-noise limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. "VREF" shall be understood as VREF(DC), as defined in Figure 1. data-eye of the input signals. and voltage effects due to ac-noise on VREF up to the specified limit (+/-1% of VDD) are included in DRAM timings and their associated deratings.

8.2 VREF Tolerances

Page 16 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D Figure 2 : Definition of differential ac-swing and "time above ac level" tDVAC [ Table 9 ] Differential AC and DC Input Levels Notes: 1. Used to define a differential signal slew-rate. 2. for CK - CK use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - DQS, DQSL - DQSL, DQSU - DQSU use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Reter to "overshoot and Undersheet Specification " [ Table 10 ] Allowed time before ringback (tDVAC) for CLK - CLK and DQS - DQS. Symbol Parameter DDR3-800/1066/1333/1600 unit Note min max VIHdiff differential input high +0.2 note 3 V 1 VILdiff differential input low note 3 -0.2 V 1 VIHdiff(AC) differential input high ac 2 x (VIH(AC)-VREF) note 3 V 2 VILdiff(AC) differential input low ac note 3 2 x (VREF - VIL(AC)) V2 Slew Rate [V/ns] tDVAC [ps] @ |VIH/Ldiff(AC)| = 350mV tDVAC [ps] @ |VIH/Ldiff(AC)| = 300mV min max min max > 4.0 75 - 175 - 4.0 57 - 170 - 3.0 50 - 167 - 2.0 38 - 163 - 1.8 34 - 162 - 1.6 29 - 161 - 1.4 22 - 159 - 1.2 13 - 155 - 1.0 0 - 150 - < 1.0 0 - 150 -

8.3.1 Differential signal definition

8.3.2 Differential swing requirement for clock (CK - CK) and strobe (DQS - DQS)

0.0 tDVAC VIH.DIFF.MIN half cycle Differential Input Voltage (i.e. DQS-DQS, CK-CK) time tDVAC VIH.DIFF.AC.MIN VIL.DIFF.MAX VIL.DIFF.AC.MAX

8.3 AC and DC Logic Input Levels for Ditterential Signals

Page 17 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D Note that while ADD/CMD and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDD/2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single- ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode charateristics of these signals. VDD or VDDQ VSEH min VDD/2 or VDDQ/2 VSEL max VSEH VSS or VSSQ VSEL CK or DQS time

8.3.3 Single-ended requirements for differential signals

Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, or DQSU) has also to comply with certain requirements for single-ended signals. CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels ( VIH(AC) / VIL(AC) ) for ADD/CMD signals) in every half-cycle. DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels ( VIH(AC) / VIL(AC) ) for DQ signals) in every half-cycle preceeding and following a valid transition. Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g. if VIH150(AC)/VIL150(AC) is used for ADD/CMD sig- nals, then these ac-levels apply also for the single-ended signals CK and CK . Figure 3 : Single-ended requirement for differential signals. [ Table 11 ] Single ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU Notes: 1. For CK, CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL(AC) of DQs. 2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here 3. These values are not defined, however they single-ended signals CK, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to "Overshoot and Undershoot Specification" Symbol Parameter DDR3-800/1066/1333/1600 Unit NotesMin Max VSEH Single-ended high-level for strobes (VDD/2)+0.175 Note3 V 1, 2 Single-ended high-level for CK, CK (VDD/2)+0.175 Note3 V 1, 2 VSEL Single-ended low-level for strobes Note3 (VDD/2)-0.175 V1 , 2 Single-ended low-level for CK, CK Note3 (VDD/2)-0.175 V1 , 2

1. Extended range for V IX is only allowed for clock and if single-ended clock input signals CKand CK are monotonic, have a single-ended swing V SEL /

cross point of true and complement signal to the mid level between of VDD and VSS. Figure 4. VIX Definition

8.4 Differential Input Cross Point Voltage

See 14.3 "Address / Command Setup, Hold and Derating" for single-ended slew rate definitions for address and command signals.

8.5 Slew Rate Definition for Single Ended Input Signals

8.6 Slew rate definition for Differential Input Signals

Figure 5. Differential Input Slew Rate definition for DQS, DQS and CK, CK Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in Table 13 and Figure 5.

Page 19 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 14 ] Single Ended AC and DC output levels Note : 1. The swing of +/-0.1 x V DDQ is based on approximately 50% of the static single en ded output high or low swing with a driver impedance of 40 Ω and an effective test load of 25Ω to VTT=VDDQ/2. Symbol Parameter DDR3-800/1066/1333/1600 Units Notes VOH(DC) DC output high measurement level (for IV curve linearity) 0.8 x V DDQ V VOM(DC) DC output mid measurement level (for IV curve linearity) 0.5 x V DDQ V VOL(DC) DC output low measurement level (for IV curve linearity) 0.2 x V DDQ V VOH(AC) AC output high measurement level (for output SR) V TT + 0.1 x VDDQ V1 VOL(AC) AC output low measurement level (for output SR) V TT - 0.1 x VDDQ V1 [ Table 15 ] Differential AC and DC output levels Note : 1. The swing of +/-0.2xV DDQ is based on approximately 50% of the static singel ended output high or low swing with a driver impedance of 40 Ω and an effective test load of 25Ω to VTT=VDDQ/2 at each of the differential outputs. Symbol Parameter DDR3-800/1066/1333/1600 Units Notes VOHdiff(AC) AC differential output high measurement level (for output SR) +0.2 x V DDQ V1 VOLdiff(DC) AC differential output low measurement level (for output SR) -0.2 x V DDQ V1

9.2 Differential AC and DC Output Levels

9.0 AC and DC Output Measurement Levels

9.1 Single Ended AC and DC Output Levels

VOH(AC) VOL(AC) delta TRsedelta TFse Figure 6. Single Ended Output Slew Rate definition for single ended signals as shown in Table 16 and figure 6. Note : Output slew rate is verified by design and characterization, and may not be subject to production test.

Description

Single ended output slew rate for rising edge VOL(AC) V OH(AC) VOH(AC)-VOL(AC) Delta TRse Single ended output slew rate for falling edge VOH(AC) V OL(AC) VOH(AC)-VOL(AC) Delta TFse Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Min Max Min Max Min Max Min Max Single ended output slew rate SRQse 2.5 5 2.5 5 2.5 5 TBD 5 V/ns VTT

Page 20 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D VOHdiff(AC) VOLdiff(AC) delta TRdiffdelta TFdiff Figure 7. Differential Output Slew Rate definition

9.5 Reference Load for AC Timing and Output Slew Rate

production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics. Figure 8. Reference Load for AC Timing and Output Slew Rate

9.4 Differential Output Slew Rate

VOHdiff(AC) for differential signals as shown inTable 18 and figure 7. Note : Output slew rate is verified by design and characterization, and may not be subject to production test. Differential output slew rate for rising edge VOLdiff(AC) V OHdiff(AC) VOHdiff(AC)-VOLdiff(AC) Delta TRdiff Differential output slew rate for falling edge VOHdiff(AC) V OLdiff(AC) VOHdiff(AC)-VOLdiff(AC) Delta TFdiff Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Min Max Min Max Min Max Min Max Differential output slew rate SRQse 5 10 5 10 5 10 TBD 10 V/ns

9.6.2 Clock, Data, Strobe and Mask Overshoot and Undershoot specifications

9.6.1 Address and Control Overshoot and Undershoot specifications

Figure 9. Address and Control Overshoot and Undershoot definition Figure 10. Clock, Data, Strobe and Mask Overshoot and Undershoot definition

9.6 Overshoot/Undershoot Specification

Figure 11. Output Driver : Definition of Voltages and Currents

1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibra-
2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS
3. Pull-down and pull-up output driver impedance are recommended to be calibrated at 0.5 X V DDQ. Other calibration schemes may be used to achieve the linearity spec
4. Measurement definition for mismatch between pull-up and pull-down, MMpupd: Measure RONpu and RONpd. both at 0.5 X V DDQ:

If temperature and/or voltage change after calibration, the tolerance limits widen according to table 23 and 24.

9.7.1 Output Drive Temperature and Voltage sensitivity

On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of MR1 register. ODT is applied to the DQ,DM, DQS/DQS and TDQS,TDQS (x8 devices only) pins.

9.8 On-Die Termination (ODT) Levels and I-V Characteristics

Figure 12. On-Die Termination : Definition of Voltages and Currents

Page 24 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D Table 26 provides and overview of the ODT DC electrical characteristics. They values for RTT60pd120, RTT60pu120, RTT120pd240, RTT120pu240, RTT40pd80, RTT40pu80, RTT30pd60, RTT30pu60, RTT20pd40, RTT20pu40 are not specification requirements, but can be used as design guide lines: [ Table 25 ] ODT DC Electrical characteristics, assuming RZQ=240 ohm +/- 1% entire operating temperature range; after proper ZQ calibration. MR1 (A9,A6,A2) RTT RESISTOR Vout Min Nom Max Unit Notes (0,1,0) 120 ohm RTT120pd240 VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ 1,2,3,4 VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ 1,2,3,4 RTT120pu240 VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ 1,2,3,4 VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ 1,2,3,4 RTT120 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/2 1,2,5 (0,0,1) 60 ohm RTT60pd240 VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/2 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/2 1,2,3,4 VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/2 1,2,3,4 RTT60pu240 VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/2 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/2 1,2,3,4 VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/2 1,2,3,4 RTT60 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/4 1,2,5 (0,1,1) 40 ohm RTT40pd240 VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/3 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/3 1,2,3,4 VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/3 1,2,3,4 RTT40pu240 VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/3 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/3 1,2,3,4 VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/3 1,2,3,4 RTT40 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/6 1,2,5 (1,0,1) 30 ohm RTT60pd240 VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/4 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/4 1,2,3,4 VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/4 1,2,3,4 RTT60pu240 VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/4 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/4 1,2,3,4 VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/4 1,2,3,4 RTT60 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/8 1,2,5 (1,0,0) 20 ohm RTT60pd240 VOL(DC) 0.2XVDDQ 0.6 1.0 1.1 RZQ/6 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/6 1,2,3,4 VOH(DC) 0.8XVDDQ 0.9 1.0 1.4 RZQ/6 1,2,3,4 RTT60pu240 VOL(DC) 0.2XVDDQ 0.9 1.0 1.4 RZQ/6 1,2,3,4 0.5XVDDQ 0.9 1.0 1.1 RZQ/6 1,2,3,4 VOH(DC) 0.8XVDDQ 0.6 1.0 1.1 RZQ/6 1,2,3,4 RTT60 VIL(AC) to VIH(AC) 0.9 1.0 1.6 RZQ/12 1,2,5 Deviation of VM w.r.t VDDQ/2, ∆VM -5 5 % 1,2,5,6

9.8.1 ODT DC electrical characteristics

Page 25 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D Note : 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS 3. Pull-down and pull-up ODT resistors are recommended to be calibrated at 0.5XV DDQ. Other calibration schemes may be used to achieve the linearity 4. Not a specification requirement, but a design guide line 5. Measurement definition for RTT: Apply VIH(AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current I(VIL(AC)) perspectively 6. Measurement definition for VM and ∆VM : Measure voltage (VM) at test pin (midpoint) with no load RTT = VIH(AC) - VIL(AC) I(VIH(AC)) - I(VIL(AC)) ∆ VM = 2 x VM VDDQ x 100- 1 If temperature and/or voltage change after calibration, the tolerance limits widen according to table below ∆T = T - T(@calibration); ∆V = VDDQ - VDDQ (@calibration); VDD = VDDQ [ Table 26 ] ODT Sensitivity Definition [ Table 27 ] ODT Voltage and Temperature Sensitivity These parameters may not be subject to production test. They are verified by design and characterization. Min Max Units RTT 0.9 - dRTTdT * |∆T| - dRTTdV * |∆V| 1.6 + dRTTdT * |∆T| + dRTTdV * |∆V| RZQ/2,4,6,8,12 Min Max Units dRTTdT 01 . 5 %/°C dRTTdV 0 0.15 %/mV

9.8.2 ODT Temperature and Voltage sensitivity

9.9.2 ODT Timing Definition

Figure 13. ODT Timing Reference Load

9.9 ODT Timing Definitions

9.9.1 Test Load for ODT Timings

Different than for timing measurements, the reference load for ODT timings is defined in Figure 13.

Page 29 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D

10.1 IDD Measurement Conditions

In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure 19 shows the setup and test load for IDD and IDDQ measurements. - IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all V DD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. - IDDQ currents (such as IDDQ2NT and IDDQ4R) are measur ed as time-averaged currents with all V DDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Attention : IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 20. In DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB. For IDD and IDDQ measurements, the following definitions apply : - "0" and "LOW" is defined as VIN <= VILAC(max). - "1" and "HIGH" is defined as VIN >= VIHAC(min). - "FLOATING" is defined as inputs are VREF = VDD / 2. - Timings used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 30. - Basic IDD and IDDQ Measurement Conditions are described in Table 31. - Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 32 on page 33 through Table 39. - IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting RON = RZQ/7 (34 Ohm in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 Ohm in MR1); RTT_Wr = RZQ/2 (120 Ohm in MR2); TDQS Feature disabled in MR1 - Attention : The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. - Define D = {CS , RAS, CAS, WE} := {HIGH, LOW, LOW, LOW} - Define D = {CS, RAS, CAS, WE} := {HIGH, HIGH, HIGH, HIGH} Timing parameters are listed in the following table: [ Table 30 ] For IDD testing the following parameters are utilized. Parameter Bin DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Unit tCKmin(IDD) 2.5 1.875 1.5 1.25 ns C L ( I D D ) 56678789 1 0 89 1 0 1 1 n C K tRCDmin(IDD) 5 6 6 7 8 7 8 9 10 8 9 10 11 nCK t R C m i n ( I D D ) 2 02 12 62 72 83 13 23 3 3 4 3 63 7 3 8 3 9 n C K tRASmin(IDD) 15 20 24 28 nCK t R P m i n ( I D D ) 56678789 1 0 89 1 0 1 1 n C K tFAW(IDD) x4/x8 16 20 20 24 nCK x16 20 27 30 32 nCK tRRD(IDD) x4/x8 4 4 4 5 nCK x16 4 6 5 6 nCK tRFC(IDD) - 512Mb 36 48 60 72 nCK tRFC(IDD) - 1Gb 44 59 74 88 nCK tRFC(IDD) - 2Gb 64 86 107 128 nCK tRFC(IDD) - 4Gb 120 160 200 240 nCK tRFC(IDD) - 8Gb 140 187 234 280 nCK

10.2 IDD Specifications definition

10.0 Idd Specification Parameters and Test Conditions

Page 30 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 31] Basic IDD and IDDQ Measurement Conditions. Symbol Description IDD0 Operating One Bank Active-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between ACT and PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 32 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table32); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 32 IDD1 Operating One Bank Active-Read-Precharge Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between ACT, RD and PRE; Command, Address, Bank Address Inputs, Data IO: partially toggling according to Table 33 ; DM:stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table33); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 33 IDD2N Precharge Standby Current CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 34 ; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 34 DD2NT Precharge Standby ODT Current CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 35 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Sig- nal: toggling according to Table 35 ; Pattern Details: see Table 35 DDQ2NT (optional) Precharge Standby ODT IDDQ Current Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current IDD2P0 Precharge Power-Down Current Slow Exit CKE: Low; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pecharge Power Down Mode: Slow Exitc) IDD2P1 Precharge Power-Down Current Fast Exit CKE: Low; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pecharge Power Down Mode: Fast Exitc) IDD2Q Precharge Quiet Standby Current CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 IDD3N Active Standby Current CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: partially toggling according to Table 34 ; Data IO: FLOATING; DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Sig- nal: stable at 0; Pattern Details: see Table 34 IDD3P Active Power-Down Current CKE: Low; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: stable at 1; Command, Address, Bank Address Inputs: stable at 0; Data IO: FLOATING;DM:stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0 IDD4R Operating Burst Read Current CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between RD; Command, Address, Bank Address Inputs: partially tog- gling according to Table 36 ; Data IO: seamless read data burst with different data between one burst and the next one according to Table 36 ; DM:stable at 0; Bank Activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,... (see Table 7 on page 10); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 36 IDDQ4R (optional) Operating Burst Read IDDQ Current Same definition like for IDD4R, however measuring IDDQ current instead of IDD current IDD4W Operating Burst Write Current CKE: High; External clock: On; tCK, CL: see Table 30 ; BL: 8a); AL: 0; CS: High between WR; Command, Address, Bank Address Inputs: partially tog- gling according to Table 37 ; Data IO: seamless write data burst with different data between one burst and the next one according to Table 37; DM: stable at 0; Bank Activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,... (see Table 37); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at HIGH; Pattern Details: see Table 37 IDD5B Burst Refresh Current CKE: High; External clock: On; tCK, CL, nRFC: see Table 30 ; BL: 8a); AL: 0; CS: High between REF; Command, Address, Bank Address Inputs: par- tially toggling according to Table 38 ; Data IO: FLOATING;DM:stable at 0; Bank Activity: REF command every nRFC (see Table 38); Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 38 IDD6 Self Refresh Current: Normal Temperature Range TCASE: 0 - 85°C; Auto Self-Refresh (ASR): Disabledd); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 30 ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING

Page 31 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [Table 31] Basic IDD and IDDQ Measurement Conditions. a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range f) Refer to DRAM supplier data sheet and/or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device Symbol Description IDD6ET Self-Refresh Current: Extended Temperature Range (optional)f) TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Disabledd); Self-Refresh Temperature Range (SRT): Extendede); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 30 ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING;DM:stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING IDD6TC Auto Self-Refresh Current (optional)f) TCASE: 0 - 95°C; Auto Self-Refresh (ASR): Enabledd); Self-Refresh Temperature Range (SRT): Normale); CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 30 ; BL: 8a); AL: 0; CS, Command, Address, Bank Address, Data IO: FLOATING; DM:stable at 0; Bank Activity: Auto Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: FLOATING IDD7 Operating Bank Interleave Read Current CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Table 30 ; BL: 8a); AL: CL-1; CS: High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table 39 ; Data IO: read data bursts with different data between one burst and the next one according to Table 39 ; DM:stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see Table 39 ; Output Buffer and RTT: Enabled in Mode Registersb); ODT Signal: stable at 0; Pattern Details: see Table 39

10.2 IDD and IDDQ Specifications

Editorial Instruction: Chapter 10.2 in JESD79-3B in principal stays at it is. See Reference Material at the end of this ballot. Only the following changes will be done to Chapter 10.2: Table 53 "IDD Specification Example 512M DDR3", add the following Rows: - Between IDD2N and IDD2Q: Add 2 rows (one for x4/x8, one for x16) with a straddled cell for Symbol "IDD2NT". - Between IDD2NT (as inserted with above bullet) and IDD2Q: Add 2 rows (one for x4/x8, one for x16) with a straddled cell for Symbol ’IDDQ2NT". - Between IDD4R and IDD4W: Add 3 rows (one for x4, one for x8 and one for x16) with a straddled cell for Symbol "IDDQ4R".

Page 33 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [Table 32] IDD0 Measurement - Loop Pattern1 Note 1. DM must be driben LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. CK/CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) toggling Static High 0 0 A C T 00110 0 0 0 0000 - 1 , 2 D , D 10000 0 0 0 0000 - 3,4 D , D 11110 0 0 0 0000 - n R A S P R E 00100 0 0 0 0000 - 1 * n R C + 0 A C T 00110 0 00 0 0 F 0- 1 * n R C + 1 , 2 D , D 10000 0 00 0 0 F 0- 1*nRC + 3, 4 D , D 11110 0 00 0 0 F 0- 1*nRC + nRAS PRE 0 0 1 0 0 0 00 0 0 F 0 1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead

Page 34 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [Table 33] IDD1 Measurement - Loop Pattern1 Note : 1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL. CK/CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) toggling Static High 0 0 A C T 00110 0 0 0 0000 - 1 , 2 D , D 10000 0 0 0 0000 - 3,4 D , D 11110 0 0 0 0000 - n R C D R D 01010 0 00 0 0 0 0 00000000 n R A S P R E 00100 0 0 0 0000 - 1 * n R C + 0 A C T 00110 0 00 0 0 F 0- 1 * n R C + 1 , 2 D , D 10000 0 00 0 0 F 0- 1*nRC + 3, 4 D , D 11110 0 00 0 0 F 0- 1*nRC + nRCD RD 01010 0 00 0 0 F 0 00110011 1 * n R C + n R A S P R E 00100 0 00 0 0 F 0- 1 2*nRC repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 4*nRC repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 6*nRC repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 8*nRC repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 10*nRC repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 12*nRC repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 14*nRC repeat Sub-Loop 0, use BA[2:0] = 7 instead [Table 34] IDD2 and IDD3N Measurement - Loop Pattern1 Note : 1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL. CK/CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) toggling Static High 0 0 D 10000 0 0 0 0000 -

1 D 10000 0 0 0 0000 -

1 4-7 repeat Sub-Loop 0, use BA[2:0] = 1 instead 2 8-11 repeat Sub-Loop 0, use BA[2:0] = 2 instead 3 12-15 repeat Sub-Loop 0, use BA[2:0] = 3 instead 4 16-19 repeat Sub-Loop 0, use BA[2:0] = 4 instead 5 20-23 repeat Sub-Loop 0, use BA[2:0] = 5 instead 6 24-27 repeat Sub-Loop 0, use BA[2:0] = 6 instead 7 28-31 repeat Sub-Loop 0, use BA[2:0] = 7 instead

Page 35 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [Table 35] IDD2NT and IDDQ2NT Measurement - Loop Pattern1 Note : 1. DM must be driven Low all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL. CK/CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) toggling Static High 0 0 D 10000 0 0 0 0000 -

1 D 10000 0 0 0 0000

1 4-7 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 2 8-11 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 2 3 12-15 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 3 4 16-19 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 5 20-23 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 6 24-27 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 6 7 28-31 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 7 [Table 36] IDD4R and IDDQ4R Measurement - Loop Pattern1 Note : 1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL. CK/CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) toggling Static High 0 0 R D 01010 0 00 0 0 0 0 00000000 2,3 D ,D 11110 0 0 0 0000 -

4 R D 01010 0 00 0 0 F 0 00110011

5 D 10000 0 00 0 0 F 0-

6,7 D ,D 11110 0 00 0 0 F 0- 1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2 3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7

Page 36 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [Table 37] IDD4W Measurement - Loop Pattern1 Note : 1. DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL. CK/CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) toggling Static High 0 0 W R 01001 0 00 0 0 0 0 00000000

1 D 10001 0 0 0 0000 -

2,3 D ,D 11111 0 0 0 0000 -

4 W R 01001 0 00 0 0 F 0 00110011

5 D 10001 0 00 0 0 F 0-

6,7 D ,D 11111 0 00 0 0 F 0- 1 8-15 repeat Sub-Loop 0, but BA[2:0] = 1 2 16-23 repeat Sub-Loop 0, but BA[2:0] = 2 3 24-31 repeat Sub-Loop 0, but BA[2:0] = 3 4 32-39 repeat Sub-Loop 0, but BA[2:0] = 4 5 40-47 repeat Sub-Loop 0, but BA[2:0] = 5 6 48-55 repeat Sub-Loop 0, but BA[2:0] = 6 7 56-63 repeat Sub-Loop 0, but BA[2:0] = 7 [Table 38] IDD5B Measurement - Loop Pattern1 Note : 1. DM must be driven LOW all the time. DQS, DQS are MID-LEVEL. 2. DQ signals are MID-LEVEL. CK/CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) toggling Static High 0 0 R E F 00010 0 0 0 0000 - 1 1 , 2 D 10000 0 0 0 0000 - 3,4 D ,D 11110 0 00 0 0 F 0 -

Page 37 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [Table 39] IDD7 Measurement - Loop Pattern1 Note : 1. DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otheerwise MID-LEVEL. 2. Burst Sequence driven on each DQ signal by Read Command. Outside burst operation. DQ signals are MID-LEVEL. CK/CK CKE Sub-Loop Cycle Number Command CS RAS CAS WE ODT BA[2:0] A[15:11] A[10] A[9:7] A[6:3] A[2:0] Data2) toggling Static High

0 A C T 00110 0 00 0 0 0 0-

1 R D A 01010 0 00 1 0 0 0 00000000

2 D 11110 0 00 0 0 0 0-

... repeat above D Command until nRRD - 1 n R R D A C T 00110 1 00 0 0 F 0- nRRD + 1 RDA 01010 1 00 1 0 F 0 00110011 nRRD + 2 D 11110 1 00 0 0 F 0- ... repeat above D Command until nRRD - 1 2 2 * nRRD repeat Sub-Loop 0, but BA[2:0] = 2 3 3 * nRRD repeat Sub-Loop 0, but BA[2:0] = 3 4 4 * nRRD D 10000 3 00 0 0 F 0- Assert and repeat above D Command until nFAW - 1, if necessary 5 nFAW repeat Sub-Loop 0, but BA[2:0] = 4 6 nFAW+nRRD repeat Sub-Loop 0, but BA[2:0] = 5 7 nFAW+2*nRRD repeat Sub-Loop 0, but BA[2:0] = 6 8 nFAW+3*nRRD repeat Sub-Loop 0, but BA[2:0] = 7 9 nFAW+4*nRRD D 10000 7 00 0 0 F 0- Assert and repeat above D Command until 2*nFAW - 1, if necessary 2 * n F A W + 0 A C T 00110 0 00 0 0 F 0- 2 * n F A W + 1 R D A 01010 0 00 1 0 F 0 00110011 2*nFAW+2 D 11110 0 00 0 0 F 0- Repeat above D Command until 2*nFAW + nRRD - 1 2 * n F A W + n R R D A C T 00110 1 00 0 0 0 0- 2 * n F A W + n R R D + 1 R D A 01010 1 00 1 0 0 0 00000000 2*nFAW+nRRD+2 D 11110 1 00 0 0 0 0- Repeat above D Command until 2*nFAW + 2*nRRD - 1 12 2*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 2 13 2*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 3 14 2*nFAW+4*nRRD D 10000 3 00 0 0 0 0- Assert and repeat above D Command until 3*nFAW - 1, if necessary 15 3*nFAW repeat Sub-Loop 10, but BA[2:0] = 4 16 3*nFAW+nRRD repeat Sub-Loop 11, but BA[2:0] = 5 17 3*nFAW+2*nRRD repeat Sub-Loop 10, but BA[2:0] = 6 18 3*nFAW+3*nRRD repeat Sub-Loop 11, but BA[2:0] = 7 19 3*nFAW+4*nRRD D 10000 7 00 0 0 0 0- Assert and repeat above D Command until 4*nFAW - 1, if necessary

Page 38 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 40 ] IDD Specification for 1Gb DDR3 D-die Symbol 256Mx4 (K4B1G0446D) Unit NotesDDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 IDD0 75 85 90 TBD mA IDD1 95 105 110 TBD mA IDD2P0(slow exit) 10 11 12 TBD mA IDD2P1(fast exit) 35 45 50 TBD mA IDD2N 50 55 60 TBD mA IDD2NT 55 65 70 TBD mA IDD2Q 45 55 60 TBD mA IDD3P(fast exit) 40 45 50 TBD mA IDD3N 50 60 65 TBD mA IDD4R 115 155 185 TBD mA IDD4W 125 160 190 TBD mA IDD5B 205 210 220 TBD mA IDD6 10 10 10 TBD mA IDD7 240 265 340 TBD mA Symbol 128Mx8 (K4B1G0846D) Unit NotesDDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 IDD0 75 85 90 TBD mA IDD1 95 105 110 TBD mA IDD2P0(slow exit) 10 11 12 TBD mA IDD2P1(fast exit) 35 45 50 TBD mA IDD2N 50 55 60 TBD mA IDD2NT 55 65 75 TBD mA IDD2Q 45 55 60 TBD mA IDD3P(fast exit) 40 45 50 TBD mA IDD3N 50 60 65 TBD mA IDD4R 135 170 205 TBD mA IDD4W 145 190 230 TBD mA IDD5B 205 210 220 TBD mA IDD6 10 10 10 TBD mA IDD7 245 275 365 TBD mA 11.0 1Gb DDR3 SDRAM D-die IDD Spec Table

Page 39 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 40] IDD Specification for 1Gb DDR3 D-die(Cont.) Symbol 64Mx16 (K4B1G1646D) Unit NotesDDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 IDD0 85 90 100 TBD mA IDD1 120 125 135 TBD mA IDD2P0(slow exit) 10 11 12 TBD mA I D D 2 P 1 ( f a s t e x i t ) 3 54 55 0 T B D m A I D D 2 N 5 05 56 0 T B D m A IDD2NT 50 55 60 TBD mA I D D 2 Q 4 55 56 0 T B D m A IDD3P(fast exit) 40 45 50 TBD mA I D D 3 N 5 06 06 5 T B D m A IDD4R 180 230 290 TBD mA IDD4W 185 235 290 TBD mA IDD5B 205 210 220 TBD mA IDD6 10 10 10 TBD mA IDD7 280 310 370 TBD mA

Page 40 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 41 ] Input / Output Capacitance Note : 1. Although the DM, TDQS and TDQS pins have different functions, the loading matches DQ and DQS 2. This parameter is not subject to production test. It is verified by design and characterization. The capacitance is measured according to JEP147("PROCEDURE FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER( VNA)") with VDD, VDDQ, VSS, VSSQ applied and all other pins floating (except the pin under test, CKE, RESET and ODT as necessary). VDD=VDDQ=1.5V, VBIAS=VDD/2 and on-die termination off. 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. Absolute value of CCK-CCK 5. Absolute value of CIO(DQS)-CIO(DQS) 6. CI applies to ODT, CS, CKE, A0-A15, BA0-BA2, RAS, CAS, WE. 7. CDI_CTRL applies to ODT, CS and CKE 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CLK)+CI(CLK)) 9. CDI_ADD_CMD applies to A0-A15, BA0-BA2, RAS, CAS and WE 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CLK)+CI(CLK)) 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS)) 12. Maximum external load capacitance on ZQ pin: 5pF Parameter Symbol DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Notes Min Max Min Max Min Max Min Max Input/output capacitance Input capacitance Input capacitance delta (CK and CK) CDCK 0 0.15 0 0.15 0 0.15 0 0.15 pF 2,3,4 Input capacitance Input capacitance delta (DQS and DQS) CDDQS 0 0.2 0 0.2 0 0.15 0 0.15 pF 2,3,5 Input capacitance delta Input capacitance delta Input/output capacitance delta Input/output capacitance of ZQ pin CZQ - 3 - 3 - 3 - 3 pF 2, 3, 12

12.0 Input/Output Capacitance

Page 41 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D

13.1 Clock specification

The jitter specified is a random jitter meeting a Gaussian distribu tion. Input clocks violating the min/max values may result i n malfunction of the DDR3 SDRAM device.

13.1.1 Definition for tCK (avg)

tCK(avg) is calculated as the average cl ock period across any consec utive 200 cycle window, where eac h clock period is calculat ed from rising edge to rising edge.

13.1.2 Definition for tCK (abs)

tCK(abs) is the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK(abs) is not subject to production test.

13.1.3 Definition for tCH(avg) and tCL(avg)

tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses: tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses: ∑ ∑

13.1.4 Definition for note for tJIT(per), tJIT(per,lck)

tJIT(per) is defined as the largest deviation of any single tCK from tCK(avg). tJIT(per) = min/max of {tCKi-tCK(avg) where i=1 to 200} tJIT(per) defines the single period jitter when the DLL is already locked. tJIT(per,lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT(per) and tJIT(per,lck) are not subject to production test.

13.1.5 Definition for tJIT(cc), tJIT(cc,lck)

tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT(cc) = Max of {tCKi+1-tCKi} tJIT(cc) defines the cycle to cycle jitter when the DLL is already locked. tJIT(cc,lck) uses the same definition for cycle to cycle jitter, during the DLL locking period only. tJIT(cc) and tJIT(cc,lck) are not subject to production test.

13.1.6 Definition for tERR(nper)

tERR is defined as the cumulative error across n multiple consecutive cycles from tCK(avg). tERR is not subject to production test. N j=1 tCKj N N=200

13.0 Electrical Characteristics and AC timing for DDR3-800 to DDR3-1600

N j=1 tCHj N x tCK(avg) N=200 N j=1 tCLj N x tCK(avg) N=200

Page 42 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 42 ] Refresh parameters by device density Note : 1. Users should refer to the DRAM supplier data sheet and/or t he DIMM SPD to determine if DDR3 SDRAM devices support the follow ing options or requirements referred to in this material. Parameter Symbol 1Gb 2Gb 4Gb 8Gb Units Note All Bank Refresh to active/refresh cmd time tRFC 110 160 300 350 ns Average periodic refresh interval tREFI 0 °C ≤ TCASE ≤ 85°C 7.8 7.8 7.8 7.8 µs 85 °C < TCASE ≤ 95°C 3.9 3.9 3.9 3.9 µs 1

13.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin

DDR3 SDRAM Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin. [ Table 43 ] DDR3-800 Speed Bins Speed DDR3-800 Units NoteCL-nRCD-nRP 6 - 6 - 6 Parameter Symbol min max Intermal read command to first data tAA 15 20 ns ACT to internal read or write delay time tRCD 15 - ns PRE command period tRP 15 - ns ACT to ACT or REF command period tRC 52.5 - ns ACT to PRE command period tRAS 37.5 9*tREFI ns 8 CL = 6 / CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3 Supported CL Settings 6 nCK Supported CWL Settings 5 nCK [ Table 44 ] DDR3-1066 Speed Bins Speed DDR3-1066 Units NoteCL-nRCD-nRP 7 - 7 - 7 Parameter Symbol min max Intermal read command to first data tAA 13.125 20 ns ACT to internal read or write delay time tRCD 13.125 - ns PRE command period tRP 13.125 - ns ACT to ACT or REF command period tRC 50.625 - ns ACT to PRE command period tRAS 37.5 9*tREFI ns 8 CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,6 CWL = 6 tCK(AVG) Reserved ns 1,2,3,4 CL = 7 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4 CL = 8 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3 Supported CL Settings 6,7,8 nCK Supported CWL Settings 5,6 nCK

13.2 Refresh Parameters by Device Density

Page 43 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 45] DDR3-1333 Speed Bins Speed DDR3-1333 Units NoteCL-nRCD-nRP 9 -9 - 9 Parameter Symbol min max Intermal read command to first data tAA 13.5 20 ns ACT to internal read or write delay time tRCD 13.5 - ns PRE command period tRP 13.5 - ns ACT to ACT or REF command period tRC 49.5 - ns ACT to PRE command period tRAS 36 9*tREFI ns 8 CL = 6 CWL = 5 tCK(AVG) 2.5 3.3 ns 1,2,3,7 CWL = 6 tCK(AVG) Reserved ns 1,2,3,4,7 CWL = 7 tCK(AVG) Reserved ns 4 CL = 7 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,4,7 CWL = 7 tCK(AVG) Reserved ns 1,2,3,4, CL = 8 CWL = 5 tCK(AVG) Reserved ns 4 CWL = 6 tCK(AVG) 1.875 <2.5 ns 1,2,3,7 CWL = 7 tCK(AVG) Reserved ns 1,2,3,4, CL = 9 CWL = 5,6 tCK(AVG) Reserved ns 4 CWL = 7 tCK(AVG) 1.5 <1.875 ns 1,2,3,4 CL = 10 CWL = 5,6 tCK(AVG) Reserved ns 4 CWL = 7 tCK(AVG) (Optional) ns 5 Supported CL Settings 6,7,8,9 nCK Supported CWL Settings 5,6,7 nCK

Page 44 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 46 ] DDR3-1600 Speed Bins Speed DDR3-1600 Units NoteCL-nRCD-nRP TBD Parameter Symbol min max Intermal read command to first data tAA TBD 20 ns ACT to internal read or write delay time tRCD TBD - ns PRE command period tRP TBD - ns ACT to ACT or REF command period tRC TBD - ns ACT to PRE command period tRAS 35 9*tREFI ns CL = 6 CWL = 5 tCK(AVG) TBD ns CWL = 6 tCK(AVG) TBD ns CWL = 7, 8 tCK(AVG) TBD ns CL = 7 CWL = 5 tCK(AVG) TBD ns CWL = 6 tCK(AVG) TBD ns CWL = 7 tCK(AVG) TBD ns CWL = 8 tCK(AVG) TBD ns CL = 8 CWL = 5 tCK(AVG) TBD ns CWL = 6 tCK(AVG) TBD ns CWL = 7 tCK(AVG) TBD ns CWL = 8 tCK(AVG) TBD ns CL = 9 CWL = 5,6 tCK(AVG) TBD ns CWL = 7 tCK(AVG) TBD ns CWL = 8 tCK(AVG) TBD ns CL = 10 CWL = 5,6 tCK(AVG) TBD ns CWL = 7 tCK(AVG) TBD ns CWL = 8 tCK(AVG) TBD ns CL = 11 CWL = 5,6,7 tCK(AVG) TBD ns CWL = 8 tCK(AVG) TBD ns TBD ns Supported CL Settings TBD nCK Supported CWL Settings TBD nCK Absolute Specification (TOPER; VDDQ = VDD = 1.5V +/- 0.075 V); Note : 1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be ful- filled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequen- CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next "SupportedCL". 4. "Reserved" settings are not allowed. User must program a different value. 5. "Optional" settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to supplier’s data sheet and/ or the DIMM SPD information if and how this setting is supported. 6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization. 8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.

13.3.1 Speed Bin Table Notes

Page 45 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 47 ] Timing Parameters by Speed Bin Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Note Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX Clock Timing Minimum Clock Cycle Time (DLL off mode) tCK(DLL_OF F) 8 - 8 - 8 - 8 - ns 6 Average Clock Period tCK(avg) See Speed Bins Table ps Clock Period tCK(abs) tCK(avg)min + tJIT(per)min tCK(avg)max + tJIT(per)max tCK(avg)min + tJIT(per)min tCK(avg)max + tJIT(per)max tCK(avg)min + tJIT(per)min tCK(avg)max + tJIT(per)max tCK(avg)min + tJIT(per)min tCK(avg)max + tJIT(per)max ps Clock Period Jitter tJIT(per) -100 100 -90 90 -80 80 -70 70 ps Clock Period Jitter during DLL locking period tJIT(per, lck) -90 90 -80 80 -70 70 -60 60 ps Cycle to Cycle Period Jitter tJIT(cc) 200 180 160 140 ps Cycle to Cycle Period Jitter during DLL locking period tJIT(cc, lck) 180 160 140 120 ps Cumulative error across 2 cycles tERR(2per) - 147 147 - 132 132 - 118 118 -103 103 ps Cumulative error across 3 cycles tERR(3per) - 175 175 - 157 157 - 140 140 -122 122 ps Cumulative error across 4 cycles tERR(4per) - 194 194 - 175 175 - 155 155 -136 136 ps Cumulative error across 5 cycles tERR(5per) - 209 209 - 188 188 - 168 168 -147 147 ps Cumulative error across 6 cycles tERR(6per) - 222 222 - 200 200 - 177 177 -155 155 ps Cumulative error across 7 cycles tERR(7per) - 232 232 - 209 209 - 186 186 -163 163 ps Cumulative error across 8 cycles tERR(8per) - 241 241 - 217 217 - 193 193 -169 169 ps Cumulative error across 9 cycles tERR(9per) - 249 249 - 224 224 - 200 200 -175 175 ps Cumulative error across 10 cycles tERR(10per) - 257 257 - 231 231 - 205 205 -180 180 ps Cumulative error across 11 cycles tERR(11per) - 263 263 - 237 237 - 210 210 -184 184 ps Cumulative error across 12 cycles tERR(12per) - 269 269 - 242 242 - 215 215 -188 188 ps Cumulative error across n = 13, 14 ... 49, 50 cycles tERR(nper) tERR(nper)min = (1 + 0.68ln(n))*tJIT(per)min tERR(nper)max = (1 = 0.68ln(n))*tJIT(per)max ps 24 Absolute clock HIGH pulse width tCH(abs) 0.43 - 0.43 - 0.43 - 0.43 - tCK(avg) 25 Absolute clock Low pulse width tCL(abs) 0.43 - 0.43 - 0.43 - 0.43 - tCK(avg) 26 Data Timing DQS,DQS to DQ skew, per group, per access tDQSQ - 200 - 150 - 125 - 100 ps 13 DQ output hold time from DQS, DQS tQH 0.38 - 0.38 - 0.38 - 0.38 - tCK(avg) 13, g DQ low-impedance time from CK, CK tLZ(DQ) -800 400 -600 300 -500 250 -450 225 ps 13,14, f DQ high-impedance time from CK, CK tHZ(DQ) - 400 - 300 - 250 - 225 ps 13,14, f Data setup time to DQS, DQS referenced to VIH(AC)VIL(AC) levels tDS(base) 75 - 25 - 30 - 10 ps d, 17 Data hold time to DQS, DQS referenced to VIH(AC)VIL(AC) levels tDH(base) 150 - 100 - 65 - 45 ps d, 17 DQ and DM Input pulse width for each input tDIPW 600 - 490 - 400 - 360 ps 28 Data Strobe Timing DQS, DQS READ Preamble tRPRE 0.9 Note 19 0.9 Note 19 0.9 Note 19 0.9 Note 19 tCK 13, 19, g DQS, DQS differential READ Postamble tRPST 0.3 Note 11 0.3 Note 11 0.3 Note 11 0.3 Note 11 tCK 11, 13, b DQS, DQS output high time tQSH 0.38 - 0.38 - 0.4 - 0.4 - tCK(avg) 13, g DQS, DQS output low time tQSL 0.38 - 0.38 - 0.4 - 0.4 - tCK(avg) 13, g DQS, DQS WRITE Preamble tWPRE 0.9 - 0.9 - 0.9 - 0.9 - tCK DQS, DQS WRITE Postamble tWPST 0.3 - 0.3 - 0.3 - 0.3 - tCK DQS, DQS rising edge output access time from rising CK, CK tDQSCK -400 400 -300 300 -255 255 -225 225 ps 13,f DQS, DQS low-impedance time (Referenced from RL-1) tLZ(DQS) -800 400 -600 300 -500 250 -450 225 ps 13,14,f DQS, DQS high-impedance time (Referenced from RL+BL/2) tHZ(DQS) - 400 - 300 - 250 - 225 ps 12,13,14 DQS,DQS faling edge setup time to CK, CK rising edge tDSS 0.2 - 0.2 - 0.2 - 0.18 - tCK(avg) c, 32 DQS,DQS faling edge hold time to CK, CK rising edge tDSH 0.2 - 0.2 - 0.2 - 0.18 - tCK(avg) c, 32

14.0 Timing Parameters by Speed Grade

Page 46 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 47 ] Timing Parameters by Speed Bin (Cont.) Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Note Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX Command and Address Timing DLL locking time tDLLK 512 - 512 - 512 - 512 - nCK internal READ Command to PRECHARGE Command delay tRTP max (4nCK,7.5ns) - max (4nCK,7.5ns) - max (4nCK,7.5ns) - max (4nCK,7.5ns) - e Delay from start of internal write transaction to internal read command tWTR max (4nCK,7.5ns) - max (4nCK,7.5ns) - max (4nCK,7.5ns) - max (4nCK,7.5ns) - e,18 WRITE recovery time tWR 15 - 15 - 15 - 15 - ns e Mode Register Set command cycle time tMRD 4 - 4 - 4 - 4 - nCK Mode Register Set command update delay tMOD max (12nCK,15ns max (12nCK,15ns max (12nCK,15ns max (12nCK,15ns CAS# to CAS# command delay tCCD 4 - 4 - 4 - 4 - nCK Auto precharge write recovery + precharge time tDAL(min) WR + roundup (tRP / tCK(AVG)) nCK Multi-Purpose Register Recovery Time tMPRR 1 - 1 - 1 - 1 - nCK 22 ACTIVE to PRECHARGE command period tRAS See 13.3 " Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin" on page 37 ns e ACTIVE to ACTIVE command period for 1KB page size tRRD max (4nCK,10ns) - max (4nCK,7.5ns) - max (4nCK,6ns) - max (4nCK,6ns) - e ACTIVE to ACTIVE command period for 2KB page size tRRD max (4nCK,10ns) - max (4nCK,10ns) - max (4nCK,7.5ns) - max (4nCK,7.5ns) - e Four activate window for 1KB page size tFAW 40 - 37.5 - 30 - 30 - ns e Four activate window for 2KB page size tFAW 50 - 50 - 45 - 40 - ns e Command and Address setup time to CK, CK refer- enced to VIH(AC) / VIL(AC) levels tIS(base) 200 - 125 - 65 - TBD - ps b,16 Command and Address hold time from CK, CK refer- enced to VIH(AC) / VIL(AC) levels tIH(base) 275 - 200 - 140 - TBD - ps b,16 Command and Address setup time to CK, CK refer- enced to VIH(AC) / VIL(AC) levels tIS(base) AC150 200 + 150 - 125 + 150 - 65+125 - TBD+125 - ps b,16,27 Control & Address Input pulse width for each input tIPW 900 - 780 - 620 - 560 - ps 28 Calibration Timing Power-up and RESET calibration time tZQinitI 512 - 512 - 512 - 512 - nCK Normal operation Full calibration time tZQoper 256 - 256 - 256 - 256 - nCK Normal operation short calibration time tZQCS 64 - 64 - 64 - 64 - nCK 23 Reset Timing Exit Reset from CKE HIGH to a valid command tXPR max(5nCK, tRFC + 10ns) - max(5nCK, tRFC + 10ns) - max(5nCK, tRFC + 10ns) - max(5nCK, tRFC + 10ns) - Self Refresh Timing Exit Self Refresh to commands not requiring a locked DLL tXS max(5nCK,tR FC + 10ns) - max(5nCK,tR FC + 10ns) - max(5nCK,tR FC + 10ns) - max(5nCK,tR FC + 10ns) - Exit Self Refresh to commands requiring a locked DLL tXSDLL tDLLK(min) - tDLLK(min) - tDLLK(min) - tDLLK(min) - nCK Minimum CKE low width for Self refresh entry to exit timing tCKESR tCKE(min) + 1tCK - tCKE(min) + 1tCK - tCKE(min) + 1tCK - tCKE(min) + 1tCK - Valid Clock Requirement after Self Refresh Entry (SRE) or Power-Down Entry (PDE) tCKSRE max(5nCK, 10ns) - max(5nCK, 10ns) - max(5nCK, 10ns) - max(5nCK, 10ns) - Valid Clock Requirement before Self Refresh Exit (SRX) or Power-Down Exit (PDX) or Reset Exit tCKSRX max(5nCK, 10ns) - max(5nCK, 10ns) - max(5nCK, 10ns) - max(5nCK, 10ns) -

Page 47 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 47 ] Timing Parameters by Speed Bin (Cont.) Speed DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 Units Note Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX Power Down Timing Exit Power Down with DLL on to any valid com- mand;Exit Percharge Power Down with DLL frozen to commands not requiring a locked DLL tXP max (3nCK, 7.5ns) max (3nCK, 7.5ns) - max (3nCK,6ns) - max (3nCK,6ns) - Exit Precharge Power Down with DLL frozen to com- mands requiring a locked DLL tXPDLL max (10nCK, 24ns) max (10nCK, 24ns) max (10nCK, 24ns) max (10nCK, 24ns) - 2 CKE minimum pulse width tCKE max (3nCK, 7.5ns) max (3nCK, 5.625ns) max (3nCK, 5.625ns) - max (3nCK,5ns) - Command pass disable delay tCPDED 1 - 1 - 1 - 1 - nCK Power Down Entry to Exit Timing tPD tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCKE(min) 9*tREFI tCK 15 Timing of ACT command to Power Down entry tACTPDEN 1 - 1 - 1 - 1 - nCK 20 Timing of PRE command to Power Down entry tPRPDEN 1 - 1 - 1 - 1 - nCK 20 Timing of RD/RDA command to Power Down entry tRDPDEN RL + 4 +1 - RL + 4 +1 - RL + 4 +1 - RL + 4 +1 - Timing of WR command to Power Down entry (BL8OTF, BL8MRS, BL4OTF) tWRPDEN WL + 4 +(tWR/ tCK(avg)) WL + 4 +(tWR/ tCK(avg)) WL + 4 +(tWR/ tCK(avg)) WL + 4 +(tWR/ tCK(avg)) - nCK 9 Timing of WRA command to Power Down entry (BL8OTF, BL8MRS, BL4OTF) tWRAPDEN WL + 4 +WR +1 - WL + 4 +WR +1 - WL + 4 +WR +1 - WL + 4 +WR +1 - nCK 10 Timing of WR command to Power Down entry (BL4MRS) tWRPDEN WL + 2 +(tWR/ tCK(avg)) WL + 2 +(tWR/ tCK(avg)) WL + 2 +(tWR/ tCK(avg)) WL + 2 +(tWR/ tCK(avg)) - nCK 9 Timing of WRA command to Power Down entry (BL4MRS) tWRAPDEN WL +2 +WR +1 - WL +2 +WR +1 - WL +2 +WR +1 - WL +2 +WR +1 - nCK 10 Timing of REF command to Power Down entry tREFPDEN 1 - 1 - 1 - 1 - 20,21 Timing of MRS command to Power Down entry tMRSPDEN tMOD(min) - tMOD(min) - tMOD(min) - tMOD(min) - ODT Timing ODT high time without write command or with wirte command and BC4 ODTH4 4 - 4 - 4 - 4 - nCK ODT high time with Write command and BL8 ODTH8 6 - 6 - 6 - 6 - nCK Asynchronous RTT tum-on delay (Power-Down with DLL frozen) tAONPD 2 8.5 2 8.5 2 8.5 2 8.5 ns Asynchronous RTT tum-off delay (Power-Down with DLL frozen) tAOFPD 2 8.5 2 8.5 2 8.5 2 8.5 ns ODT turn-on tAON -400 400 -300 300 -250 250 -225 225 ps 7,f RTT_NOM and RTT_WR turn-off time from ODTLoff reference Write Leveling Timing First DQS pulse rising edge after tDQSS margining mode is programmed tWLMRD 40 - 40 - 40 - 40 - tCK 3 DQS/DQS delay after tDQS margining mode is pro- grammed tWLDQSEN 25 - 25 - 25 - 25 - tCK 3 Setup time for tDQSS latch tWLS 325 - 245 - 195 - 165 - ps Write leveling hold time from rising DQS, DQS cross- ing to rising CK, CK crossing tWLH 325 - 245 - 195 - 165 - ps Write leveling output delay tWLO 0 9 0 9 0 9 0 7.5 ns Write leveling output error tWLOE 0 2 0 2 0 2 0 2 ns

Page 48 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D

14.1 Jitter Notes

Specific Note a Unit ’tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ’nCK’ represents one clock cycle of the input clock, counting the actual cloc k edges.ex) tMRD = 4 [nCK] means; if one Mode Register Set command is registered at Tm, another Mode Register Set command may be registered at Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min. Specific Note b These parameters are measured from a command/address signal (CKE, CS , RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK ) crossing. The spec values are not affected by the amount of clock jitte r applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these param- eters should be met whether clock jitter is present or not. Specific Note c These parameters are measured from a data strobe signal (DQS(L/U), DQS (L/U)) crossing to its respective clock signal (CK, CK ) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. Specific Note d These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to its respective data strobe signal (DQS(L/U), DQS(L/U)) crossing. Specific Note e For these paramete rs, the DDR3 SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg) [ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(av g)}, which is in clock cycles, if all i nput clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP = RU{tRP / tCK(avg)} = 6, as long as the input clock jitter specifi- cations are met, i.e. Precharge command at Tm and Active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter. Specific Note f When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = - 172 ps and tERR(mper),act,max = + 193 ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = - 400 ps - 193 ps = - 593 ps and tDQSCK,max(derated) = tDQSCK,max - tERR(mper),act,min = 400 ps + 172 ps = + 572 ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) = - 800 ps - 193 ps = - 993 ps and tLZ(DQ),max(derated) = 400 ps + 172 ps = + 572 ps. (Caution on the min/max usage!) Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 <= n <= 12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 <= n <= 12. Specific Note g When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (out- put deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act = 2500 ps, tJIT(per),act,min = - 72 ps and tJIT(per),act,max = + 93 ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500 ps - 72 ps = + 2178 ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,m in = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500 ps - 72 ps = + 878 ps. (Caution on the min/max usage!)

Page 49 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D ZQCorrection (TSens x Tdriftrate) + (VSens x Vdriftrate) 0.5 = 0.133 ~~ 128ms

14.2 Timing Parameter Notes

1. Actual value dependant upon measurement level definitions which are TBD. 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register 5. Value must be rounded-up to next higher integer value 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7. For definition of RTT turn-on time tAON see "Device Operation" 8. For definition of RTT turn-off time tAOF see "Device Operation". 9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer. 10. WR in clock cycles as programmed in MR0 11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the right side. Device Operation. 12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated by TBD 13. Value is valid for RON34 14. Single ended signal parameter. Refer to chapter 8 and chapter 9 for definition and measurement method. 15. tREFI depends on T OPER 16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK differential slew rate, Note for DQ and DM signals, V REF(DC) = VREFDQ(DC). FOr input only pins except RESET, VREF(DC)=VREFCA(DC). See "Address/ Command Setup, Hold and Derating" 17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS differential slew rate. Note for DQ and DM signals, V REF(DC)= VREFDQ(DC). For input only pins except RESET, VREF(DC)=VREFCA(DC). See "Data Setup, Hold and Slew Rate Derating" 18. Start of internal write transaction is definited as follows ; For BL8 (fixed by MRS and on-the-fly) : Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly) : Rising clock edge 4 clock cycles after WL For BC4 (fixed by MRS) : Rising clock edge 2 clock cycles after WL 19. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side. See "Device Operation" 20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. 21. Altough CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there are cases where additional time such as tXPDLL(min) is also required. See "Device Operation". 22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function. 23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQCorrection) of RON and RTT impedance error within 64 nCK for all speed bins assuming the maximum sensitivities specified in the ’Output Driver Voltage and Temperature Sensitivity’ and ’ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval between ZQCS commands can be determined from these tables and other application specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is sub- ject to in the application, is illustrated. The interval could be defined by the following formula: where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 1.5% / °C, VSens = 0.15% / mV, Tdriftrate = 1 °C / sec and Vdriftrate = 15 mV / sec, then the interval between ZQCS commands is calcu- lated as: 24. n = from 13 cycles to 50 cycles. This row defines 38 parameters. 25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. 27. The tIS(base) AC150 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of derating to accommodate for the lower alter- nate threshold of 150 mV and another 25 ps to account for the earlier reference point [(175 mv - 150 mV) / 1 V/ns]. 28. Pulse width of a input signal is defined as the width between the first crossing of V REF(DC) and the consecutive crossing of VREF(DC) 29. tDQSL describes the instantaneous differential input low pulse width on DQS-DQS, as measured from one falling edge to the next consecutive rising edge. 30. tDQSH describes the instantaneous differential input high pulse width on DQS-DQS, as measured from one rising edge to the next consecutive falling edge. 31. tDQSH, act + tDQSL, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application. 32. tDSH, act + tDSS, act = 1 tCK, act ; with tXYZ, act being the actual measured value of the respective timing parameter in the application.

Page 50 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see Table 48) to the ∆tIS and ∆tIH derating value (see Table 49) respectively. Example: tIS (total setup time) = tIS(base) + ∆tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(DC) to ac region’, use nominal slew rate for derating value (see Figure 23). If the actual signal is later than the nominal slew rate line anywhere between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac le vel to dc level is used for derating value (see Figure 25). Hold (tIH) nominal slew rate for a rising signal is def ined as the slew rate between the last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min and the first crossing of VREF(DC). If the actual signal is always later than the nom inal slew rate line between shaded ’dc to VREF(DC) region’, use nominal slew rate for derating value (see Figure 24). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 26). For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 50). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC). For slew rates in between the values listed in Table 51, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. [ Table 48] ADD/CMD Setup and Hold Base-Values for 1V/ns Note : AC/DC referenced for 1V/ns DQ-slew rate and 2V/ns DQS slew rate Note : The tIS(base)-AC150 specifications are further adjusted to add an addi-tional 100ps of derating to accommodate for the lower alternate thresh-old of 150mV and another 25ps to acccount for the earlier reference point [(175mv-150mV)/1 V/ns]. [ps] DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 reference tIS(base) 200 125 65 45 V IH/L(AC) tIH(base) 275 200 140 120 V IH/L(DC) tIS(base)-AC150 200 + 150 125 + 150 65+125 45+125 V IH/L(AC) [ Table 49] Derating values DDR3-800/1066/1333/1600 tIS/tIH-ac/dc based ∆tIS, ∆tIH Derating [ps] AC/DC based AC175 Threshold -> VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV CLK,CLK Differential Slew Rate CMD/ ADD Slew rate V/ns 2 . 0 8 85 08 85 08 85 09 65 8 1 0 4 6 6 1 1 2 7 4 1 2 0 8 4 1 2 8 1 0 0 1 . 5 5 93 45 93 45 93 46 74 27 55 08 35 89 16 89 98 4 1 . 0 00000088 1 6 1 6 2 4 2 4 3 2 3 4 4 0 5 0 0 . 9- 2 - 4 - 2 - 4 - 2 - 4 6 4 1 41 22 02 03 03 03 84 6 0.8 -6 -10 -6 -10 -6 -10 2 -2 10 6 13 14 26 24 34 40 0.7 -11 -16 -11 -16 -11 -16 -3 -8 5 0 13 8 21 18 29 34 0.6 -17 -26 -17 -26 -17 -26 -9 -18 -1 -10 7 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -27 -32 -19 -24 -11 -16 -2 -6 5 10

14.3 Address / Command Setup, Hold and Derating:

Page 51 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D [ Table 50 ] Derating values DDR3-1333/1600 tIS/tIH-ac/dc based - Alternate AC150 Threshold [ Table 51 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition ∆tIS, ∆tIH Derating [ps] AC/DC based Alternate AC150 Threshold -> VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV CLK,CLK Differential Slew Rate CMD/ ADD Slew rate V/ns 2 . 0 7 55 07 55 07 55 08 35 89 16 69 97 4 1 0 7 8 4 1 1 5 1 0 0 1 . 5 5 03 45 03 45 03 45 84 26 65 07 45 88 26 89 08 4 1 . 0 00000088 1 6 1 6 2 4 2 4 3 2 3 4 4 0 5 0 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0 . 8 0- 1 00- 1 00- 1 08 - 21 6 6 2 41 43 22 44 04 0 0.7 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 -26 -1 -26 -1 -26 7 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -17 -52 -9 -44 -1 -36 7 -26 15 -10 Slew Rate[V/ns] tVAC @175mV [ps] tVAC @150mV [ps] min max min max >2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 150 - < 0.5 0 - 150 -

Page 52 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D VSS CK CK tDS tDH Setup Slew RateSetup Slew Rate Rising SignalFalling Signal Delta TF Delta TR VREF(DC) - VIL(AC)max Delta TF= VIH(AC)min - VREF(DC) Delta TR= VDDQ VIH(AC) min VIH(DC) min VREF(DC) VIL(DC) max VIL(AC) max nominal slew rate nominal slew rate VREF to ac region VREF to ac region Figure 21 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock). tIS tIH tDS tDH tIS tIH tVAC tVAC Note :Clock and Strobe are drawn on a different time scale. DQS DQS

Page 53 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D VSS CK CK Hold Slew RateHold Slew Rate Falling SignalRising Signal Delta TR Delta TF VREF(DC) - VIL(DC)max Delta TR= VIH(DC)min - VREF(DC) Delta TF= VDDQ VIH(AC) min VIH(DC) min VREF(DC) VIL(DC) max VIL(AC) max nominal slew rate nominal slew rate dc to VREF region dc to VREF region Figure 22 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock). tIS tIH tIS tIH dc to VREF region Note :Clock and Strobe are drawn on a different time scale. tDS tDH tDS tDH DQS DQS

Figure 23. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS Note :Clock and Strobe are drawn on a different time scale.

Page 55 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D VSS Hold Slew Rate Delta TFDelta TR tangent line [ VIH(DC)min - VREF(DC) ] Delta TF= VDDQ VIH(AC) min VIH(DC) min VREF(DC) VIL(DC) max VIL(AC) max tangent tangent dc to VREF region dc to VREF region line line nominal line nominal line Falling Signal Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ] Delta TR= Rising Signal Figure 24 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock) CK CK tIS tIH tIS tIH Note :Clock and Strobe are drawn on a different time scale. tDS tDH tDS tDH DQS DQS

Page 56 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D For all input signals the total tDS (setup time) and tDH (hold time) required is calc ulated by adding the data sheet tDS(base) and tDH(base) value (see Table 52) to the ∆ tDS and ∆tDH (see Table 53) derating value respectively. Example: tDS (total setup time) = tDS(base) + ∆tDS. Setup (tDS) nominal slew rate for a ri sing signal is defined as the slew rate between the last crossing of V REF(DC) and the first crossing of V IH(AC)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V REF(DC) and the first crossing of V IL(AC)max (see Figure 25). If the actual signal is always earli er than the nominal slew rate line between shaded ’VREF(DC) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the nominal slew rate line anywhere between shaded ’VREF(DC) to ac region’, the slew rate of a tangent line to the act ual signal from the ac level to dc level is used for derating val ue (see Figure 27). Hold (tDH) nominal slew rate for a rising signal is def ined as the slew rate between the last crossing of V IL(DC)max and the first crossing of V REF(DC). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of V IH(DC)min and the first crossing of V REF(DC) (see Figure 26). If the actual signal is always later than the nominal slew rate line between shaded ’dc level to VREF(DC) region’, use nominal slew rate for derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 28). For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 54). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached V IH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC). For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization [ Table 52 ] Data Setup and Hold Base-Value Note : AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate) [ Table 53 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-ac/dc based Note : a. Cell contents shaded in red are defined as ’not supported’. [ Table 54 ] Required time tVAC above VIH(AC) {blow VIL(AC)} for valid transition [ps] DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 reference tDS(base) 75 25 30 10 V IH/L(AC) tDH(base) 150 100 65 45 V IH/L(DC) ∆tDS, ∆tDH Derating [ps] AC/DC baseda DQS,DQS Differential Slew Rate DDR3 800/ 1066 DQ Slew rate V/ns 2 . 0 8 85 08 85 08 85 0 - - - - - - - - - - 1 . 5 5 93 45 93 45 93 46 74 2 - - - - - - - - 1 . 0 00000088 1 6 1 6 - - - - - - 0 . 9 - - - 2- 4- 2- 4 6 41 4 1 2 2 2 2 0 - - - - 0.8 - - - - -6 -10 2 -2 10 6 18 14 26 24 - - 0.7 - - - - - - -3 -8 5 0 13 8 21 18 29 34 DDR3 1333/ 1600 DQ Slew rate V/ns 2 . 0 7 55 07 55 07 55 0 - - - - - - - - - - 1 . 5 5 03 45 03 45 03 45 84 2 - - - - - - - - 1 . 0 00000088 1 6 1 6 - - - - - - 0 . 9 - - 0 - 4 0 - 4 8 4 1 61 22 42 0 - - - - 0.8 - - - - 0 -10 8 -2 16 6 24 14 32 24 - - 0.7 - - - - - - 8 -8 16 0 24 8 32 18 40 34 Slew Rate[V/ns] tVAC[ps] DDR3-800/1066 tVAC[ps] DDR3-1333/1600 min max min max >2.0 75 - 175 - 2.0 57 - 170 - 1.5 50 - 167 - 1.0 38 - 163 - 0.9 34 - 162 - 0.8 29 - 161 - 0.7 22 - 159 - 0.6 13 - 155 - 0.5 0 - 155 - <0.5 0 - 150 -

14.4 Data Setup, Hold and Slew Rate Derating:

Page 57 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D VSS CK CK tDS tDH Setup Slew RateSetup Slew Rate Rising SignalFalling Signal Delta TF Delta TR VREF(DC) - VIL(AC)max Delta TF = VIH(AC)min - VREF(DC) Delta TR VDDQ VIH(AC) min VIH(DC) min VREF(DC) VIL(DC) max VIL(AC) max nominal slew rate nominal slew rate VREF to ac region VREF to ac region Figure 25 - Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock). tIS tIH tDS tDH tIS tIH tVAC tVAC Note :Clock and Strobe are drawn on a different time scale. DQS DQS

Page 58 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D VSS CK CK Hold Slew RateHold Slew Rate Falling SignalRising Signal Delta TR Delta TF VREF(DC) - VIL(DC)max Delta TR VIH(DC)min - VREF(DC) Delta TF VDDQ VIH(AC) min VIH(DC) min VREF(DC) VIL(DC) max VIL(AC) max nominal slew rate nominal slew rate dc to VREF region dc to VREF region Figure 26 - Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock). tIS tIH tIS tIH dc to VREF region Note :Clock and Strobe are drawn on a different time scale. tDS tDH tDS tDH DQS DQS

Page 59 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D VSS Setup Slew Rate Setup Slew Rate Rising Signal Falling Signal Delta TF Delta TR tangent line[VREF(DC) - VIL(AC)max] Delta TF= tangent line[VIH(AC)min - VREF(DC)] Delta TR= VDDQ VIH(AC) min VIH(DC) min VREF(DC) VIL(DC) max VIL(AC) max tangent tangent VREF to ac region VREF to ac region line line nominal line nominal line Figure 27 - Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS (for ADD/CMD with respect to clock) CK CK tIS tIH tIS tIH tVAC Note :Clock and Strobe are drawn on a different time scale. tDS tDH tDS tDH DQS DQS

Page 60 of 60 Rev. 1.1 August 2008 1Gb DDR3 SDRAMK4B1G04(08/16)46D VSS Hold Slew Rate Delta TFDelta TR tangent line [ VIH(DC)min - VREF(DC) ] Delta TF= VDDQ VIH(AC) min VIH(DC) min VREF(DC) VIL(DC) max VIL(AC) max tangent tangent dc to VREF region dc to VREF region line line nominal line nominal line Falling Signal Hold Slew Rate tangent line [ VREF(DC) - VIL(DC)max ] Delta TR= Rising Signal Figure 28 - Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH (for ADD/CMD with respect to clock) CK CK tIS tIH tIS tIH Note :Clock and Strobe are drawn on a different time scale. tDS tDH tDS tDH DQS DQS