K3P6C2000B-SC SAMSUNG | Alldatasheet

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K3P6C2000B-SC CMOS MASK ROM Pin Name Pin Function A 0 - A 1 Page Address Inputs A 2 - A 19 Address Inputs Q 0 - Q 30 Data Outputs Q 31 /A -1 Output 31(Double word mode)/ LSB Address(Word mode) WORD Double word/Word mode selection CE Chip Enable OE Output Enable V CC Power (+5V) V SS Ground N.C No Connection 32M-Bit (2Mx16 /1Mx32) CMOS MASK ROM The K3P6C2000B-SC is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 2,097,152x16 bit(word mode) or as 1,048,576x32 bit(double word mode) depending on WORD voltage level.(See mode selection table) This device includes page read mode function, page read mode allows 4 double words(or 8 words) of data to read fast in the same page, CE and A 2 ~ A 19 should not be changed. This device operates with a 5V single power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The K3P6C2000B-SC is packaged in a 70-SSOP. GENERAL DESCRIPTIONFEATURES

  • Switchable organization 2,097,152 x 16(word mode) 1,048,576 x 32(double word mode)
  • Fast access time Random Access : 100ns(Max.) Page Access : 30ns(Max.)
  • 4 double words/ 8 words page access
  • Current consumption Operating : 150mA(Max.) Standby : 50 µA(Max.)
  • Fully static operation
  • All inputs and outputs TTL compatible
  • Three state outputs
  • Package -. K3P6C2000B-SC : 70-SSOP-500 PIN CONFIGURATION A 0 A 1 A 2 A 3 A 4 A 5 V CC Q 0 Q 16 Q 1 Q 17 V SS V CC Q 2 Q 18 Q 3 Q 19 Q 4 Q 20 Q 5 Q 21 V SS V CC Q 6 Q 22 Q 7 Q 23 V SS A 6 A 7 A 8 A 9 A 10 A 11 A 12

35 A 13

N.C N.C N.C SSOP K3P6C2000B-SC FUNCTIONAL BLOCK DIAGRAM A 19 X A 0~ A 1 AND DECODER BUFFERS A 2 Y AND DECODER BUFFERS MEMORY CELL SENSE AMP. CONTROL LOGIC MATRIX (1,048,576x32/ 2,097152x16) DATA OUT BUFFERS A -1 CE OE WORD Q 0 /Q 16 Q 15 /Q 31 . . .

K3P6C2000B-SC CMOS MASK ROM ABSOLUTE MAXIMUM RATINGS NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to th e conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extend ed periods may affect device reliability. Item Symbol Rating Unit Voltage on Any Pin Relative to V SS V IN -0.3 to +7.0 V Temperature Under Bias T BIAS -10 to +85 °C Storage Temperature T STG -55 to +150 °C RECOMMENDED OPERATING CONDITIONS (Voltage reference to V SS , T A =0 to 70 °C) Item Symbol Min Typ Max Unit Supply Voltage V CC 4.5 5.0 5.5 V Supply Voltage V SS 0 0 0 V DC CHARACTERISTICS NOTE : Minimum DC Voltage(V IL ) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(V IH ) is V CC +0.3V which, during transitions, may overshoot to V CC +2.0V for periods <20ns. Parameter Symbol Test Conditions Min Max Unit Operating Current ICC Cycle=5MHz, all outputs open CE = OE =V IL , V IN =0.6V to 2.4V (AC Test Condition) - 150 mA Standby Current(TTL) ISB1 CE =V IH , all outputs open - 1 mA Standby Current(CMOS) ISB2 CE =V CC , all outputs open - 50 µA Input Leakage Current I LI V IN =0 to V CC - 10 µA Output Leakage Current ILO V OUT =0 to V CC - 10 µA Input High Voltage, All Inputs V IH 2.2 V CC +0.3 V Input Low Voltage, All Inputs V IL -0.3 0.8 V Output High Voltage Level V OH I OH =-400 µA 2.4 - V Output Low Voltage Level V OL I OL =2.1mA - 0.4 V MODE SELECTION CE OE WORD Q 31 /A -1 Mode Data Power H X X X Standby High-Z Standby L H X X Operating High-Z Active L L H Output Operating Q 0 ~Q 31 :Dout Active L Input Operating Q 0 ~Q 15 : Dout Q 16 ~Q 30 : Hi-Z Active CAPACITANCE (T A =25 °C, f=1.0MHz) NOTE : Capacitance is periodically sampled and not 100% tested. Item Symbol Test Conditions Min Max Unit Output Capacitance C OUT V OUT =0V - 12 pF Input Capacitance C IN V IN =0V - 12 pF

K3P6C2000B-SC CMOS MASK ROM TEST CONDITIONS Item Value Input Pulse Levels 0.6V to 2.4V Input Rise and Fall Times 10ns Input and Output timing Levels 0.8V and 2.0V Output Loads 1 TTL Gate and C L =100pF AC CHARACTERISTICS (T A =0 °C to 70 °C, V CC =5V ±10%, unless otherwise noted.) READ CYCLE NOTE : Page Address is determined as below. Double word mode ( WORD =V IH ) ; A 0 , A 1 Word mode ( WORD =V IL ) ; A -1 , A 0 , A 1 Item Symbol K3P6C2000B-SC10 K3P6C2000B-SC12 K3P6C2000B-SC15 Unit Min Max Min Max Min Max Read Cycle Time tRC 100 120 150 ns Chip Enable Access Time t ACE 100 120 150 ns Address Access Time tAA 100 120 150 ns Page Address Access Time tPA 30 50 70 ns Output Enable Access Time tOE 30 50 70 ns Output or Chip Disable to Output High-Z tDF 20 20 30 ns Output Hold from Address Change t OH 0 0 0 ns

K3P6C2000B-SC CMOS MASK ROM TIMING DIAGRAM READ ADD CE OE D OUT A 0 ~A 19 A -1(*1) D 0 ~D 15 D 16 ~D 31(*2) PAGE READ OE ADD D OUT CE ADD A 0, A 1 A 2 ~A 19 VALID DATA VALID DATA VALID DATA VALID DATA 1 st 2 nd 3 rd tDF(*3) ADD1 ADD2 VALID DATA VALID DATA tOH tDF(*3) tRC tACE t OE tAA NOTES : *1. Word Mode only. A -1 is Least Significant Bit Address.( WORD = V IL ) *2. Double Word Mode only.( WORD = V IH ) *3. t DF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V OH or V OL level. tAA t PA A -1(*1) D 0 ~D 15 D 16 ~D 31(*2) ≈ ≈