K1S32161CC-FI70

K1S32161CC SAMSUNG | Alldatasheet

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Revision 0.0 July 2003 K1S32161CC - 1 - U t RAM Preliminary Document Title 2Mx16 bit Page Mode Uni-Transistor Random Access Memory The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the spec ifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision History

Revision No. 0.0 Remark Preliminary History Initial Draft Draft Date July 14, 2003

Revision 0.0 July 2003 K1S32161CC - 2 - U t RAM Preliminary PRODUCT FAMILY Product Family Operating Temp. Vcc Range Speed (t RC ) Power Dissipation PKG TypeStandby (I SB1 , Max.) Operating (I CC2 , Max.) K1S32161CC-I Industrial(-40~85 °C) 2.7~3.1V 70ns 100 µA 40mA 48-FBGA-6.00x8.00 2M x 16 bit Page Mode Uni-Transistor CMOS RAM GENERAL DESCRIPTION The K1S32161CC is fabricated by SAMSUNG ′s advanced CMOS technology using one transistor memory cell. The device support 4 page mode operation, Industrial temperature range and 48 ball Chip Scale Package for user flexibility of system design. The device also supports deep power down mode for low standby current.

FEATURES

• Process Technology: CMOS
• Organization: 2M x16 bit
• Power Supply Voltage: 2.7~3.1V
• Three State Outputs
• Compatible with Low Power SRAM
• Support 4 page read mode
• Package Type: 48-FBGA-6.00x8.00 PIN DESCRIPTION 1) Reserved for future use Name Function Name Function CS 1,CS2 Chip Select Inputs Vcc Power OE Output Enable Input Vss Ground WE Write Enable Input UB Upper Byte(I/O 9 ~ 16 ) A 0 ~A 20 Address Inputs LB Lower Byte(I/O 1 ~ 8 ) I/O 1 ~I/O 16 Data Inputs/Outputs NC No Connection 1) 48-FBGA: Top View(Ball Down) LB OE A0 A1 A2 CS2 I/O9 UB A3 A4 CS 1 I/O1 I/O10 I/O11 A5 A6 I/O2 I/O3 Vss I/O12 A17 A7 I/O4 Vcc Vcc I/O13 NC A16 I/O5 Vss I/O15 I/O14 A14 A15 I/O6 I/O7 I/O16 A19 A12 A13 WE I/O8 A18 A8 A9 A10 A11 A20 1 2 3 4 5 6 A B C D E F G H SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice . FUNCTIONAL BLOCK DIAGRAM Clk gen. Row select I/O 1 ~I/O 8 Data cont Data cont Data cont I/O 9 ~I/O 16 Vcc Vss Precharge circuit. Memory array I/O Circuit Column select WE OE UB CS1 LB Control Logic CS2 Row Addresses Column Addresses

Revision 0.0 July 2003 K1S32161CC - 3 - U t RAM Preliminary POWER UP SEQUENCE 1. Apply power. 2. Maintain stable power(Vcc min.=2.7V) for a minimum 200 µs with CS 1=high.or CS2=low. Min. 200 µs TIMING WAVEFORM OF POWER UP(1) ( CS 1 controlled) TIMING WAVEFORM OF POWER UP(2) (CS 2 controlled) POWER UP(2) 1. After V CC reaches V CC (Min.), wait 200 µs with CS 2 low. Then the device gets into the normal operation. ≈≈≈≈ V CC CS 1 CS 2 V CC(Min) POWER UP(1) 1. After V CC reaches V CC (Min.), wait 200 µs with CS 1 high. Then the device gets into the normal operation. Min. 200 µs V CC CS 1 CS 2 V CC(Min) ≈≈≈ Normal Operation Power Up Mode Normal Operation Power Up Mode

Revision 0.0 July 2003 K1S32161CC - 4 - U t RAM Preliminary ABSOLUTE MAXIMUM RATINGS 1) 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional oper ation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reli- ability. Item Symbol Ratings Unit Voltage on any pin relative to Vss V IN , V OUT -0.2 to V CC +0.3V V Voltage on Vcc supply relative to Vss V CC -0.2 to 3.6V V Power Dissipation P D 1.0 W Storage temperature T STG -65 to 150 °C Operating Temperature T A -40 to 85 °C FUNCTIONAL DESCRIPTION 1. X means don ′t care.(Must be low or high state) CS 1 CS2 OE WE LB UB I/O 1~8 I/O 9~16 Mode Power H X 1) X 1) X 1) X 1) X 1) High-Z High-Z Deselected Standby X 1) L X 1) X 1) X 1) X 1) High-Z High-Z Deselected Standby X 1) X 1) X 1) X 1) H H High-Z High-Z Deselected Standby L H H H L X 1) High-Z High-Z Output Disabled Active L H H H X 1) L High-Z High-Z Output Disabled Active L H L H L H Dout High-Z Lower Byte Read Active L H L H H L High-Z Dout Upper Byte Read Active L H L H L L Dout Dout Word Read Active L H X 1) L L H Din High-Z Lower Byte Write Active L H X 1) L H L High-Z Din Upper Byte Write Active L H X 1) L L L Din Din Word Write Active

Revision 0.0 July 2003 K1S32161CC - 5 - U t RAM Preliminary DC AND OPERATING CHARACTERISTICS 1. Typical values are tested at V CC =2.9V, T A =25 °C and not guaranteed. Item Symbol Test Conditions Min Typ 1) Max Unit Input leakage current ILI V IN =Vss to Vcc -1 - 1 µA Output leakage current ILO CS =V IH, ZZ =V IH , OE =V IH or WE =V IL , V IO =Vss to Vcc -1 - 1 µA Average operating current ICC1 Cycle time=1 µs, 100% duty, I IO =0mA, CS ≤0.2V, ZZ ≥Vcc-0.2V, V IN ≤0.2V or V IN ≥V CC -0.2V - - 7 mA ICC2 Cycle time=t RC +3t PC , I IO =0mA, 100% duty, CS =V IL , ZZ =V IH, V IN =V IL or V IH - 40 mA Output low voltage V OL IOL =2.1mA - - 0.4 V Output high voltage V OH IOH =-1.0mA 2.4 - - V Standby Current(CMOS) ISB1 2) CS ≥Vcc-0.2V, ZZ ≥Vcc-0.2V, Other inputs=Vss to Vcc - - 100 µA RECOMMENDED DC OPERATING CONDITIONS 1) 1. T A =-40 to 85 °C, otherwise specified. 2. Overshoot: Vcc+1.0V in case of pulse width ≤20ns. 3. Undershoot: -1.0V in case of pulse width ≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. Item Symbol Min Typ Max Unit Supply voltage Vcc 2.7 2.9 3.1 V Ground Vss 0 0 0 V Input high voltage V IH 2.2 - Vcc+0.3 2) V Input low voltage V IL -0.2 3) - 0.6 V CAPACITANCE 1) (f=1MHz, T A =25 °C) 1. Capacitance is sampled, not 100% tested. Item Symbol Test Condition Min Max Unit Input capacitance C IN V IN =0V - 8 pF Input/Output capacitance C IO V IO =0V - 10 pF PRODUCT LIST Industrial Temperature Product(-40~85 °C) Part Name Function K1S32161CC-FI70 48-FBGA, 70ns, 2.9V

Revision 0.0 July 2003 K1S32161CC - 6 - U t RAM Preliminary AC CHARACTERISTICS (Vcc=2.7~3.1V, T A =-40 to 85 °C) 1. t WP (min) =70ns for continuous write operation over 50 times. Parameter List Symbol Speed Bin Units70ns 1) Min Max Read Read Cycle Time tRC 70 - ns Address Access Time tAA - 70 ns Chip Select to Output tCO - 70 ns Output Enable to Valid Output tOE - 35 ns UB , LB Access Time tBA - 70 ns Chip Select to Low-Z Output tLZ 10 - ns UB , LB Enable to Low-Z Output tBLZ 10 - ns Output Enable to Low-Z Output tOLZ 5 - ns Chip Disable to High-Z Output tHZ 0 25 ns UB , LB Disable to High-Z Output tBHZ 0 25 ns Output Disable to High-Z Output tOHZ 0 25 ns Output Hold from Address Change tOH 5 - ns Page Cycle tPC 25 - ns Page Access Time tPA - 20 ns Write Write Cycle Time tWC 70 - ns Chip Select to End of Write tCW 60 - ns Address Set-up Time tAS 0 - ns Address Valid to End of Write tAW 60 - ns UB , LB Valid to End of Write tBW 60 - ns Write Pulse Width tWP 55 1) - ns Write Recovery Time tWR 0 - ns Write to Output High-Z tWHZ 0 25 ns Data to Write Time Overlap tDW 30 - ns Data Hold from Write Time tDH 0 - ns End Write to Output Low-Z tOW 5 - ns AC OPERATING CONDITIONS TEST CONDITIONS (Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load: C L =50pF C L 1. Including scope and jig capacitance Dout

Revision 0.0 July 2003 K1S32161CC - 7 - U t RAM Preliminary Address Data Out Previous Data Valid Data Valid TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled , CS = OE =V IL , WE= V IH , UB or/and LB =V IL ) TIMING WAVEFORM OF READ CYCLE(2) ( WE =V IH ) tAA tRC tOH (READ CYCLE) 1. tHZ and t OHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, t HZ (Max.) is less than t LZ (Min.) both for a given device and from device to device interconnection. 3. t OE (max) is met only when OE becomes enabled after t AA (max). 4. If invalid address signals shorter than min. t RC are continuously repeated for over 4us, the device needs a normal read timing(t RC ) or needs to sustain standby state for min. t RC at least once in every 4us. Data ValidHigh-Z tRC tOHtAA tBA tOE tOLZ tBLZ tLZ tOHZ tBHZ tHZ tCO Address UB , LB OE Data out TIMING WAVEFORM OF PAGE CYCLE(READ ONLY) Data Valid Data Valid Data Valid Data Valid Valid Address Valid Address Valid Address Valid Address Valid Address tPC tPA High Z A20~A2 A1~A0 DQ15~DQ0 OE tOHZtOE tCO tAA CS 1 CS 2 CS 1 CS 2

Revision 0.0 July 2003 K1S32161CC - 8 - U t RAM Preliminary TIMING WAVEFORM OF WRITE CYCLE(2) ( CS 1 Controlled) Address Data Valid UB , LB WE Data in Data out High-Z tWC tCW tAW tBW tWP tDHtDW tWRtAS CS 1 CS 2 TIMING WAVEFORM OF WRITE CYCLE(1) ( WE Controlled) Address CS 1 Data Undefined UB , LB WE Data in Data out tWC tCW tWR tAW tBW tWP tAS tDHtDW tWHZ tOW High-Z High-ZData Valid CS 2

Revision 0.0 July 2003 K1S32161CC - 9 - U t RAM Preliminary Address Data Valid UB , LB WE Data in Data out High-Z TIMING WAVEFORM OF WRITE CYCLE(4) ( UB , LB Controlled) NOTES (WRITE CYCLE) 1. A wri te occurs during the overlap(t WP ) of low CS 1 and low WE . A write begins when CS 1 goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest tran- sition when CS 1 goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS 1 going low to the end of write. 3. t AS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS 1 or WE going high. tWC tCW tBW tWP tDHtDW tWR tAW tAS CS 1 CS 2 TIMING WAVEFORM OF WRITE CYCLE(3) (CS 2 Controlled) Address Data Valid UB , LB WE Data in Data out High-Z tWC tCW tAW tBW tWP(1) tDHtDW tWR tAS CS 1 CS 2

Revision 0.0 July 2003 K1S32161CC - 10 - U t RAM Preliminary C 1 /2 PACKAGE DIMENSION 6 5 4 3 2 1 A B C D E F G H C B/2 B C 1 B C Bottom ViewTop View D E C Side View 0 .5 5 /T y p . 0 .3 5 /T y p . A Y Detail A Min Typ Max A - 0.75 - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.40 0.45 0.50 E - 0.90 1.00 E1 - 0.55 - E2 0.30 0.35 0.40 Y - - 0.08 #A1 Notes. 1. Bump counts: 48(8 row x 6 column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are ±0.050 unless specified beside figures. 4. Typ : Typical 5. Y is coplanarity: 0.08(Max) Unit: millimeters 48 BALL FINE PITCH BGA(0.75mm ball pitch)