K1B6416B6C SAMSUNG | Alldatasheet

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Revision 1.0 January 2005 K1B6416B6C - 1 - UtRAM Document Title 4Mx16 bit Synchronous Burst Uni-Transistor Random Access Memory The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the spe cifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

Revision History

Revision No. 0.0 0.1 0.2 0.3 0.4 1.0 Remark Advance Advance Advance Preliminary Preliminary Final History Initial Draft - Design target Revised - Deleted Deep Power Down Mode support Revised - Changed product code from K1B6416B7C into K1B6416B6C Revised - Filled out Package type(54ball FBGA 6.0mm x 8.0mm) - Changed Hi-Z parameters(tCHZ, tOHZ, tBHZ, tWZ) from Max.7ns into Max.12ns and changed tHZ from Max.10ns into Max.12ns - Updated "Fig.17 TIMING WAVEFORM OF WRITE CYCLE(1)" in page 23 - Added comment on standby current(I SB1) measure condition as "Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measured after 60ms from the time when standby mode is set up." - Added comment on restriction of the transition between Asynchro- nous Write operation and Fully Synchronous bus operation(Page 10,11) - Filled out ISB1 value, ISBP value and ICC2 value in Table 17(DC AND OPERATING CHARACTERISTICS) - Added Synchronous Operating Current(I CC3, Max.40mA) - Added tCSHP(A)(CS high pulse width) parameter as Min.10ns in the ASYNCHRONOUS AC CHARACTERISTICS Revised - Changed ISB1(< 40°C) and ISBP(3/4 block, < 40°C) from 100µA into 120µA - Changed ISBP(1/2 block and 1/4 block, < 40°C) from 95µA into 115µA Finalized Draft Date March 11, 2004 April 19, 2004 May 10, 2004 September 1, 2004 October 12, 2004 January 20, 2005

Revision 1.0 January 2005 K1B6416B6C - 2 - UtRAM 4M x 16 bit Synchronous Burst Uni-Transistor CMOS RAM

FEATURES

  • Process Technology: CMOS
  • Organization: 4M x16 bit
  • Power Supply Voltage: 1.7~2.0V
  • Three State Outputs
  • Supports MRS (Mode Register Set)
  • MRS control - MRS Pin Control
  • Supports Power Saving modes - Partial Array Refresh mode Internal TCSR
  • Supports Driver Strength Optimization for system environment power saving.
  • Supports Asynchronous 4-Page Read and Asynchronous Write Operation
  • Supports Synchronous Burst Read and Asynchronous Write Operation(Address Latch Type and Low ADV Type)
  • Supports Synchronous Burst Read and Synchronous Burst Write Operation
  • Synchronous Burst(Read/Write) Operation - Supports 4 word / 8 word / 16 word and Full Page(256 word) burst - Supports Linear Burst type & Interleave Burst type - Latency support : Latency 5 @ 66MHz(tCD 10ns) Latency 4 @ 54MHz(tCD 10ns) - Supports Burst Read Suspend in No Clock toggling - Supports Burst Write Data Masking by /UB & /LB pin control - Supports WAIT pin function for indicating data availability.
  • Max. Burst Clock Frequency : 66MHz
  • Package Type : 54 ball FBGA 6.0mm x 8.0mm SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. GENERAL DESCRIPTION The world is moving into the mobile multi-media era and there- fore the mobile handsets need much bigger memory capacity to handle the multi-media data. SAMSUNG’s UtRAM products are designed to meet all the request from the various customers who want to cope with the fast growing mobile market. UtRAM is the perfect solution for the mobile market with its low cost, high density and high performance feature. K1B6416B6C is fabricated by SAMSUNG ′s advanced CMOS technology using one transistor memory cell. The device supports the traditi onal SRAM like asynchronous bus operation(asynchronous page read and asynchronous write), the NOR flash like sy nchronous bus operation(synchro- nous burst read and asynchronous write) and the fully synchro- nous bus operation(synchronous burst read and synchronous burst write). These three bus operation modes are defined through the mode register setting. The device also supports the s pecial features for the standby power saving. Those are the Partial Array Refresh(PAR) mode and internal Temperature Compensated Self Refresh(TCSR) mode. The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings. Through this driver strength optim ization, the device can mini- mize the noise generated on the data bus during read operation.

Table 1. PRODUCT FAMILY

Table 2. PIN DESCRIPTION

Revision 1.0 January 2005 K1B6416B6C - 4 - UtRAM

CONTENTS

Features and General Description Pin Description Power Up Sequence Functional Description Mode Register Setting Operation Mode Register Setting Timing Asynchronous Operation Asynchronous 4 Page Read Operation Asynchronous Write Operation Asynchronous Write Operation in Synchronous Mode Synchronous Burst Operation Synchronous Burst Read Operation Synchronous Burst Write Operation Synchronous Burst Operation Terminology Clock Latency Count Burst Length Burst Stop WAIT Control Burst Type Low Power Features Internal TCSR Driver Strength Optimization Partial Array Refresh(PAR) Mode Product List Absolute Maximum Ratings Recommended DC Operating Conditions Capacitance DC and Operating Characteristics Asynchronous AC Characteristics Asynchronous Timing Waveforms Synchronous AC Characteristics Synchronous Timing Waveforms Transition Timing Waveforms Package Dimension Page

Table 3. Asynchronous 4 Page Read & Asynchronous Write Mode Truth Table Table 4. Synchronous Burst Read & Asynchronous Write Mode Truth Table Table 5. Synchronous Burst Read & Synchronous Burst Write Mode Truth Table Table 6. Mode Register Setting according to Field of Function Table 7. Mode Register Set Table 8. MRS AC Characteristics Table 9. Latency Count Support Table 10. Number of Clocks for 1st Data Table 11. Burst Sequence Table 12. PAR Mode Characteristics Table 13. Product List Table 14. Absolute Maximum Ratings Table 15. Recommended DC Operating Conditions Table 16. Capacitance Table 17. DC and Operating Characteristics Table 18. Asynchronous AC Characteristics Table 19. Asynchronous Read AC Characteristics Table 20. Asynchronous Page Read AC Characteristics Table 21. Asynchronous Write AC Characteristics(WE Table 22. Asynchronous Write AC Characteristics(UB & LB Controlled) Table 23. Asynch. Write in Synch. Mode AC Characteristics(Address Latch Type, WE Controlled) Table 24. Asynch. Write in Synch. Mode AC Characteristics(Address Latch Type, UB & LB Controlled) Table 25. Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type, WE Controlled) Table 26. Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type, UB & LB Controlled) Table 27. Asynch. Write in Synch. Mode AC Characteristics(Low ADV Type Multiple Write, WE Controlled) Table 28. Synchronous AC Characteristics Table 29. Burst Operation AC Characteristics Table 30. Burst Read AC Characteristics(CS Table 31. Burst Read AC Characteristics(CS Low Holding Consecutive Burst) Table 32. Burst Read AC Characteristics(Last Data Sustaining) Table 33. Burst Write AC Characteristics(CS Toggling Consecutive Burst) Table 34. Burst Write AC Characteristics(CS Low Holding Consecutive Burst) Table 35. Burst Read Stop AC Characteristics Table 36. Burst Write Stop AC Characteristics Table 37. Burst Read Suspend AC Characteristics Table 38. Burst Read to Asynch. Write(Address Latch Type) AC Characteristics Table 39. Burst Read to Asynch. Write(Low ADV Table 40. Asynch. Write(Address Latch Type) to Burst Read AC Characteristics Table 41. Asynch. Write(Low ADV Type) to Burst Read AC Characteristics Table 42. Burst Read to Burst Write AC Characteristics Table 43. Burst Write to Burst Read AC Characteristics

Revision 1.0 January 2005 K1B6416B6C - 7 - UtRAM Fig.2 FUNCTIONAL BLOCK DIAGRAM CLK generator Row select I/O0~I/O7 Data controller I/O8~I/O15 Vcc Vss Precharge circuit. Memory array I/O Circuit Column select OE CS WE ADV UB Control Logic MRS Row Addresses Column Addresses LB CLK WAIT Data controller Data controller

Revision 1.0 January 2005 K1B6416B6C - 8 - UtRAM POWER UP SEQUENCE After applying VCC upto minimum operating voltage(1.7V), drive CS High first and then drive MRS High. Then the device gets into the Power Up mode. Wait for minimum 200µs to get into the normal operation mode. During the Power Up mode, the standby current can not be guaranteed. To get the stable standby current level, at least one cycle of active operation should be implemented regardless of wait time duration. To get the appropriate device operation, be sure to keep the following power up sequence. 1. Apply power. 2. Maintain stable power(Vcc min.=1.7V) for a minimum 200µs with CS and MRS high. 200µs VCC Fig.3 POWER UP TIMING VCC(Min) Min. 200µs MRS CS Normal Operation Min. 0ns Power Up Mode (Note) 1. After VCC reaches VCC(Min.), wait 200µs with CS and MRS high. Then the device gets into the normal operation. Min. 0ns Fig.4 STANDBY MODE STATE MACHINES Default mode after power up is Asynchronous mode(4 Page Read and Asynchronous Write). But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up. For entry to PAR mode, drive MRS pin into VIL for over 0.5µs(suspend period) during standby mode after MRS setting has been completed(A4=1, A3=0). If MRS pin is driven into VIH during PAR mode, the device gets back to the standby mode without wake up sequence. CS=VIH CS=VIL, UB or LB=VIL MRS=VIH Power On Initial State (Wait 200µs) Active Standby Mode CS=VIH PAR ModeMRS Setting CS=UB=LB=VIL, WE=VIL, MRS=VILMRS=VIH MRS Setting CS=VIL, WE=VIL, MRS=VIL MRS=VIH MRS=VIL

Table 4. SYNCHRONOUS BURST READ & ASYNCHRONOUS WRITE MODE(A15/A14=0/1)

  1. X must be low or high state.
  2. X means "Don’t care"(can be low, high or toggling).
  3. /WAIT is device output signal so does not have any affect to the mode definition. Please refer to each timing diagram for /WAIT pin function.

Table 3. ASYNCHRONOUS 4 PAGE READ & ASYNCHRONOUS WRITE MODE(A15/A14=0/0)

  1. X must be low or high state.
  2. In asynchronous mode, Clock and ADV are ignored.
  3. /WAIT pin is High-Z in Asynchronous mode.

Table 5. SYNCHRONOUS BURST READ & SYNCHRONOUS BURST WRITE MODE(A15/A14=1/0)

  1. X must be low or high state.
  2. X means "Don’t care"(can be low, high or toggling).
  3. /WAIT is device output signal so does not have any affect to the mode definition. Please refer to each timing diagram for /WAIT pin function.
  4. The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then implement at least one dummy

write cycle before change mode into synchronous burst read and synchronous burst write mode.

  1. The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the transition from Synchronous

burst write operation to Asynchronous write operation is prohibited.

chronous Burst Write mode, Standby mode and Partial Array Refresh(PAR) mode. Burst Length, Burst Type, Wait Polarity and Latency Count at Synchronous Burst Read/Write mode. tions. The default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes. and Driver Strength uses A16~A17. Refer to the Table below for detailed Mode Register Setting. A18~A21 addresses are "Don’t care" in Mode Register Setting. NOTE : The address bits other than those listed in the table above are reserved. For example, Burst Length address bits(A7:A6:A5) have 4 sets of reserved bits like 0:0:0, 0:0:1, 1:0:1 and 1:1:0. these default modes are written in blue-bold in the table above. But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up. A12 is a reserved bit for future use. A12 must be set as "0". Not all the mode settings are tested. Per the mode settings to be tested, please contact Samsung Product Planning team. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns. ment at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. transition from Synchronous burst write operation to Asynchronous write operation is prohibited.

0 Low Enable 0 Must 00 0 3 0 Linear 010 4 w o r d

1 High Enable 1 - 0 0 1 4 1 Interleave 0 1 1 8 word

11 PAR Disable 1 Top Array 0 1 3/4 Array

execute Partial Array Refresh mode. input) is not issued within 0.5µs, then the device might get into the PAR mode. Table 8. MRS AC CHARACTERISTICS (VCC=1.7~2.0V, TA=-40 to 85°C, Maximum Main Clock Frequency=66MHz)

Revision 1.0 January 2005 K1B6416B6C - 13 - UtRAM ASYNCHRONOUS OPERATION Asynchronous 4 Page Read Operation Asynchronous normal read operation starts when CS, OE and UB or LB are driven to VIL under the valid address without tog- gling page addresses(A0, A1). If the page addresses(A0, A1) are toggled under the other valid address, the first data will be out with the normal read cycle time(tRC) and the second, the third and the fourth data will be out with the page cycle time(tPC). (MRS and WE should be driven to VIH during the asynchronous (page) read operation) Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation. Asynchronous Write Operation Asynchronous write operation starts when CS, WE and UB or LB are driven to VIL under the valid address.(MRS and OE should be driven to VIH during the asynchronous write opera- tion.) Clock, ADV, WAIT signals are ignored during the asyn- chronous (page) read operation. Asynchronous Write Operation in Syn- chronous Mode A write operation starts when CS, WE and UB or LB are driven to VIL under the valid address. Clock input does not have any affect to the write operation(MRS and OE should be driven to VIH during write operation. ADV can be either toggling for address latch or held in VIL). Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation. SYNCHRONOUS BURST OPERATION Burst mode operations enable the system to get high perfor- mance read and write operation. The address to be accessed is latched on the rising edge of clock or ADV (whichever occurs first). CS should be setup before the address latch. During this first clock rising edge, WE indicates whether the operation is going to be a Read(WE High) or a Write(WE Low). For the optimized Burst Mode to each system, the system should determine how many clock cycles are required for the first data of each burst access(Latency Count), how many words the device outputs at an access(Burst Length) and which type of burst operation(Burst Type : Linear or Interleave) is needed. The Wait Polarity should also be determined.(See Table "Mode Register Set") Synchronous Burst Read Operation The Synchronous Burst Read command is implemented when the clock rising is detected during the ADV low pulse. ADV and CS should be set up before the clock rising. During Read com- mand, WE should be held in VIH. The multiple clock risings(dur- ing low ADV period) are allowed but the burst operation starts from the first clock rising. The first data will be out with Latency count and tCD. Synchronous Burst Write Operation The Synchronous Burst Write command is implemented when the clock rising is detected during the ADV and WE low pulse. ADV, WE and CS should be set up before the clock rising. The multiple clock risings(during low ADV period) are allowed but the burst operation starts from the first clock rising. The first data will be written in the Latency clock with tDS. A21~A2 A1~A0 CS UB, LB OE Data out High-Z High-Z High-Z Address CS UB, LB WE Data in Data out Fig.6 ASYNCHRONOUS 4-PAGE READ Fig.7 ASYNCHRONOUS WRITE CLK ADV Addr. UB, LB OE Data out CS WAIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Fig.8 SYNCHRONOUS BURST READ(Latency 5, BL 4, WP : Low Enable) Fig.9 SYNCHRONOUS BURST WRITE(Latency 5, BL 4, WP : Low Enable) CLK ADV Addr. UB, LB WE Data in CS WAIT 0 1 2 3 4 5 6 7 8 9 10 11 12 13

write operation is synchronized to the rising edge of the clock. The clock transitions must swing between VIL and VIH. be available on its data pins. This value depends on the input clock frequency. The supported Latency Count is as follows. Table 9. Latency Count support : 3, 4, 5 NOTE : The first data will always keep the Latency. From the second data, some period of wait time might be caused by WAIT pin. burst read or write. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns. The first data will be out with the set Latency + tCD. From the second data, the data will be out with tCD from each clock. burst operation can be issued only after the previous burst operation is finished. which accounts for big portion in usage for the mobile handset application environment.

Revision 1.0 January 2005 K1B6416B6C - 15 - UtRAM SYNCHRONOUS BURST OPERATION TERMINOLOGY WAIT Control(WAIT) The WAIT signal is the device’s output signal which indicates to the host system when the device’s data-out or data-in is valid. To be compatible with the Flash interfaces of various microprocessor types, the WAIT polarity(WP) can be configured. The polarity can be programmed to be either low enable or high enable. For the timing of WAIT signal, the WAIT signal should be set active one clock prior to the data regardless of Read or Write cycle. Burst Type The device supports Linear type burst sequence and Interleave type burst sequence. Linear type burst sequentially increments the burst address from the starting address. The detailed Linear and Interleave type burst address sequence is shown in burst sequence table in next page. 123456789 1 0 1 1 1 2 1 3 ADV Read CLK DQ0 DQ1 DQ2 Fig.11 WAIT Control and Read/Write Latency Control(LATENCY : 5, Burst Length : 4, WP : Low Enable) Write D0 D1 D2 DQ3 Data out Data in CS Latency 5 Latency 5 High-ZWAIT High-ZWAIT

  1. Wrap : Burst Address wraps within word boundary and ends after fulfilled the burst length.
  2. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns.

to be refreshed and so the previously stored data will get lost. array as long as MRS pin is not driven to low for over 0.5µs. ation. The device supports full drive, 1/2 drive and 1/4 drive. more refresh cycles, which lead to standby current increase. below 40°C in the phone standby mode. Table 12. PAR MODE CHARACTERISTIC

  1. Only the data in the refreshed block are valid
  2. PAR Array can be selected through Mode Register Set(See Page 11)
  3. Standby mode is supposed to be set up after at least one active operation.after power up.

ISB1 is measured after 60ms from the time when standby mode is set up.

Table 14. ABSOLUTE MAXIMUM RATINGS1)

  1. Stresses greater than those listed under "Absolute Maximum Ra tings" may cause permanent damage to the device. Functional ope ration should be

Table 15. RECOMMENDED DC OPERATING CONDITIONS1)

  1. TA=-40 to 85°C, otherwise specified.
  2. Overshoot: VCC+1.0V in case of pulse width ≤20ns.
  3. Undershoot: -1.0V in case of pulse width ≤20ns.
  4. Overshoot and undershoot are sampled, not 100% tested.

Table 16. CAPACITANCE1)(f=1MHz, TA=25°C)

  1. Capacitance is sampled, not 100% tested.
  2. Full Array Partial Refresh Current(ISBP) is same as Standby Current(ISB1).
  3. Standby mode is supposed to be set up after at least one active operation.after power up.

ISB1 is measured after 60ms from the time when standby mode is set up.

Table 18. ASYNCHRONOUS AC CHARACTERISTICS (VCC=1.7~2.0V, TA=-40 to 85°C)

  1. tWP(min)=70ns for continuous write operation over 50 times.

Figure 14. AC Output Load Circuit Vtt=0.5 x VCC

  1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
  2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
  3. In asynchronous read cycle, Clock, ADV and WAIT signals are ignored.
  1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels.
  2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
  3. In asynchronous 4 page read cycle, Clock, ADV and WAIT signals are ignored.

Table 21. ASYNCHRONOUS WRITE AC CHARACTERISTICS(WE Controlled)

  1. tWP(min)=70ns for continuous write operation over 50 times.
  2. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.

  1. tCW is measured from the CS going low to the end of write.
  2. tAS is measured from the address valid to the beginning of write.
  3. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
  4. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored.
  5. Condition for continuous write operation over 50 times : tWP(min)=70ns
  1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.

  1. tCW is measured from the CS going low to the end of write.
  2. tAS is measured from the address valid to the beginning of write.
  3. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
  4. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored.
  5. tWP(min)=70ns for continuous write operation over 50 times.
  1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.

  1. tAW is measured from the address valid to the end of write. In this address latch type write timing, t WC is same as tAW.
  2. tCW is measured from the CS going low to the end of write.
  3. tBW is measured from the UB and LB going low to the end of write.
  4. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
  5. tWP(min)=70ns for continuous write operation over 50 times.
  1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

CS goes or and WE goes high. The tWP is measured from the beginning of write to the end of write.

  1. tAW is measured from the address valid to the end of write. In this address latch type write timing, t WC is same as tAW.
  2. tCW is measured from the CS going low to the end of write.
  3. tBW is measured from the UB and LB going low to the end of write.
  4. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
  5. tWP(min)=70ns for continuous write operation over 50 times.
  1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.

  1. tCW is measured from the CS going low to the end of write.
  2. tAS is measured from the address valid to the beginning of write.
  3. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
  4. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
  5. tWP(min)=70ns for continuous write operation over 50 times.
  1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.

  1. tCW is measured from the CS going low to the end of write.
  2. tAS is measured from the address valid to the beginning of write.
  3. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
  4. Clock input does not have any affect to the write operation if the parameter tWLRL is met.
  5. tWP(min)=70ns for continuous write operation over 50 times.
  1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB

when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write.

  1. tCW is measured from the CS going low to the end of write.
  2. tAS is measured from the address valid to the beginning of write.
  3. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high.
  4. Clock input does not have any affect to the asynchronous multiple write operation if t WHP is shorter than (Read Latency - 1) clock
  5. tWP(min)=70ns for continuous write operation over 50 times.
  6. tWP(min)=70ns for continuous write operation over 50 times.

Table 28. SYNCHRONOUS AC CHARACTERISTICS (VCC=1.7~2.0V, TA=-40 to 85°C, Maximum Main Clock Fre- Figure 24. AC Output Load Circuit

  1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
  2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
  4. Burst Cycle Time(tBC) should not be over 2.5µs.

Table 30. BURST READ AC CHARACTERISTICS(CS Toggling Consecutive Burst)

  1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
  2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
  4. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address.
  5. Burst Cycle Time(tBC) should not be over 2.5µs.
  1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
  3. Burst Cycle Time(tBC) should not be over 2.5µs.
  1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
  2. Multiple clock risings are allowed during low ADV

period. The burst operation starts from the first clock rising.

  1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  2. D2 is masked by UB and LB.
  3. Burst Cycle Time(tBC) should not be over 2.5µs.
  1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
  2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
  3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  4. D2 is masked by UB and LB.
  5. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address.
  6. Burst Cycle Time(tBC) should not be over 2.5µs.
  1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBSADV
  2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
  4. The burst stop operation should not be repeated for over 2.5µs.
  1. The new burst operation can be issued only after the previous burst operation is finished.
  2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
  4. The burst stop operation should not be repeated for over 2.5µs.
  1. If clock input is halted during burst read operation, the data out will be suspended. During the burst read suspend period, OE high

drives data out to high-Z. If clock input is resumed, the suspended data will be out first.

  1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  2. During suspend period, OE high drives DQ to High-Z and OE low drives DQ to Low-Z.

If OE stays low during suspend period, the previous data will be sustained.

  1. Burst Cycle Time(tBC) should not be over 2.5µs.
  1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
  2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
  4. Burst Cycle Time(tBC) should not be over 2.5µs.
  5. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation.

  1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
  2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
  4. Burst Cycle Time(tBC) should not be over 2.5µs.
  5. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation. Table 39. BURST READ to ASYNCH. WRITE(Low ADV Type) AC CHARACTERISTICS

  1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
  2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
  4. Burst Cycle Time(tBC) should not be over 2.5µs.
  5. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation.

  1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
  2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS
  3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
  4. Burst Cycle Time(tBC) should not be over 2.5µs.
  5. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock

in write timing is just a reference to WE low going for proper write operation.

  1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
  2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
  4. Burst Cycle Time(tBC) should not be over 2.5µs.
  1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV
  2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge)
  3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising.
  4. Burst Cycle Time(tBC) should not be over 2.5µs.

Revision 1.0 January 2005 K1B6416B6C - 46 - UtRAM C1/2 PACKAGE DIMENSION 65 4 3 2 1 A B C D E F G H C B/2 B B C Bottom ViewTop View D E C Side View 0.55/Typ. 0.35/Typ. A Y Detail A Min Typ Max A - 0.75 - B 5.90 6.00 6.10 B1 - 3.75 - C 7.90 8.00 8.10 C1 - 5.25 - D 0.40 0.45 0.50 E - 0.90 1.00 E1 - 0.55 - E2 0.30 0.35 0.40 Y- - 0 . 1 0 #A1 Notes. 1. Bump counts: 54(9 row x 6 column) 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) 3. All tolerence are ±0.050 unless specified beside figures. 4. Typ : Typical 5. Y is coplanarity: 0.10(Max) Unit: millimeters 54 BALL FINE PITCH BGA(0.75mm ball pitch) J