IPTG007N06NM5 INFINEON | Alldatasheet
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OptiMOS™ 5 Power-Transistor, 60 V PG-HSOG-8-1 Features ra + N-channel * Superior thermal resistance 4 + 100% avalanche tested . + Pb-free lead plating; ROHS compliant + Halogen-free according to IEC61249-2-21 . Y Product validation Fully qualified according to JEDEC for Industrial Applications Table 1 Key Performance Parameters ne joe fet fr @ RoHS IPTGOO7NO6NMS5 PG-HSOG-8-1 oornooen =| ld Final Data Sheet 1 Rev. 2.1, 2021-04-22
OptiMOS™ 5 Power-Transistor, 60 V Cinfi neon IPTGOO7NO6NM5 Table of Contents Final Data Sheet 2 Rev. 2.1, 2021-04-22
OptiMOS™ 5 Power-Transistor, 60 V Cin ineon IPTGOO7NO6NM5
1 Maximum ratings
at Ta=25 °C, unless otherwise specified Table 2__ Maximum ratings Paramet ymeot [—taues Note / Test Condit ‘arameter [Min. | lote est ondition Typ. Max. |
454 Ves=10 V, To=25 °C
. A 349 Vos=10 V, Tc=100 °C 4) » Continuous drain current Io 303 «A Ves=6 V, Tc=100 °C
53 Voes=10 V, Ta=25°C,Rrisa=40°C/W”
Pulsed drain current? lioowe (- - 1816 Ta=25 °C Avalanche energy, single pulse® les |e |e 1100 Ip=150 A, Res=25 Q cin ati 375 Tc=25 °C Operating and storage temperature ite [ss | is fo | La caatic category; DIN IEC 68-1:
2 Thermal characteristics
Table 3 Thermal characteristics Paramet mea [ae Note / Test Condit arameter ote / Test Condition Thermal resistance, junction - case [Rec |- ——'fo.2 [oa fcr - Thermal resistance, junction - ambient, ° 6 om? cooling area Row Fao ow. Thermal resistance, junction - ambient, ey minimal footprint” Fon Fee fo *) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature as specified. For other case temperatures please refer to Diagram 2, De-rating will be required based on the actual environmental conditions. 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm? (one layer, 70 ym thick) copper area for drain connection. PCB is vertical in still air. 3) See Diagram 3 for more detailed information ” See Diagram 13 for more detailed information Final Data Sheet 3 Rev. 2.1, 2021-04-22
OptiMOS™ 5 Power-Transistor, 60 V Cin Ineon IPTGOO7NOGNM5 3_ Electrical characteristics at Tj=25 °C, unless otherwise specified Table 4 Static characteristics Paramet symbol Note / Test Condit ‘arameter yymbol [Min. | lote est Condition Typ. [Max.__ Drain-source breakdown voltage [Venoss 60 |- |- |v | Ves=0 V, lb=1 mA Gate threshold voltage Vos=Ves, o=280 HA Zero gate voltage drain current lees | oo to0 yes85 vr ay Mi pat3s sc Gate-source leakage current licss [= ——«|10—s[t00. [na Voes=20 V, Vos=0 V Drain-source on-state resistance roam oe br Vere eyee A Transconductance lo. [reo [320 |- = |s__ | [Vos|22|/o|Ros(onymax, Ib=100 A Table 5 Dynamic characteristics Paramet yma [taut Note / Test Condit ‘arameter [Min. | ote est Condition Typ. Max. | Input capacitance” [Css |-__ [46000 |21000 Ves=0 V, Vos=30 V, f=1 MHz Output capacitance” [Cos [= __ [3100 [4000 Ves=0 V, Vos=30 V, 1 MHz Reverse transfer capacitance” [Cas > [200 [350 [pF Ves=0 V, Vos=30 V, f1 MHz ee ot 1. ext 1. ee x1, Table 6 Gate charge characteristics” Paramet symbst a a Note / Test Conditi ‘arameter [Min | lote / Test Condition Typ. [Max Gate to source charge [as |- ——|e7_—|- [nC _ | Vo0=80 V, fo=100 A, Vos=0 to 10 V Gate charge at threshold [Quy > «4 (- |r| Vo0=80V, f0=100 A, Vos=0 to 10 V Gate to drain charge” [Qe (85 [53 nC __| Vo0=30V, fo=100 A, Vos=0 to 10 V Switching charge [Qw |- «(87 |- [nC _ | Voo=30 V, fo=100 A, Vos=0 to 10 V Gate charge total” la, se —— 209 [261 [nc _ | Voo=30V, fo=100 A, Vos=0 to 10 V Gate plateau voltage [Von | (4.2 |__| Voo=80 V, f= 100 A, Vos=0 to 10 V ») Defined by design. Not subject to production test. 2) See "Gate charge waveforms” for parameter definition Final Data Sheet 4 Rev. 2.1, 2021-04-22
OptiMOS™ 5 Power-Transistor, 60 V ¢ In fi neon IPTGOO7NOGNMS Table 7 Reverse diode Paramet symbol Note / Test Condit ‘arameter yymbol lote est Condition [min [Typ. [Max._| Diode continuous forward current ls (- |- (316 [a | Tc=25 °C Diode pulse current lisome [- |e 1816 Tc=25 °C Diode forward voltage [vo |= —(fo.87 [4 |V__ | Ves=0 V, Ie=150 A, Ti=25 °C Reverse recovery time” lt —|-—(|87_—*([474 [ns | Va=30 V, Ir=100 A, die/dt=100 A/us Reverse recovery charge") la se sta s- SS [nc Vp=30 V, Ir=100 A, die/dt=100 A/us ” Defined by design. Not subject to production test. Final Data Sheet 5 Rev. 2.1, 2021-04-22
OptiMOS™ 5 Power-Transistor, 60 V Cin fi neon IPTGOO7NO6NM5
4 Electrical characteristics diagrams
a wot | | [| [ tT Tf a A SS a a ee ee wo 300 r a A a A es wo. |[N | | 7 7 a (tT | AT fT fT tf a S\\N Zoo | | Ii tt tot ig E+ AE é of | Ne) pe eee wo | | | IAT ft 200 fp ft | | TN | fT] a OO es a GO GG A 100 a Lt ft | fT FAT fT soo} X a a a a A EE 0 25 50 75 100 125 150 175 200 i) 25 50 75 100 125 150 175 200 Tc [°C] Te [°C] NO) es SS Se SS Se SS SSS 10! Se COCCI []--- 0.02 con ot CTI ASTIN tI []-+++++ 0.05 | a yo LH NN 04
7 STN Sarit eset memeiit epee aaa
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2 SESS Ae 18 i LIM eer I UT
2 TAA To NARS QE eae
_— en eel SSCA | et eT vo LUT NUNIT eS =e | a A we LCE} gs ETI EIT TEV 10° 10° 10° 10? 10° 10+ 10° 10? 107 10° Vos [V] t [s] Final Data Sheet 6 Rev. 2.1, 2021-04-22
OptiMOS™ 5 Power-Transistor, 60 V Cin fi neon IPTGOO7NO6NM5 2000 ¢ 247 TT Cee EEE Eee eee 1750 /; 0 S00 iH) 2 CEE CHE Eee eee Il/ 20) Soo 1500 / GARE Eee eee iV 7 S000 08 | wee ECE
1250 We ne S000) Oe
_ HH oT HTT 2 Soe de E s000 WAT 2 Cee ry Ii / 2 CEE eee eee pew WA BARGE 750+ @ COCre eee Wi oe GEEEEC COC Ae
500 Geer ree oo
| (0a eee COC hoy / Te TTT | oe CEE EEE eee
250 ALL 4 EEE eee
“I oo SOECC ECE rE eee eee 0 1 2 3 4 5 0 200 400 600 800 1000 Vos [V] ofA] “me Be |) “ooo EERE Cee eee
1750 EEE eee
2 CECE EC eee
2000 See Se
1500 | EEE eee / EERE / te HOE Eee 2 Se _ // BGS esse E s000 CN so 2 / Loe y Se
760 I 2 Oo
/ oa CECE EEE eee
250 Y) 4 EEE eee
/ EERE EEC eer eee ° Ly oo SOECE EC ECE rE eee ee 0 1 2 3 4 5 6 7 0 2 4 6 8 10 Ves [V] Ves [V] TEI Wa), Vea Res parameter T Final Data Sheet 7 Rev. 2.1, 2021-04-22
OptiMOS™ 5 Power-Transistor, 60 V Cin fi neon IPTGOO7NO6NM5 2.0 3.5 COO q COCCCECEPeeeeeeee eo HUTTE COCO ae petanel i LLNS 3.0 < | COCCCECEPeeeee Co COPE SSENE TL
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2 PTT eee) |. 20 NON BC = HUTTE NNT E Le] 1s HHT th 2B CCP N § Cee CE ee € LETT 1.0 POPPE EET oe EECEEEEECCCCCCC ee Toe | OT BERR RRRRRRRR ESR RRRRRRRERREE ~ TET COCCCeCEPEeeee ee oo LELEEEEEPE eee] | yg FEL -80 -40 0 0. rer 120 160 200 -80 -40 0 oO. rer 120 160 200 See | ° CePrr rrr errr eer eee eee eee) ippecpmiiiniiiitimnn CEPT [}--- 175°C PoP eee CEPT [Jes 175°C, max | | TTT TTT | CTT POO Naor) | LETTE TTT wo SAUTE Ps) LEE ees ee ee ee eee ee ee eee Cc CEPT TT TST eee _ EE Oe eee oe = LETT TT AS js LPP aA eT | 9° ee * tH fee TNO}. ATT a ee ee eee ON Ee Bs 2 CEPT TTT TT TAT LEP a TT CUT TNE ETT CEE) Crss* ve CUE). LPT Final Data Sheet 8 Rev. 2.1, 2021-04-22
OptiMOS™ 5 Power-Transistor, 60 V ¢ In fi neon IPTGOO7NO6NM5 Diagram 13: Avalanche characteristics Diagram 14: Typ. gate charge 10° rr eg 10 ooo ——=—==—— =e esl rr TTL LEE ELL) —— = ?2MT 7 Te a | —-30V FCLCEECEELLE Pe a a res 48V Fee eee ee AA) LT TT TP TTT S| COCR PETITE) GEER PN CTT TTT rr rT tr rt tt yer tT ON CNMI EEE
2 SSS HERRERA
E+} SS NS 5 £4 SE SSS S25 “cd 2 Z PT NENT S S FCLOELCLEEL EL CCE = ETA PNT ote HH = COCO 2 | LTA TTA | nS Fe 7 2 NQ n ee ee Ae IN | LTT TT Tyr rrr rr rrr 40°§ Et [TTT TWIT ttt T ttre tet ee tet te Ser EEE SS EB 0 a ott ZT TTT Tt LT TT TP TTT [TTAT TTT TTT Tr ryt rt tt) Coo Coon Coon By 400 0000000000000008858 CITT re eT 40° (yp 40 10° 10° 10 10° 0 40 80 120 160 200 240 tav [Hs] Qgate [NC] Ins=f(tav); Res=25 Q; parameter: Tjstat Ves=f(Qoate), lo=100 A pulsed, T=25 °C; parameter: Voo Diagram 15: Drain-source breakdown voltage Diagram Gate charge waveforms 85 eee ER ee ECE CCE
64 GEOEC EEE Ves
ECE ECC eee Q,
63 GEOECEEe
62 GEEEC EEE
_ oy a S a er
8 CYT TTT rr yyy yr ee
& 2 ey e+ eee COCO CCA oe 4 a
69 CECT
63 COOOZEECEE Eee Q Q @
67 COOP eee Qou
80 40 0 40. 80 120 160 200 TLC) Venoss TT A — Final Data Sheet 9 Rev. 2.1, 2021-04-22
or. OptiMOS™ 5 Power-Transistor, 60 V Cinfi neon IPTGOO7NO6NM5
5 Package Outlines
D a a ne rT 4 f l =| = | en | HEA 7 UME: [e] b + a Cc Ly [pensions | ne] [a 2.20 2.40 [ar [0.00 [0.10 _} [0.60 0.80 [ef 0.40 0.60] [970 0.10 [or [9.36 9.56 [e580 1.90 [er [as [8.75] [ez | 87 7.0] a [et 0 a a (e290 3.10] Figure 1 Outline PG-HSOG-8-1, dimensions in mm Final Data Sheet 10 Rev. 2.1, 2021-04-22
—_— I fi OptiMOS™ 5 Power-Transistor, 60 V nrineon IPTGOO7NOGNM5
Revision History
Revision: 2021-04-22, Rev. 2.1 Previous Revision Revision [Date __| Subjects (major changes since last revision) 2.0 2021-02-11 _|Release of final version 21 2021-04-22 |Update capacitances and gate charges Trademarks All referenced product or service names and trademarks are the property of their respective owners. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: erratum@infineon.com Published by Infineon Technologies AG
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