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Technical content
Features
+ N-channel rab + Very low on-resistance Rosjon) + Superior thermal resistance + 100% avalanche tested 123) + Pb-free lead plating; ROHS compliant 4567) + Halogen-free according to IEC61249-2-21 8 Product validation Fully qualified according to JEDEC for Industrial Applications Table 1 Key Performance Parameters aT Ce Eo @) @ RoHS IPTOS4N15N5 PG-HSOF-8 osantsns =| Final Data Sheet 1 Rev. 2.0, 2021-09-10
OptiMOS™ 5 Power-Transistor, 150 V Cinfi neon IPTOS4N15N5 Table of Contents Final Data Sheet 2 Rev. 2.0, 2021-09-10
OptiMOS™ 5 Power-Transistor, 150 V ¢ In ineon IPTO54N15N5
1 Maximum ratings
at Ta=25 °C, unless otherwise specified Table 2__ Maximum ratings Paramet Note / Test Condit arameter ote / Test Condition [min. |Typ._[Max._|
143 Ves=10 V, Tc=25 °C
Continuous drain current’? lo 101. A Ves=10 V, Tc=100 °C
17.5 Ves=10V, Ta=25°C, Rinsa=40°C/W”
Avalanche energy, single pulse les |- —s|-——s([t90.— fms Ip=100 A, Res=25 Q «cin at 250 Tc=25 °C Power dissipation me ob fF Be bh | Ta=25 °C, Roua=40 °C/W? Operating and storage temperature ite [ss | is fo | re cumatic category; DIN IEC 68-1:
2 Thermal characteristics
Table 3 Thermal characteristics Paramet symbol Note / Test Condit arameter ymbol jlote / Test Condition [min. [Typ.[Max._| Thermal resistance, junction - case [Rec | s|- —sfoe —_fecrw - Thermal resistance, junction - ambient, 3 6 cm? cooling area row to om : Thermal resistance, junction - ambient, 3 minimal footprint” Pow Fe ow. *) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature as specified. For other case temperatures please refer to Diagram 2, De-rating will be required based on the actual environmental conditions. 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm? (one layer, 70 ym thick) copper area for drain connection. PCB is vertical in still air. 3) See Diagram 3 for more detailed information ” See Diagram 13 for more detailed information Final Data Sheet 3 Rev. 2.0, 2021-09-10
OptiMOS™ 5 Power-Transistor, 150 V ¢ In fi neon IPTOS4N15N5 3_ Electrical characteristics at Tj=25 °C, unless otherwise specified Table 4 Static characteristics Paramet symbol Note / Test Condit ‘arameter yymbol lote est Condition [min.[Typ._[Max._| Drain-source breakdown voltage [Veaoss 150 |- |- |v | Ves=0 V, lb=1 mA Gate threshold voltage IVesm [30 [98 (46 [V [Vos Vos, =181 WA A 0.1 1.0 Vos=120 V, Ves=0 V, T=25 °C Zero gate voltage drain current eee Vos=120 Vv. Ves=0 v. T=125 °C Gate-source leakage current licss [= ——«|10—s[t00. [na Ves=20 V, Vos=0 V . . 46 |54 Ves=10 V, Io=50 A Drain-source on-state resistance roam fF 8 BS Ime | Ves=8 V, In=25 A Transconductance lo | [23 - fs | [Vos|22|/o|Ros(on)max, Ib=50 A Table 5 Dynamic characteristics Paramet Note / Test Condit ‘arameter ote est Condition [min. [Typ._[Max._| Input capacitance” [Css (-___—*([4100_ [5300 Ves=0 V, Vos=75 V, f=1 MHz Output capacitance” [Cos [= [4000 [1300 Ves=0 V, Vos=75 V, f=1 MHz Reverse transfer capacitance” [Case [2442p Ves=0 V, Vos=75 V, f&1 MHz i Von=75 V, Ves=10 V, Ib=50 A, ise ti Voo=75 V, Ves=10 V, In=50 A, i Von=75 V, Ves=10 V, Ib=50 A, . Vop=75 V, Ves=10 V, Ib=50 A, Table 6 Gate charge characteristics” Paramet Note / Test Conditi ‘arameter lote / Test Condition [min.|Typ. [Max._| Gate to source charge [Qs [-——«|28 = [nC _| Von 75 V, fo=50 A, Vos=0 to 10 V Gate charge at threshold [Quem > «(18.7 [+ [nC Voo=75 V, o=50 A, Vos=0 to 10 V Gate to drain charge” [Qe ttt [46.7 [nc | Vo0=75 V, b=50 A, Vos=0 to 10 V Switching charge [Qu [-——*| 48.2 |- [nC _| Voo=75 V, 10=50 A, Vos=0 to 10 V Gate charge total” la se ——|8 [69 |nC_| Voo= 75 V, o=50 A, Vos=0 to 10 V Gate plateau voltage [Vows > (5.8 | |V__| Von 75 V, fo=50 A, Vos=0 to 10 V ») Defined by design. Not subject to production test. 2) See "Gate charge waveforms” for parameter definition Final Data Sheet 4 Rev. 2.0, 2021-09-10
OptiMOS™ 5 Power-Transistor, 150 V ¢ In ineon IPTOS4N15N5 Table 7 Reverse diode paramet symbol Note / Test Conditi arameter ymbo lote / Test Condition [min. [Typ.[Max._| Diode continuous forward current lis eta Tc=25 °C Diode forward voltage [Vos - «0.83. |4.0 |V__| Vas=0 V, k=50 A, Ti=25 °C Reverse recovery time” lt _'|- ‘(48.0 [96.0 ns | Va=75 V, Ir=50 A, die/dt=100 A/us Reverse recovery charge") la «Fs jeoa [421 [nc | Vp=75 V, Ir=50 A, dic/dt=100 A/us ‘) Defined by design. Not subject to production test. Final Data Sheet 5 Rev. 2.0, 2021-09-10
OptiMOS™ 5 Power-Transistor, 150 V Cin fi neon IPTOS4N15N5
4 Electrical characteristics diagrams
i | a ee ee ee ESE EEE eS | eS SSS | eS a eS a 200 +f KP SS a eS SS a sO i a =e 160 i. a EE =F ES = A OE os EN Ce eS E+ —- 4 FF a a A eS SS a A so {+f} —_f ff A —— A ————E go | rN 28 OOOO a CO SS | rN a or 0 ee ee en | 0 25 50 75 100 125 150 175 200 i) 25 50 75 100 125 150 175 200 Te [°C] Tc [°C] SSS SS ea H— single puse tt —E HH Pritt EH Se EEE ws H—-o0t PE TT ANTTIESST i []--- 0.02 Eero STONE RCT e008 NIC Co
10 SSS eae Serer | ae ee
SH eee | ccmmeo cl ELI ll a aS 10 TT TT tt tor LOU ATTN TTT Ee SS SSE SSS |e Steet ttt .) SSS Se Mpeg < ee eS a fem teri | Dae TTT TTT eet eee SS SS SESS SSS EE Y EEE 0 ms Et 10" Oe eee 40° LTT NIN ETT] Pecan =e aed ee | SS A 4. SSS SFr NE ie Aa ETM I TTI TT FET AAT | ge TIE TUTTI VET ee LL CE |: V1 10° 10° 107 10° 10° 10+ 10° 107 107 10° Vos [VJ ts] Final Data Sheet 6 Rev. 2.0, 2021-09-10
OptiMOS™ 5 Power-Transistor, 150 V nrineon IPTOS4N15N5 Diagram 5: Typ. output characteristics Diagram 6: Typ. drain-source on resistance OY EERE |” EE ee EERE Ee ee eee Pe PPP COCO
5 SERRE ee ECC ee
400 (I COCOA CECE CCC | LTT TTA TT eg YY ey a =e AoA eee} 3 COREE CCC ee © 0 SOOO eee |B Ree ee ld suuaea? /2eeeesssseessunania | MMserscuetsse2:sssaersenessese5n A = —— im ECE erry é 6 OEE te / va GLEE co COCOA eee HEBER EERE REECE Ut =rt0v
200 VASE FRESE Ree PEE]
HH A4-HEHE-H-H- HHH - H+] COC HEYA EEE EEE EEE EEE SE too CECE eee CECE 2/1 oe COC Y/_|_ SSS Se 2 my 22 TT TTT TTT ry re S / 40S | SE y 400 COCO ) COE EEE EHS V 9 EOCCCACCC eee 0 1 2 3 4 5 0 50 100 150 200 250 300 Vos [V] Io IA] To=f(Vos), Ti=25 °C; parameter: Ves Rosten)=(lo), T=25 °C; parameter: Ves Diagram 7: Typ. transfer characteristics Diagram 8: Typ. drain-source on resistance
280 Tee a
aap CECCCCC ECC SOOO COIRAC Ee COCEECE Cee EARP rec CCC i a eS A
200 EEECCCE ECC] Pp
yeo HECECCCCCEEECeeeeeee je eee CEE 12 A = Gee) eB eee
2 COCEPCEPCeeeeeeeeeeeeee er) ye a
yoo EECA |} ee COCPCePeeeereeeeeeeeee er) | 8 A Se a COCECEE CCE COCs eer 7 a COCA HERE sc ee a a COCO a
40 CEP eo Pe
9 SOCCCCC CEC eer eer] ee
0 4 2 3 4 5 6 7 0 5 10 15 20 Ves [V] Ves [V] Io=f( Ves), |Vos|>2|/o|Ros(onymax; parameter: 7; Rosjon)=f(Ves), [o=50 A; parameter: Tj Final Data Sheet 7 Rev. 2.0, 2021-09-10
OptiMOS™ 5 Power-Transistor, 150 V nrineon IPTO54N15N5 Diagram 9: Normalized drain-source on resistance Diagram 10: Typ. gate threshold voltage no Sooo
20 EEOC CORSE
FE EEEEEEEEEEEEEera aU EN RAC CECEC EEE LO Pee ‘ COCO ERS) > COO PARA
2 SOO HS
8 eee eee eee EEE PPT TTT AWN TEEN ETT 8 4 CECCCEEEEE CCN PN
2 COCO SEE EEE et
; eo Nieto ua] 3 y ee S22 eco SCP eee eee EE EE BCU | EE eS a Se S I oe HEC HH EECCEEC EEE z rai CECE é€ COPIA CECE COC 7 SOOO o COCOA COC ee CECE eee CECE CECE EEE CECE CECE EEE CECE oo LCCC Eee] 9 -CCCEEC eee ee -80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200 TEC] TEC] Ros(on=f(Tj), lo=50 A, Ves=10 V Vestn=f(T)), Ves= Vos; parameter: lo Diagram 11: Typ. capacitances Diagram 12: Forward characteristics of reverse diode 10) eee eee 10° oS ERREEEREEREREER REE REEREREEEREH H—25°c EEEEERERERERERREEEEE) ERREEEEEEEEEEEEEEEEEEEEEEEEEEH 4 FEREREEEEEEEEEEEEEEH CPP rrr errr eer eee eee) [}—— 25°C,max FCC REECE css [}--= 175°C eet SCHERRER SHEER SEER ER BREE RR ES [fev 175°C, max | TTT er eer SST TTT a FREER EERE EERE RRR SEE EEREEREH FREER REE EEER EERE SERRE EEE FERRER EEE EEE EEE EEE SSE EERE EERE EERE eee eee FEE EEE EEE EE tose Se eee Se Pe eee c ee = SS ee 2 7 N ° PUT TTITITITT TTT HITT * HI TT FREER ESSERE REE REE REE REE REE REH EERE EERE EAR HEHE EERE EEE NCEE EEE EEE EEE EEE EEE EH EERE EEE EEE COPPr rrr rsx rer eee) ee Be ee eee COPS ee COCCI COCCI CUT PSSST LOTT PT THETA Tisscocy ) LTTE EEE wo OSS] | ae | Vos [V] Vsp [V] C=f(Vos); Ves=0 V; f=1 MHz I=f(Vso); parameter: T; Final Data Sheet 8 Rev. 2.0, 2021-09-10
| fi OptiMOS™ 5 Power-Transistor, 150 V ¢ nrineon IPTO54N15N5 Diagram 13: Avalanche characteristics Diagram 14: Typ. gate charge a a et eee 2 720 Settee Wo=7sy HH | H=--zovp TE eA CCCI CI ET aa ee wo LUTTE TET BEECH ee Eco CECCEEELEELLELLLLLI WF CELL SEES SES CEEEEECEEEEEE EEA EEL COTTA IST TST a 6 eee CELL LUI TTI UTA ANU) J ECE err © yo — | 2 (CHW z SER SESE SSE Sey / nse 400 °C ff COPPA TIE PTET COCO NS HEHEHE to? et COCOA = TT — | | — / SHEA Fran Fria —-irni | EOAPRREEPEER Pore EH Mua US00005EEEEEUEGUSUEEEREEEE 10° i} 10" 10° 10° 107 10° 0 10 20 30 40 50 60 tay [us] Qeate [NC] Ins=f(tav), Ros=25 Q, parameter: Thwan Vos=f(Qgate), /0=50 A pulsed, T=25 °C; parameter: Voo Diagram 15: Drain-source breakdown voltage Diagram Gate charge waveforms 160 — oe A eee ee eee eee ee eee 158 eee ee eee eee Ves A A A 7 eee ee ee eee eee ee ee ae Q eee ee ee ee g 156 eee ee eee eee A 7 eee ee ee Cerrrererre reer yee eee ee ee eee ee ee eee
184 Eee Ae
180 [EEE AEE eee eee eee eee ee eee eee 4 eee | 148 ae ee eee / A eee ee eee Cerra tTry yee FREE EERE EE EERE EEE EEE Q 146 Q fi eee Gown Se, eee ee eee eee ee eee 144 eee ee eee Polo | Qou 80-40 0 40 80 120 160 200 TPC] Veness AT BET A OO Final Data Sheet 9 Rev. 2.0, 2021-09-10
OptiMOS™ 5 Power-Transistor, 150 V ¢ Infi neon IPTO54N15N5
5 Package Outlines
E 5 A ee Kr) i SY x a KY yn ! s DICITITIOI LILI Ty ¢ " 8xb i le] ia ——| E Ea w ES z 1) Mold Flash area = ALA SAA | [| 2: 1) partially covered with Mold Flash [___mumerers [INCHES [om a ae ae DOCUMENT NO. ———— [or 970890 032 0.380 0 [ba oan oso Toot 0.020 SCALE [e040 050] | ea) a 2 | 2 [e970 t0.t0 0382 0398 | 0 2 a a | "sm a a 7 | (re 20 esc) 0a esc) EUROPEAN PROJECTION a CC a A <2 | Ce © ck: a a a, << =: ISSUE DATE a | a 7: SX 7 ee a a | 02 Figure 1 Outline PG-HSOF-8, dimensions in mm/inches Final Data Sheet 10 Rev. 2.0, 2021-09-10
OptiMOS™ 5 Power-Transistor, 150 V Cin ineon IPTO54N15N5
Revision History
Revision: 2021-09-10, Rev. 2.0 Previous Revision Revision [Date __| Subjects (major changes since last revision) 2.0 2021-09-10 | Release of final version Trademarks All referenced product or service names and trademarks are the property of their respective owners We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: erratum@infineon.com Published by Infineon Technologies AG
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