IPM018N10NM5LF2 INFINEON | Alldatasheet
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Technical content
Features
Fully qualified according to JEDEC for Industrial Applications Table 1 Key performance parameters Parameter Value Unit V 100 V R 1.85 mΩ I 285 A I ( =56 V, =10 ms)V t 12 A PG‑HSOG‑4 Part number Package Marking Related links IPM018N10NM5LF2 PG‑HSOG‑4 18N10LF2 ‑ Ideal for hot‑swap and e‑fuse applications• Very low on‑resistance R• DS(on) Wide safe operating area SOA• Low V spread• gs(th) Improved current sharing• N‑channel, normal level• 100% avalanche tested• Pb‑free lead plating; RoHS compliant• Halogen‑free according to IEC61249‑2‑21• DS DS(on),max D pulse DS p Public IPM018N10NM5LF2 Final datasheet Drain tab Gate Pin 1 Source Pin 2-4 *1: Internal body diode
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 2 Revision 1.0 https://www.infineon.com 2025‑03‑07 Table of contents
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 3 Revision 1.0 https://www.infineon.com 2025‑03‑07
1 Maximum ratings
at =25 °C, unless otherwise specifiedT Table 2 Maximum ratings Parameter Symbol Values Unit Note / Test condition Min. Typ. Max. Continuous drain current 1) I ‑ ‑ 285 A V =10 V, =25 °CT
204 V =10 V, =100 °CT
213 V =15 V, =100 °CT
Pulsed drain current 3) I ‑ ‑ 1140 A T =25 °C Avalanche energy, single pulse 4) E ‑ ‑ 807 mJ I =100 A, =25 ΩR Gate source voltage V ‑20 ‑ 20 V ‑ Power dissipation P ‑ ‑ 349 W T =25 °C Operating and storage temperature T, T ‑55 ‑ 175 °C ‑ Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature as 1) specified. For other case temperatures please refer to Diagram 2. De‑rating will be required based on the actual environmental conditions. Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 μm thick) copper area for drain connection. PCB 2) 2 is vertical in still air. See Diagrams 3 and 4 for more detailed information3) See Diagram 14 for more detailed information4)
2 Thermal characteristics
Table 3 Thermal characteristics Parameter Symbol Values Unit Note / Test condition Min. Typ. Max. Thermal resistance, junction ‑ case R ‑ ‑ 0.43 °C/W ‑ Thermal resistance, junction ‑ ambient, 6 cm² cooling area 5) R 40 Thermal resistance, junction ‑ ambient, minimal footprint R 62 Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm (one layer, 70 μm thick) copper area for drain connection. PCB 5) 2 is vertical in still air. A D GS C GS C GS C GS A thJA D,pulse A AS D GS GS tot C A thJA j stg thJC thJA thJA
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 4 Revision 1.0 https://www.infineon.com 2025‑03‑07
3 Electrical characteristics
at =25 °C, unless otherwise specifiedT Table 4 Static characteristics Parameter Symbol Values Unit Note / Test condition Min. Typ. Max. Drain‑source breakdown voltage V 100 ‑ ‑ V V =0 V, =1 mAI Gate threshold voltage V 2.85 3.15 3.45 V V = , =240 μAV I Zero gate voltage drain current I ‑ 0.1 1 μA V =100 V, =0 V, =25 °CV T 10 100 V =100 V, =0 V, =125 °CV T Gate‑source leakage current I ‑ 10 100 nA V =20 V, =0 VV Drain‑source on‑state resistance R ‑ 1.4 1.7 mΩ V =15 V, =100 AI 1.6 1.85 V =10 V, =100 AI Gate resistance R ‑ 1.4 2.1 Ω ‑ Transconductance g 65 130 ‑ S | |≥2| | , =100 AV I R I Table 5 Dynamic characteristics Parameter Symbol Values Unit Note / Test condition Min. Typ. Max. Input capacitance 6) C 11000 14000 pF V =0 V, =50 V, =1 MHzV fOutput capacitance 6) C 1600 2100 Reverse transfer capacitance 6) C 61 110 Turn‑on delay time t ‑ ns V =50 V, =10 V, =100 A, V I =1.6 ΩR Rise time t 23 Turn‑off delay time t 36 Fall time t 16 Defined by design. Not subject to production test.6) j (BR)DSS GS D GS(th) DS GS D DSS DS GS j DS GS j GSS GS DS DS(on) GS D GS D G fs DS D DS(on)max D iss GS DSoss rss d(on) DD GS D G,ext r d(off) f
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 5 Revision 1.0 https://www.infineon.com 2025‑03‑07 Table 6 Gate charge characteristics 7) Parameter Symbol Values Unit Note / Test condition Min. Typ. Max. Gate to source charge Q 74 ‑ nC V =50 V, =100 A, =0 to 10 VI V Gate charge at threshold Q 35 ‑ nC Gate to drain charge 8) Q 25 38 nC Switching charge Q 64 ‑ nC Gate charge total 8) Q 142 178 nC Gate plateau voltage V 6.6 ‑ V Gate charge total, sync. FET Q ‑ 128 ‑ nC V =0.1 V, =0 to 10 VV Output charge 8) Q ‑ 181 241 nC V =50 V, =0 VV See "Gate charge waveforms" for parameter definition7) Defined by design. Not subject to production test.8) Table 7 Reverse diode Parameter Symbol Values Unit Note / Test condition Min. Typ. Max. Diode continuous forward current I ‑ ‑ 285 A T =25 °C Diode pulse current I 1140 Diode forward voltage V ‑ 0.84 1.0 V V =0 V, =100 A, =25 °CI T Reverse recovery time 9) t 58 116 ns V =50 V, =100 A, d /d =100 A/μsI i t Reverse recovery charge 9) Q 118 236 nC Defined by design. Not subject to production test.9) gs DD D GS g(th) gd sw g plateau g(sync) DS GS oss DS GS S C S,pulse SD GS F j rr R F F rr
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 6 Revision 1.0 https://www.infineon.com 2025‑03‑07
4 Electrical characteristics diagrams
Diagram 1: Power dissipation Diagram 2: Drain current P =f( )T I =f( ); ≥10 VT V Diagram 3: Safe operating area Diagram 4: Safe operating area I =f( ); =25 °C; =0; parameter: V T D t I =f( ); =125 °C; =0; parameter: V T D t tot C D C GS D DS C p D DS C p 0 25 50 75 100 125 150 175 TC [°C] 100 150 200 250 300 350 400Ptot [W] 0 25 50 75 100 125 150 175 TC [°C] 100 150 200 250 300ID [A] 10 1 100 101 102 VDS [V] 10 1 100 101 102 103 104 ID [A] 1 µs 10 µs 100 µs1 ms10 ms 100 ms DC 10 1 100 101 102 VDS [V] 10 1 100 101 102 103 104 ID [A] 1 µs 10 µs 100 µs1 ms 10 ms 100 ms DC
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 7 Revision 1.0 https://www.infineon.com 2025‑03‑07 Diagram 5: Max. transient thermal impedance Diagram 6: Typ. output characteristics Z =f( ); parameter: = /t D t T I =f( ), =25 °C; parameter: V T V Diagram 7: Typ. drain‑source on resistance Diagram 8: Typ. transfer characteristics R =f( ), =25 °C; parameter: I T V I =f( ), | |>2| | ; parameter: V V I R T thJC p p D DS j GS DS(on) D j GS D GS DS D DS(on)max j 10 6 10 5 10 4 10 3 10 2 10 1 100 tp [s] 10 3 10 2 10 1 100 101 ZthJC [K/W] single pulse 0.01 0.02 0.05 0.1 0.2 0.5 0 1 2 3 4 5 VDS [V] 200 400 600 800 1000 1200ID [A] 7 V 8 V 9 V 10 V 12 V 15 V 0 100 200 300 400 500 600 ID [A] RDS(on) [m ] 7 V 8 V 9 V 10 V 12 V 15 V 0 1 2 3 4 5 6 7 8 9 VGS [V] 200 400 600 800 1000ID [A] 25 °C 175 °C
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 8 Revision 1.0 https://www.infineon.com 2025‑03‑07 Diagram 9: Typ. drain‑source on resistance Diagram 10: Normalized drain‑source on resistance R =f( ), =100 A; parameter: V I T R =f( ), =100 A, =10 VT I V Diagram 11: Typ. gate threshold voltage Diagram 12: Typ. capacitances V =f( ), = ; parameter: T V V I C=f( ); =0 V; =1 MHzV V f DS(on) GS D j DS(on) j D GS GS(th j GS DS D DS GS 0 2 4 6 8 10 12 14 16 VGS [V] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 RDS(on) [m ] 25 °C 175 °C 0 25 50 75 100 125 150 175 200 Tj [°C] 0.0 0.4 0.8 1.2 1.6 2.0 2.4 RDS(on) (normalized to 25 °C) 0 25 50 75 100 125 150 175 200 Tj [°C] 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VGS(th) [V] 240 µA 2.4 mA 0 20 40 60 80 100 VDS [V] 101 102 103 104 105 C [pF] Ciss Coss Crss
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 9 Revision 1.0 https://www.infineon.com 2025‑03‑07 Diagram 13: Forward characteristics of reverse diode Diagram 14: Avalanche characteristics I =f( ); parameter: V T I =f( ); =25 Ω; parameter: t R T Diagram 15: Typ. gate charge Diagram 16: Min. drain‑source breakdown voltage V =f( ), =100 A pulsed, =25 °C; parameter: Q I T V V =f( ); =1 mAT I F SD j AS AV GS j,start GS gate D j DD BR(DSS) j D VSD [V] 101 102 103 104 IF [A] 25 °C 25 °C. max 175 °C 175 °C. max 100 101 102 103 tAV [µs] 100 101 102 103 IAV [A] 25 °C 100 °C 150 °C 0 20 40 60 80 100 120 140 Qgate [nC] 10VGS [V] 20 V 50 V 80 V 0 25 50 75 100 125 150 175 200 Tj [°C] 100 102 104 106 108 VBR(DSS) [V]
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 10 Revision 1.0 https://www.infineon.com 2025‑03‑07 Gate charge waveforms G a t e c h a r g e w a v e f o r m s
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 11 Revision 1.0 https://www.infineon.com 2025‑03‑07
5 Package outlines
Figure 1 Outline PG‑HSOG‑4, dimensions in mm DIMENSIONSMIN.MAX. bDcE AA1 6.100.90 7.80 1.106.408.20 MILLIMETERS1.500.001.700.15PG-HSOG-4-U01PACKAGE - GROUPNUMBER: E1D1E2 MIN.MAX.DIMENSIONSMILLIMETERSeL 2.00L1Ɵ0°8°D20.70 Ɵ Ɵ Ɵ18°12°aaa0.10bbb0.05 5.000.601.10N 4
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 12 Revision 1.0 https://www.infineon.com 2025‑03‑07 Figure 2 Footprint drawing PG‑HSOG‑4, dimensions in mm All dimensions are in units mmcoppersolder maskstencil aperturesAll pads are non-solder mask definedPin1 1.12.0552.331.015
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 13 Revision 1.0 https://www.infineon.com 2025‑03‑07 Figure 3 Packaging variant PG‑HSOG‑4, dimensions in mm The drawing is in compliance with ISO 128-30, Projection Method 1 [ ]All dimensions are in units mm Pin1412 0.3 1.95167.5 8.38.29
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 14 Revision 1.0 https://www.infineon.com 2025‑03‑07 IPM018N10NM5LF2 Revision 2025‑03‑07, Rev. 1.0 Previous revisions Revision Date Subjects (major changes since last revision) 1.0 2025‑03‑07 Release of final datasheet
Revision history
OptiMOS™ 5 Linear FET 2 , 100 V IPM018N10NM5LF2 Public Datasheet 15 Revision 1.0 https://www.infineon.com 2025‑03‑07 Trademarks All referenced product or service names and trademarks are the property of their respective owners. We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: erratum@infineon.com Published by Infineon Technologies AG
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