IPD10N03LAG INFINEON | Alldatasheet

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Technical content

Features

  • Ideal for high-frequency dc/dc converters
  • Qualified according to JEDEC1) for target application
  • N-channel, logic level
  • Excellent gate charge x R DS(on) product (FOM)
  • Superior thermal resistance
  • 175 °C operating temperature
  • Pb-free lead plating; RoHS compliant Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Conditions Unit Continuous drain current I D T C=25 °C2) 30 A T C=100 °C 30 Pulsed drain current I D,pulse T C=25 °C3) 210 Avalanche energy, single pulse E AS I D=30 A, R GS=25 Ω 80 mJ Reverse diode dv /dt dv /dt I D=30 A, V DS=20 V, di /dt =200 A/µs, T j,max=175 °C 6 kV/µs Gate source voltage4) V GS ±20 V Power dissipation P tot T C=25 °C 52 W Operating and storage temperature T j, T stg -55 ... 175 °C IEC climatic category; DIN IEC 68-1 55/175/56 Value V DS 25 V R DS(on),max 10.4 mΩ I D 30 A Product Summary Type IPD10N03LA IPF10N03LA IPS10N03LA IPU10N03LA Marking 10N03LA 10N03LA 10N03LA 10N03LA Rev. 1.6 page 1 2006-05-15

Parameter Symbol Conditions Unit min. typ. max. Thermal characteristics Thermal resistance, junction - case R thJC - - 2.9 K/W SMD version, device on PCB R thJA minimal footprint - - 75 6 cm2 cooling area5) -- 5 0 Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D=1 mA 25 - - V Gate threshold voltage V GS(th) V DS=V GS, I D=20 µA 1.2 1.6 2 Zero gate voltage drain current I DSS V DS=25 V, V GS=0 V, T j=25 °C - 0.1 1 µA V DS=25 V, V GS=0 V, T j=125 °C - 10 100 Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 10 100 nA Drain-source on-state resistance R DS(on) V GS=4.5 V, I D=20 A - 13.9 17.4 mΩ V GS=10 V, I D=30 A - 8.7 10.4 Gate resistance R G -1- Ω Transconductance g fs |V DS|>2|I D|R DS(on)max, I D=30 A 20 41 - S 5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Values 2) Current is limited by bondwire; with an R thJC=2.9 K/W the chip is able to carry 53 A. 3) See figure 3 4) T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V 1) J-STD20 and JESD22 Rev. 1.6 page 2 2006-05-15

Parameter Symbol Conditions Unit min. typ. max. Dynamic characteristics Input capacitance C iss - 1021 1358 pF Output capacitance C oss - 393 522 Reverse transfer capacitance Crss -5 2 7 8 Turn-on delay time t d(on) - 6.3 9.4 ns Rise time t r - 4.8 7.2 Turn-off delay time t d(off) -1 8 2 7 Fall time t f - 2.8 4.2 Gate Charge Characteristics+A406) Gate to source charge Q gs - 3.4 4.5 nC Gate charge at threshold Q g(th) - 1.6 2.2 Gate to drain charge Q gd - 2.3 3.5 Switching charge Q sw - 4.1 5.8 Gate charge total Q g - 8.2 11 Gate plateau voltage V plateau - 3.3 - V Gate charge total, sync. FET Q g(sync) V DS=0.1 V, V GS=0 to 5 V - 7.2 9.6 nC Output charge Q oss V DD=15 V, V GS=0 V - 8.5 11 Reverse Diode Diode continous forward current I S - - 30 A Diode pulse current I S,pulse - - 210 Diode forward voltage V SD V GS=0 V, I F=30 A, T j=25 °C - 0.93 1.2 V Reverse recovery charge Q rr V R=15 V, I F=I S, di F/dt =400 A/µs - - 10 nC 6) See figure 16 for gate charge parameter definition T C=25 °C Values V GS=0 V, V DS=15 V, f =1 MHz V DD=15 V, V GS=10 V, I D=15 A, R G=2.7 Ω V DD=15 V, I D=15 A, V GS=0 to 5 V Rev. 1.6 page 3 2006-05-15

1 Power dissipation 2 Drain current

P tot=f(T C) I D=f(T C); V GS≥10 V 3 Safe operating area 4 Max. transient thermal impedance I D=f(V DS); T C=25 °C; D =0 Z thJC=f(t p) parameter: t p parameter: D =t p/T 1 µs 10 µs 100 µs 1 ms 10 ms DC 100 1000 0.1 1 10 100 V DS [V] I D [A] limited by on-state resistance single pulse 0.01 0.02 0.05 0.1 0.2 0.5 10010-110-210-310-410-510-6 0.01 0.1 0000001 t p [s] Z thJC [K/W] 0 50 100 150 200 T C [°C] P tot [W] 0 50 100 150 200 T C [°C] I D [A] Rev. 1.6 page 4 2006-05-15

5 Typ. output characteristics 6 Typ. drain-source on resistance I D=f(V DS); T j=25 °C R DS(on)=f(I D); T j=25 °C parameter: V GS parameter: V GS 7 Typ. transfer characteristics 8 Typ. forward transconductance I D=f(V GS); |V DS|>2|I D|R DS(on)max g fs=f(I D); T j=25 °C parameter: T j 3 V 3.2 V 3.5 V 3.8 V 4.1 V 4.5 V 10 V 0 1 02 03 04 05 0 I D [A] R DS(on) [mΩ ] 25 °C175 °C 012345 V GS [V] I D [A] 0 1 02 03 04 05 06 0 I D [A] g fs [S] 2.8 V 3 V 3.2 V 3.5 V 3.8 V 4.1 V

4.5 V10 V

V DS [V] I D [A] Rev. 1.6 page 5 2006-05-15

9 Drain-source on-state resistance 10 Typ. gate threshold voltage R DS(on)=f(T j); I D=30 A; V GS=10 V V GS(th)=f(T j); V GS=V DS parameter: I D 11 Typ. capacitances 12 Forward characteristics of reverse diode C =f(V DS); V GS=0 V; f =1 MHz I F=f(V SD) parameter: T j typ 98 % -60 -20 20 60 100 140 180 T j [°C] R DS(on) [mΩ ] 20 µA 200 µA 0.5 1.5 2.5 -60 -20 20 60 100 140 180 T j [°C] V GS(th) [V] Ciss Coss Crss 104 103 102 101 10 100 1000 10000 0 5 10 15 20 25 30 V DS [V] C [pF] 25 °C 175 °C 25 °C, 98% 175 °C, 98% 100 1000 V SD [V] I F [A] Rev. 1.6 page 6 2006-05-15

13 Avalanche characteristics 14 Typ. gate charge I AS=f(t AV); R GS=25 Ω V GS=f(Q gate); I D=15 A pulsed parameter: T j(start) parameter: V DD

15 Drain-source breakdown voltage 16 Gate charge waveforms

V BR(DSS)=f(T j); I D=1 mA 5 V 15 V 20 V 048 1 2 1 6 2 0 Q gate [nC] V GS [V] -60 -20 20 60 100 140 180 T j [°C] V BR(DSS) [V] V GS Q gate V gs(t h ) Q g(th) Q gs Q gd Q sw Q g 25 °C100 °C150 °C 100 1 10 100 1000 t AV [µs] I AV [A] Rev. 1.6 page 7 2006-05-15

PG-TO252-3-11: Outline Footprint: Packaging: Rev. 1.6 page 8 2006-05-15

PG-TO252-3-23: Outline Footprint: Rev. 1.6 page 9 2006-05-15

PG-TO251-3-11: Outline PG-TO251-3-21: Outline Rev. 1.6 page 10 2006-05-15

PG-TO251-3-11: Outline PG-TO251-3-21: Outline Rev. 1.6 page 11 2006-05-15

81726 München, Germany

© Infineon Technologies AG 2006. All Rights Reserved. Attention please! The information given in this data sheet shall in no event be regarded as a guarantee of conditions or characteristics (“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com ). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.6 page 12 2006-05-15