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Infineon Technologies, Rev. 2.0 18.06.2013 OptiMOSTM3 Power MOS Transistor Chip Type V(BR)DSS RDS(on) Die size Thickness IPC313N10N3R 100 V 2.7 mΩ1) 6 * 5.2 mm2 220 µm
DESCRIPTION
- N-channel enhancement mode
- For dynamic characterization refer to the datasheet of IPB027N10N3 G2)
- AQL 0.65 for visual inspection according to failure catalogue
- Electrostatic Discharge Sensitive Device according to JEDEC
- Die bond: soldered or glued
- Backside metallization: NiV system
- Frontside metallization: AlCu system
- Passivation: nitride (only on edge structure) Electrical Characteristics on Wafer Level at Tj = 25 °C, unless otherwise specified. Parameter Symbol Value Unit Conditions min. typ. max. Drain-source breakdown voltage V(BR)DSS 100 - - V V GS = 0V ID = 1 mA Gate threshold voltage VGS(th) 2 2.7 3.5 V V DS = VGS ID = 275 µA Zero gate voltage drain current IDSS - 0.1 1 µA V GS = 0V VDS = 100 V Gate-source leakage current IGSS - 1 100 nA V GS = 20 V VDS = 0 V Drain-source on-resistance RDS(on) - 1.9 3) 100 4) mΩ VGS= 10 V ID= 2.0 A Reverse diode forward on-voltage VSD - 1.0 1.2 V V GS=0 V IF= 1 A Internal gate resistance RG - 8 - Ω Avalanche energy, single pulse EAS - 45 5) - mJ I D= 30 A, RGS=25Ω
Infineon Technologies, Rev. 2.0 18.06.2013 Chip-Layout: 1) packaged in a P-TO263-3 (see ref. product) 2) IPB027N10N3 G dynamic characterization does not include the internal added RG 3) typical bare die RDS(on); VGS=10V 4) limited by wafer test-equipment 5) Wafer tested. For general avalanche capability refer to the datasheet of IPB027N10N3 G
Infineon Technologies, Rev. 2.0 18.06.2013 Published by Infineon Technologies AG
81726 Munich, Germany
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