IPB048N15N5LFATMA1

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Document overview

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• PDF pages: 11

Technical content

Features

• Idealforhot-swapande-fuseapplications
• Verylowon-resistanceRDS(on)
• WidesafeoperatingareaSOA
• N-channel,normallevel
• 100%avalanchetested
• Pb-freeplating;RoHScompliant
• QualifiedaccordingtoJEDEC1)fortargetapplications
• Halogen-freeaccordingtoIEC61249-2-21 Table1KeyPerformanceParameters Parameter Value Unit VDS 150 V RDS(on),max 4.8 mΩ ID(siliconlimited) 182 A ID(packagelimited) 120 A Ipulse(VDS=56V,tp=10 ms) 10.8 A Type/OrderingCode Package Marking RelatedLinks IPB048N15N5LF PG-TO 263-3 048N15LF - 1) J-STD20 and JESD22

OptiMOSTM5LinearFET,150V IPB048N15N5LF Rev.2.0,2017-03-29Final Data Sheet TableofContents

OptiMOSTM5LinearFET,150V IPB048N15N5LF Rev.2.0,2017-03-29Final Data Sheet 1Maximumratings atTC=25°C,unlessotherwisespecified Table2Maximumratings Values Min. Typ. Max. Parameter Symbol Unit Note/TestCondition Continuous drain current ID 120 115 A VGS=10V,TC=25°C VGS=10V,TC=100°C VGS=10V,TC=25°C,RthJA=40K/W1) Pulsed drain current2) ID,pulse - - 480 A TC=25°C Avalanche energy, single pulse3) EAS - - 30 mJ ID=40A,RGS=25Ω Gate source voltage VGS -20 - 20 V - Power dissipation Ptot - - 313 W TC=25°C Operating and storage temperature Tj,Tstg -55 - 150 °C IEC climatic category; DIN IEC 68-1: 55/150/56 2Thermalcharacteristics Table3Thermalcharacteristics Values Min. Typ. Max. Parameter Symbol Unit Note/TestCondition Thermal resistance, junction - case RthJC - 0.25 0.4 K/W - Device on PCB, minimal footprint RthJA - - 62 K/W - Device on PCB, 6 cm² cooling area1) RthJA - - 40 K/W - 1) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. 2) See Diagram 3 for more detailed information 3) See Diagram 13 for more detailed information

OptiMOSTM5LinearFET,150V IPB048N15N5LF Rev.2.0,2017-03-29Final Data Sheet 3Electricalcharacteristics Table4Staticcharacteristics Values Min. Typ. Max. Parameter Symbol Unit Note/TestCondition Drain-source breakdown voltage V(BR)DSS 150 - - V VGS=0V,ID=1mA Gate threshold voltage VGS(th) 3.3 4.1 4.9 V VDS=VGS,ID=255µA Zero gate voltage drain current IDSS 100 µA VDS=120V,VGS=0V,Tj=25°C VDS=120V,VGS=0V,Tj=125°C Gate-source leakage current IGSS -5 µA VGS=20V,VDS=0V VGS=-10V,VDS=0V Drain-source on-state resistance RDS(on) - 3.9 4.8 mΩ VGS=10V,ID=100A Gate resistance1) RG - 25 38 Ω - Transconductance gfs 17 34 - S |VDS|>2|ID|RDS(on)max,ID=100A Table5Dynamiccharacteristics1) Values Min. Typ. Max. Parameter Symbol Unit Note/TestCondition Input capacitance Ciss - 290 380 pF VGS=0V,VDS=75V,f=1MHz Output capacitance Coss - 1400 1800 pF VGS=0V,VDS=75V,f=1MHz Reverse transfer capacitance Crss - 13 23 pF VGS=0V,VDS=75V,f=1MHz Turn-on delay time td(on) - 8 - ns VDD=75V,VGS=10V,ID=60A, RG,ext=1.6Ω Rise time tr - 48 - ns VDD=75V,VGS=10V,ID=60A, RG,ext=1.6Ω Turn-off delay time td(off) - 42 - ns VDD=75V,VGS=10V,ID=60A, RG,ext=1.6Ω Fall time tf - 10 - ns VDD=75V,VGS=10V,ID=60A, RG,ext=1.6Ω Table6Gatechargecharacteristics2) Values Min. Typ. Max. Parameter Symbol Unit Note/TestCondition Gate to source charge Qgs - 2 - nC VDD=75V,ID=60A,VGS=0to10V Gate to drain charge1) Qgd - 56 - nC VDD=75V,ID=60A,VGS=0to10V Gate charge total1) Qg - 84 - nC VDD=75V,ID=60A,VGS=0to10V Gate plateau voltage Vplateau - 7 - V VDD=75V,ID=60A,VGS=0to10V Output charge1) Qoss - 211 280 nC VDD=75V,VGS=0V 1) Defined by design. Not subject to production test. 2) See ″Gate charge waveforms″ for parameter definition

OptiMOSTM5LinearFET,150V IPB048N15N5LF Rev.2.0,2017-03-29Final Data Sheet Table7Reversediode Values Min. Typ. Max. Parameter Symbol Unit Note/TestCondition Diode continuous forward current IS - - 120 A TC=25°C Diode pulse current IS,pulse - - 480 A TC=25°C Diode forward voltage VSD - 0.93 1.2 V VGS=0V,IF=100A,Tj=25°C Reverse recovery time1) trr - 60 - ns VR=75V,IF=60A,diF/dt=100A/µs Reverse recovery charge1) Qrr - 81 - nC VR=75V,IF=60A,diF/dt=100A/µs 1) Defined by design. Not subject to production test.

OptiMOSTM5LinearFET,150V IPB048N15N5LF Rev.2.0,2017-03-29Final Data Sheet 4Electricalcharacteristicsdiagrams Diagram1:Powerdissipation TC[°C] Ptot[W] 100 125 150 175 100 150 200 250 300 350 Ptot=f(TC) Diagram2:Draincurrent TC[°C] ID[A] 100 120 140 160 100 150 200 250 limited by package limited by silicon ID=f(TC);VGS≥10V Diagram3:Safeoperatingarea VDS[V] ID[A] 100 101 102 103 100 101 102 103 1 µs 10 µs 100 µs 1 ms 10 ms DC ID=f(VDS);TC=25°C;D=0;parameter:tp Diagram4:Max.transientthermalimpedance tp[s] ZthJC[K/W] 10-5 10-4 10-3 10-2 10-1 100 10-2 10-1 100 0.5 0.2 0.1 0.05 0.02 0.01 single pulse ZthJC=f(tp);parameter:D=tp/T

OptiMOSTM5LinearFET,150V IPB048N15N5LF Rev.2.0,2017-03-29Final Data Sheet Diagram5:Typ.outputcharacteristics VDS[V] ID[A] 10V 5.5V ID=f(VDS),Tj=25°C;parameter:VGS Diagram6:Typ.drain-sourceonresistance ID[A] RDS(on)[mΩ ] 8 V 10 V RDS(on)=f(ID),Tj=25°C;parameter:VGS Diagram7:Typ.transfercharacteristics VGS[V] ID[A] 150 °C 25 °C ID=f(VGS),|VDS|>2|ID|RDS(on)max;parameter:Tj Diagram8:Typ.forwardtransconductance ID[A] gfs[S] gfs=f(ID),VDS=5V,Tj=25°C

OptiMOSTM5LinearFET,150V IPB048N15N5LF Rev.2.0,2017-03-29Final Data Sheet Diagram9:Normalizeddrain-sourceon-stateresistance Tj[°C] RDS(on),normalizedto25°C -80 -40 120 160 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 RDS(on)=f(Tj),ID=100A,VGS=10V Diagram10:Typ.gatethresholdvoltage Tj[°C] VGS(th)[V] -80 -40 120 160 2550 µA 255 µA VGS(th=f(Tj),VGS=VDS;parameter:ID Diagram11:Typ.capacitances VDS[V] C[pF] 100 125 150 101 102 103 104 Coss Ciss Crss C=f(VDS);VGS=0V;f=1MHz Diagram12:Forwardcharacteristicsofreversediode VSD[V] IF[A] 0.00 0.25 0.50 0.75 1.00 1.25 1.50 100 101 102 103 25 °C 25 °C, max 150 °C 150 °C, max IF=f(VSD);parameter:Tj

OptiMOSTM5LinearFET,150V IPB048N15N5LF Rev.2.0,2017-03-29Final Data Sheet Diagram13:Avalanchecharacteristics tAV[µs] IAV[A] 100 101 102 103 10-1 100 101 102 25 °C 100 °C 125 °C IAS=f(tAV);RGS=25Ω ;parameter:Tj,start Diagram14:Typ.gatecharge Qgate[nC] VGS[V] 100 30V 75V 120V VGS=f(Qgate);ID=60Apulsed,resistiveload;parameter:VDD Diagram15:Drain-sourcebreakdownvoltage Tj[°C] VBR(DSS)[V] -80 -40 120 160 144 146 148 150 152 154 156 158 160 VBR(DSS)=f(Tj);ID=1mA Gate charge waveforms

OptiMOSTM5LinearFET,150V IPB048N15N5LF Rev.2.0,2017-03-29Final Data Sheet 5PackageOutlines Figure1OutlinePG-TO263-3,dimensionsinmm/inches

OptiMOSTM5LinearFET,150V IPB048N15N5LF Rev.2.0,2017-03-29Final Data Sheet RevisionHistory IPB048N15N5LF Revision:2017-03-29,Rev.2.0 Previous Revision Revision Date Subjects (major changes since last revision) 2.0 2017-03-29 Release of final version TrademarksofInfineonTechnologiesAG AURIX™,C166™,CanPAK™,CIPOS™,CoolGaN™,CoolMOS™,CoolSET™,CoolSiC™,CORECONTROL™,CROSSAVE™,DAVE™,DI-POL™,DrBlade™, EasyPIM™,EconoBRIDGE™,EconoDUAL™,EconoPACK™,EconoPIM™,EiceDRIVER™,eupec™,FCOS™,HITFET™,HybridPACK™,Infineon™, ISOFACE™,IsoPACK™,i-Wafer™,MIPAQ™,ModSTACK™,my-d™,NovalithIC™,OmniTune™,OPTIGA™,OptiMOS™,ORIGA™,POWERCODE™, PRIMARION™,PrimePACK™,PrimeSTACK™,PROFET™,PRO-SIL™,RASIC™,REAL3™,ReverSave™,SatRIC™,SIEGET™,SIPMOS™,SmartLEWIS™, SOLIDFLASH™,SPOC™,TEMPFET™,thinQ™,TRENCHSTOP™,TriCore™. TrademarksupdatedAugust2015 OtherTrademarks Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. WeListentoYourComments Anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?Yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.Pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com Publishedby InfineonTechnologiesAG 81726München,Germany ©2017InfineonTechnologiesAG AllRightsReserved. LegalDisclaimer Theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics (“Beschaffenheitsgarantie”). Withrespecttoanyexamples,hintsoranytypicalvaluesstatedhereinand/oranyinformationregardingtheapplicationofthe product,InfineonTechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithoutlimitation warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. Inaddition,anyinformationgiveninthisdocumentissubjecttocustomer’scompliancewithitsobligationsstatedinthis documentandanyapplicablelegalrequirements,normsandstandardsconcerningcustomer’sproductsandanyuseofthe productofInfineonTechnologiesincustomer’sapplications. Thedatacontainedinthisdocumentisexclusivelyintendedfortechnicallytrainedstaff.Itistheresponsibilityofcustomer’s technicaldepartmentstoevaluatethesuitabilityoftheproductfortheintendedapplicationandthecompletenessoftheproduct informationgiveninthisdocumentwithrespecttosuchapplication. Information Forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestInfineon TechnologiesOffice(www.infineon.com). Warnings Duetotechnicalrequirements,componentsmaycontaindangeroussubstances.Forinformationonthetypesinquestion, pleasecontactthenearestInfineonTechnologiesOffice. TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered.