IMX122LQJ-C

IMX122LQJ-C SONY | Alldatasheet

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Features

◆ CMOS active pixel type dots ◆ Input clock frequency: 54 MHz/37.125 MHz ◆ Readout mode All-pixel scan mode HD1080 p mode (when INCK = 37.125 MHz) HD720 p mode (when INCK = 37.125 MHz) Window cropping mode Horizontal vertical 2 × 2 binning mode Vertical 1/2 subsampling mode ◆ Variable-speed shutter function (Minimum unit: One horizontal sync signal period (1XHS)) ◆ H driver, V driver and serial communication circuit on chip ◆ CDS/PGA on chip 0 dB to 24 dB: Analog Gain 24 dB (step pitch 0.3 dB) 24.3 dB to 42 dB: Analog Gain 24 dB + Digit al Gain 0.3 to 18 dB (step pitch 0.3 dB) ◆ 10-bit/12-bit A/D converter on-chip ◆ Output method switchable CMOS logic parallel SDR/DDR output Data-Clock output Low voltage LVDS serial 1ch/2ch output Data-Strobe output ◆ R, G, B primary color pigment mosaic filters on chip ◆ Recommended lens F value: 2.8 or more (close side) ◆ Recommended exit pupil distance: –30 mm to –∞ * “Exmor” is a trademark of Sony Corporation. The “Exmor” is a version of Sony's high performance CMOS image sensor with high-speed processing, low noise and low power dissipation by using column-parallel A/D conversion.

◆ CMOS image sensor ◆ Image size Diagonal 6.4 mm (Type 1/2.9) ◆ Total number of pixels All-pixel scan: 2000 (H) × 1241 (V) approx. 2.48 M pixels HD1080 p: 2000 (H) × 1121 (V) approx. 2.24 M pixels ◆ Number of effective pixels All-pixel scan: 1984 (H) × 1225 (V) approx. 2.43 M pixels HD1080 p: 1984 (H) × 1105 (V) approx. 2.19 M pixels ◆ Number of active pixels All-pixel scan: 1936 (H) × 1217 (V) approx. 2.36 M pixels HD1080 p: 1936 (H) × 1097 (V) approx. 2.12 M pixels ◆ Number of recommended recording pixels All-pixel scan: 1920 (H) × 1200 (V) approx. 2.30 M pixels HD1080 p: 1920 (H) × 1080 (V) approx. 2.07 M pixels ◆ Chip size ◆ Unit cell size 2.8 μm (H) × 2.8 μm (V) ◆ Optical black Horizontal (H) direction: Front 16 pixels, rear 0 pixels Vertical (V) direction: Front 16 pixels, rear 0 pixels ◆ Dummy Horizontal (H) direction: Front 0 pixels, rear 0 pixels Vertical (V) direction: Front 7 pixels, rear 0 pixels ◆ Substrate material Silicon

Supply voltage (analog 2.7 V) AV DD –0.3 to +3.3 V Supply voltage (digital 1.2 V) DV DD –0.3 to +2.0 V Supply voltage (digital 1.8 V) OV DD –0.3 to +3.3 V Input voltage (digital) V I –0.3 to OV DD +3.3 V Output voltage (digital) V O –0.3 to OV DD +3.3 V Guaranteed Operating temperature Topr –10 to +60 °C Guaranteed storage temperature Tstg –30 to +80 °C Guaranteed performance temperature Tspc –10 to +60 °C Recommended Operating Conditions Supply voltage (analog 2.7 V) AV DD 2.7 ± 0.1 V Supply voltage (digital 1.2 V) DV DD 1.2 ± 0.1 V Supply voltage (digital 1.8 V) OV DD 1.8 ± 0.1 V Input voltage (digital) V I –0.1 to OV DD +0.1 V Output voltage (digital) V O –0.1 to OV DD +0.1 V

This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the image sensor products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may , at any time, modify this Notice which will be available to you in the latest specifica tions book for the Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor. You should consult a sales representative of the subsidiary or distributor of Sony on such a use restriction notice when you consider using the Products. Use Restrictions The Products are intended for incorporation into such general electronic equipment as office products, communication products, measurement products, and home electronics products in accordance with the terms and conditions set forth in this specifications book and otherwise notified by Sony from time to time. You should not use the Products for critical applications which may pose a life- or injury- threatening risk or are highly likely to cause significant property damage in the event of failure of the Products. You should consult your sales representative beforehand when you consider using the Products for such critical applications. In addition, you should not use the Products in weapon or military equipment. Sony disclaims and does not assume any liability and damages arising out of misuse, improper use, modification, use of the Products for the above-mentioned critical applications, weapon and military equipment, or any deviation from the requirements set forth in this specifications book. Design for Safety Sony is making continuous efforts to further improve the quality and reliability of the Products; however, failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care to ensure the safe design of your products such as component redundancy, anti-conflagration features, and features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or other social damage as a result of such failure. Export Control If the Products are controlled items under the export control laws or regulations of various countries, approval may be required for the export of the Products under the said laws or regulations. You should be responsible for compliance with the said laws or regulations. No License Implied The technical information shown in this specifications book is for your reference purposes only . The availability of this specifications book shall not be construed as giving any indication that Sony and its licensors will license any intellectual property rights in such information by any implication or otherwise. Sony will not assume responsibility for any problems in connection with your use of such information or for any infringement of third-party rights due to the same. It is therefore your sole legal and financial responsibility to resolve any such problems and infringement. Governing Law This Notice shall be governed by and construed in accordance with the laws of Japan, without reference to principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating to this Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the court of first instance. Other Applicable Terms and Conditions The terms and conditions in the Sony additional specifications, which will be made available to you when you order the Products, shall also be applicable to your use of the Products as well as to this specifications book. You should review those terms and conditions when you consider purchasing and/or using the Products.

Chip Center and Optical Center 6.40 ± 0.075 mm 12.80 ± 0.10 mm 5.80 ± 0.075 mm 11.60 ± 0.10 mm A1-pin A10-pin L1-pin L10-pin Sensor Scaninng V Direction (normal) Top View Unit: mm Optical center Package reference plane Package Outline Sensor Scaninng H Direction Package Outline V direction Package Outline H direction Optical Center

(Top View) Reference pin RG GB GB RG GB R G RG GB L10-pin A10-pin L1-pin A1-pin 1200 16 24 8 1920 8 24 Ignored area of effective pixel side Margin for color processing Margin for color processing Ignored area of effective pixel side Margin for color processing Ignored area of effective pixel side Margin for color processing Ignored area of effective pixel side Ignored area of OB Ignored area of OB Vertical effective OB Number of recording pixels Number of recommended recording pixels Number of active pixels Number of effective pixels Total number of pixels Ignored area of OB Horizontal scan direction Vertical scan direction (Normal) Pixel Arrangement - Physical Image

Block Diagram and Pin Configuration (Top View) DCK DO0/DATA0 Sensor Control Unit (SCU) Bias PLL Drive Circuit 12/10-bit Digital Output CDS/Column Circuit Sensor DO1/DATAM0 DO2/STRBP0 DO3/STRBM0 DO4/STRBP1 DO5/STRBM1 DO6/DATAP1 DO7/DATAM1 DO8 DO9 DO10 DO11 Block Diagram N.C. N.C. LK J H G F E D C BA XVS VDDL VDDH VDDH VDDH VDDH TEST6 N.C. N.C. N.C. N.C. N.C. VSSH VSSH VSSH VSSH VSSL INCK TEST7 DCK VSSL VSSL VSSL VSSL VSSH VSSL Vcap2 Vcap1 DO0 / DATAP0 DO1 / DATAM0 XCLR VDDL VDDL VDDL VDDH2 VDDL VSSL VSSH DO2 / STRBP0 DO3 / STRBM0 XHS DO4 / STRBP1 DO5 / STRBM1 VSSL DO6 / DATAP1 DO7 / DATAM1 VSSL DO8 DO9 VDDM DO10 DO11 VDDM N.C. N.C. VSSL N.C. N.C. TEST3 VDDL VDDL SCK VDDM VDDH N.C. N.C. N.C. N.C. VSSH VSSM SDO VSSL VSSL VSSL VDDH SDI TEST2 XCE VCP VRLTEST5 TEST4 TEST1 VDDL VSSH VDDH XMASTER VDDL VDDL VSSL VSSL VSSH VDDH VDDH VSSM VSSM IMX122 TOP View Pin Configuration

No. Pin. No. I/O Analog/ Digital Symbol Description Remarks CMOS parallel LVDS serial N.C. N.C. Not connected. OPEN N.C. N.C. Not connected. OPEN

3 A3 TEST D TEST3 TEST 3 Test Low level fixed

4 A4 Power D VDDL VDDL 1.2 V power supply 5 A5 Power D VDDL VDDL 1.2 V power supply

6 A6 I D SCK SCK Serial I/F (Communication clock input)

7 A7 Power D VDDM VDDM 1.8 V power supply 8 A8 Power A VDDH V DDH 2.7 V power supply N.C. N.C. Not connected. OPEN A10 N.C. N.C. Not connected. OPEN N.C. N.C. Not connected. OPEN N.C. N.C. Not connected. OPEN 13 B3 GND D VSSL VSSL 1.2 V GND 14 B4 GND D VSSL VSSL 1.2 V GND 15 B5 GND D VSSL VSSL 1.2 V GND

16 B6 O D SDO SDO Serial I/F (Register value output)

17 B7 GND D VSSM VSSM 1.8 V GND 18 B8 GND A VSSH VSSH 2.7 V GND N.C. N.C. Not connected. OPEN B10 N.C. N.C. Not connected. OPEN

21 C1 O D DO10 TEST11 When CMOS output: Digital output

When LVDS output: Open

22 C2 O D DO11 TEST12 When CMOS output: Digital output

When LVDS output: Open 23 C3 Power D VDDM VDDM 1.8 V power supply 24 C4 GND D VSSL VSSL 1.2 V GND 25 C5 Power A VDDH V DDH 2.7 V power supply

26 C6 I D SDI SDI Serial I/F (Register value input)

27 C7 TEST D TEST2 TEST 2 Test Low level fixed

28 C8 I D XCE XCE Serial I/F (Communication enable)

29 C9 O A VCP VCP Connected to VRL

capacitor.

30 C10 I A VRL VRL Connected to VCP

capacitor.

31 D1 O D DO8 TEST9 When CMOS output: Digital output

When LVDS output: Open

32 D2 O D DO9 TEST10 When CMOS output: Digital output

When LVDS output: Open 33 D3 Power D VDDM VDDM 1.8 V power supply 34 D4 Power D VDDL VDDL 1.2 V power supply 35 D5 GND A VSSH VSSH 2.7 V GND 36 D6 Power A VDDH V DDH 2.7 V power supply 37 D7 I D XMASTER XMASTER Slave Mode: High / Master Mode: Low High:1.8 V Low:GND

38 D8 TEST D TEST1 TEST1 Test 10 kΩPull-Up

39 D9 TEST D TEST4 TEST4 Test OPEN

40 D10 TEST D TEST5 TEST5 Test OPEN

No. Pin. No. I/O Analog/ Digital Symbol Description Remarks CMOS parallel LVDS serial

41 E1 O D DO6 DATAP1

When CMOS output: Digital output When LVDS output: LVDS DATAP1 signal output of low power version

42 E2 O D DO7 DATAM1

When CMOS output: Digital output When LVDS output: LVDS DATAM1 signal output of low power version 43 E3 GND D VSSL VSSL 1.2 V GND 44 E8 GND D VSSM VSSM 1.8 V GND 45 E9 GND D VSSM VSSM 1.8 V GND 46 E10 GND A VDDH VDDH 2.7 V power supply

47 F1 O D DO4 STRBP1

When CMOS output: Digital output When LVDS output: LVDS strobeP1 signal output of low power version

48 F2 O D DO5 STRBM1

When CMOS output: Digital output When LVDS output: LVDS strobeM1 signal output of low power version 49 F3 GND D VSSL VSSL 1.2 V GND 50 F8 Power D VDDL VDDL 1.2 V power supply 51 F9 GND D VSSL VSSL 1.2 V GND 52 F10 Power A VDDH V DDH 2.7 V power supply

53 G1 O D DO2 STRBP0

When CMOS output: Digital output When LVDS output: LVDS strobeP0 signal output of low power version

54 G2 O D DO3 STRBM0

When CMOS output: Digital output When LVDS output: LVDS strobeM0 signal output of low power version

55 G3 I/O D XHS XHS Horizontal sync signal input/output

: Only input 56 G8 Power D VDDL VDDL 1.2 V power supply 57 G9 GND D VSSL VSSL 1.2 V GND 58 G10 GND A VSSH VSSH 2.7 V GND

59 H1 O D DO0 DATAP0

When CMOS output: Digital output When LVDS output: LVDS DATAP0 signal output of low power version

60 H2 O D DO1 DATAM0

When CMOS output: Digital output When LVDS output: LVDS DATAM0 signal output of low power version

61 H3 I D XCLR XCLR System clear

62 H4 Power D VDDL VDDL 1.2 V power supply 63 H5 Power D VDDL VDDL 1.2 V power supply 64 H6 Power D VDDL VDDL 1.2 V power supply 65 H7 Power A VDDH2 VDDH2 2.7 V power supply 66 H8 Power D VDDL VDDL 1.2 V power supply 67 H9 GND D VSSL VSSL 1.2 V GND 68 H10 GND A VSSH VSSH 2.7 V GND

69 J1 O D TEST7 TEST7 Test

70 J2 O D DCK TEST8 When CMOS output: clock output. When LVDS output: open 71 J3 GND D VSSL VSSL 1.2 V GND 72 J4 GND D VSSL VSSL 1.2 V GND 73 J5 GND D VSSL VSSL 1.2 V GND 74 J6 GND D VSSL VSSL 1.2 V GND 75 J7 GND A VSSH VSSH 2.7 V GND 76 J8 GND D VSSL VSSL 1.2 V GND

77 J9 TEST A Vcap2 Vcap2 Test

capacitor.

78 J10 TEST A Vcap1 Vcap1 Test

capacitor.

No. Pin. No. I/O Analog/ Digital Symbol Description Remarks CMOS parallel LVDS serial N.C. N.C. Not connected. OPEN N.C. N.C. Not connected. OPEN

81 K3 I D INCK INCK Master clock

82 K4 GND D VSSL VSSL 1.2 V GND 83 K5 GND A VSSH VSSH 2.7 V GND 84 K6 GND A VSSH VSSH 2.7 V GND 85 K7 GND A VSSH VSSH 2.7 V GND 86 K8 GND A VSSH VSSH 2.7 V GND N.C. N.C. Not connected. OPEN K10 N.C. N.C. Not connected. OPEN N.C. N.C. Not connected. OPEN N.C. N.C. Not connected. OPEN

91 L3 I/O D XVS XVS Horizontal sync signal input/output

Slave mode : Input , Master mode : Output When LVDS output : Only input 92 L4 GND D VDDL VDDL 1.2 V power supply 93 L5 Power A VDDH VDDH 2.7 V power supply 94 L6 Power A VDDH VDDH 2.7 V power supply 95 L7 Power A VDDH VDDH 2.7 V power supply 96 L8 Power A VDDH VDDH 2.7 V power supply

97 L9 TEST D TEST6 TEST6 Test OPEN

N.C. N.C. Not connected. OPEN

Electrical Characteristics

The electrical characteristics of this device is shown below. DC Characteristics Item Pin Symbol Conditions Min. Typ. Max. Unit Supply voltage Analog V DD H AV DD — 2.6 2.7 2.8 V Digital V DD M OV DD — 1.7 1.8 1.9 V V DD L DV DD — 1.1 1.2 1.3 V Digital input voltage XHS XVS XCLR INCK XMASTER XCE SDI SCK V IH XVS/XHS: In slave mode 0.8OV DD — — V V IL — — 0.2OV DD V Digital output voltage DO [11:0] DCK V OH CMOS output I OH = -4 mA OV DD 0.4 — — V V OL CMOS output I OL = 4 mA — — 0.4 V DATA0/1 STRB0/1 V CM LVDS output Terminating resistance: 100 Ω OV DD – 0.1 OV DD /2 OV DD + 0.1 V V OD 100 150 200 mV XHS XVS SDO V OH XVS/XHS: In master mode, CMOS output OV DD 0.4 — — V V OL — — 0.4 V LVDS Output V CM V OD LVDS + output LVDS - output

Item, conditions Pin Symbol Typ. Max. Unit Standard Luminous intensity Saturated luminous intensity Standard Luminous intensity Saturated Luminous intensity All-pixel mode Parallel CMOS-SDR output INCK = 54 MHz 10 bit/12 bit 19.64 frame/s V DD H IAV DD 36 36 46 46 mA V DD L IDV DD 34 43 46 52 V DD M IOV DD 25 5 31 8 All-pixel mode Serial LVDS-2ch output INCK = 54 MHz 10 bit/12 bit 19.64 frame/s V DD H IAV DD 36 36 46 46 mA V DD L IDV DD 36 45 50 54 V DD M IOV DD 12 12 18 18 HD1080 p mode Parallel CMOS-SDR output INCK = 37.125 MHz 10 bit/12 bit 30 frame/s V DD H IAV DD 36 36 46 46 mA V DD L IDV DD 36 49 47 58 V DD M IOV DD 33 5 42 8 HD1080 p mode Serial LVDS-2ch output INCK = 37.125 MHz 10 bit/12 bit 30 frame/s V DD H IAV DD 36 36 46 46 mA V DD L IDV DD 39 52 51 62 V DD M IOV DD 12 12 18 18 Standby current V DD H IAV DD _STB 3 47 μ A V DD L IDV DD _STB 400 2200 V DD M IOV DD _STB 143 Typ.: AV DD = 2.7 V, OV DD = 1.8 V, DV DD Max.: AV DD = 2.8 V, OV DD = 1.9 V, DV DD Standard luminous intensity: Luminous intensity at standard imaging condition I Saturated luminous intensity: Luminous intensity when the sensor is saturated Power Consumption Item, conditions Pin Symbol Typ. Max. Unit Standard Luminous intensity Saturated luminous intensity Standard Luminous intensity Saturated Luminous intensity All-pixel mode Parallel CMOS-SDR output INCK = 54 MHz 10 bit/12 bit 19.64 frame/s V DD H IAV DD 97.2 97.2 128.8 128.8 mW V DD L IDV DD 40.8 51.6 59.8 67.6 V DD M IOV DD 45.0 9.0 58.9 15.2 TOTAL PV DD 183.0 157.8 247.5 211.6 All-pixel mode Serial LVDS-2ch output INCK = 54 MHz 10 bit/12 bit 19.64 frame/s V DD H IAV DD 97.2 97.2 128.8 128.8 mW V DD L IDV DD 43.2 54.0 65.0 70.2 V DD M IOV DD 21.6 21.6 34.2 34.2 TOTAL PV DD 162 172.8 228.0 233.2 HD1080 p mode Parallel CMOS-SDR output INCK=37.125 MHz 10 bit/12 bit 30 frame/s V DD H IAV DD 97.2 97.2 128.8 128.8 mW V DD L IDV DD 43.2 58.8 61.1 75.4 V DD M IOV DD 59.4 9.0 79.8 15.2 TOTAL PV DD 199.8 165.0 269.7 219.4 HD1080 p mode Serial LVDS-2ch output INCK = 37.125 MHz 10 bit/12 bit 30 frame/s V DD H IAV DD 97.2 97.2 128.8 128.8 mW V DD L IDV DD 46.8 62.4 66.3 80.6 V DD M IOV DD 21.6 21.6 34.2 34.2 TOTAL PV DD 165.6 181.2 229.3 243.6 * The condition of measuring Typ. value and Max. value are the same as current consumption.

a) Master clock (INCK) INCK 0.8 × OVDD 0.2 × OVDD 0.5 × OVDD t WHINCK t WLINCK 1/f INCK t WP t P Duty Ratio = t WP / t P × 100 Item Symbol Min. Typ. Max. Unit Remarks INCK clock frequency f INCK 53 54 55 MHz INCK Low level width t WLINCK 6.5 — — ns INCK High level width t WHINCK 6.5 — — ns INCK clock duty — 45 50 55 % Defined with 0.5 × OV DD Item Symbol Min. Typ. Max. Unit Remarks INCK clock frequency f INCK 37.125 MHz INCK Low level width t WLINCK 10.3 — — ns INCK High level width t WHINCK 10.3 — — ns INCK clock duty — 45 50 55 % Defined with 0.5 × OV DD *1 The INCK fluctuation affects the frame rate. 37.125 MHz is the value of INCK for HD1080 p mode and the sensor does not operate with specified 30 frame/s except for typical value.

b) XVS and XHS Input Characteristics (In Slave Mode) 0.8 × OVDD 0.2 × OVDD XVS 0.8 × OVDD 0.2 × OVDD XHS t WLXVS t WLXHS t VHDLY 0.8 × OVDD 0.2 × OVDD XVS XHS t f t r INCK 0.8 × OVDD 0.2 × OVDD t VHSU t VHHLD Item Symbol Min. Typ. Max. Unit XVS fall time tf — — 5 ns XVS rise time tr — — 5 ns XHS fall time tf — — 5 ns XHS rise time tr — — 5 ns XVS, XHS input setup time t VHSU 0 — — ns XVS, XHS input hold time t VHHLD 5 — — ns XVS Low level pulse width t WLXVS 4 — 100 INCK XHS Low level pulse width t WLXHS 4 — 100 INCK XVS-XHS fall delay t VHDLY — — 1 INCK

c) XVS, XHS Output Characteristics (In Master Mode, CMOS Output) DCK 0.8 × OVDD 0.2 × OVDD 0.8 × OVDD 0.2 × OVDD XVS 0.8 × OVDD 0.2 × OVDD XHS t VFDLY t WLXVS t WLXHS t HFDLY (Load capacitance: 20 pF) Item Symbol Min. Typ. Max. Unit XVS Low level pulse width t WLXVS 1 1 8 H XHS Low level pulse width t WLXHS 6 6 128 DCK DCK-XVS fall delay t VFDLY –1 — 15 ns DCK-XHS fall delay t HFDLY –1 — 15 ns

d) Serial Communication (4-wire Serial) XCLR 0.8 × OVDD 0.2 × OVDD XCE 0.8 × OVDD 0.2 × OVDD SCK 0.8 × OVDD 0.2 × OVDD SDI 0.8 × OVDD 0.2 × OVDD SDO 0.8 × OVDD 0.2 × OVDD DATA DATA t WLXCLR t ENXCE t SUXCE 1/f SCK t SUSDI t HDSDI t HDSDO DATA t HDXCE t WLXCE t SUSDO (Output load capacitance: 20 pF) Item Symbol Min. Typ. Max. Unit SCK clock frequency f SCK — 13.5 28 MHz XCLR Low level pulse width t WLXCLR 500 — — ns XCE effective margin t ENXCE 100 — — ns XCE input setup time t SUXCE 20 — — ns XCE input hold time t HDXCE 20 — — ns XCE High level pulse width t WLXCE 20 — — ns SDI input setup time t SUSDI 10 — — ns SDI input hold time t HDSDI 10 — — ns SDO output setup time t SUSDO — — 25 ns SDO output hold time t HDSDO 0 — — ns

e) DCK and DO Output Characteristics (Parallel CMOS Output Mode) e-1) SDR Output (FRSEL = 1d) DCK (DCKDLY = 0d) DCK (DCKDLY = 1d) DO* 1/f DCK t SKMAXDOS t SKMINDOS 0.5×OV DD DATA 0.5×OV DD 0.5×OV DD (Output load capacitance: 20 pF) Item Symbol Min. Typ. Max. Unit DCK clock frequency f DCK — INCK — MHz DCK clock duty — 40 50 60 % Maximum skew between DCK and DO* t SKMAXDOS — — 2 ns Minimum skew between DCK and DO* t SKMINDOS — — 2 ns The DCK frequency is the same as that of INCK. It is 54 MHz for all-pixel mode or other modes and 37.125 MHz for HD720 p mode. e-2) DDR Output In-phase Output (DCKDLY = 0d) (FRSEL = 1d) DO* DCK 1/f DCK t SKMAXDOD t SKMINDOD DATA DATA t SKMAXDOD t SKMINDOD DATA 0.5×OV DD 0.5×OV DD (Output load capacitance: 20 pF) Item Symbol Min. Typ. Max. Unit DCK clock frequency f DCK — INCK/2 — MHz DCK clock duty — 40 50 60 % Maximum skew between DCK and DO* t SKMAXDOD — — 2 ns Minimum skew between DCK and DO* t SKMINDOD — — 2 ns

e-3) DDR Output 90 ° Phase Delay Output (DCKDLY = 1d) (FRSEL = 1d) DO* DCK 1/f DCK t SKMAXDOD t SKMINDOD DATA t SKMAXDOD t SKMINDOD 0.5×OV DD 0.5×OV DD (Output load capacitance: 20 pF) Item Symbol Min. Typ. Max. Unit DCK clock frequency f DCK — INCK/2 — MHz DCK clock duty — 40 50 60 % Maximum skew between DCK and DO* t SKMAXDOD — — 6.6 ns Minimum skew between DCK and DO* t SKMINDOD 3.2 — — ns

f) DATA/STROBE Output Characteristics (Serial LVDS Output Mode) Voa[0d] Vob[0d] Voa[1d] Vob[1d] Voa[0s] Vob[0s] Voa[1s] Vob[1s] t chdly t chcskew(min.) t chcskew(max.) tdatskew(min.) tdatskew(max.) tdatskew(min.) tdatskew(max.) Note) 1. Voa/Vob: Differential signals which are paired DATAM0 / DATAP0 DATAM1 / DATAP1 STRBM0 / STRBP0 STRBM1 / STRBP1 2. Characteristics in [ ] indicate the followings Figure (0/1): Output channel Alphabet (d/s): d: Data s: Strobe 3. T chcskew uses the cross point of Voa and Vob as a reference. The skew of STRB signal is set with the DATA clock as a reference in the diagram. Item Symbol Min. Typ. Max. Unit Skew between differential signal clocks t chcskew –400 — 400 ps Skew between different signals t datskew –250 — 250 ps Difference between data and strobe edges t chdly 1 — — bit *1 The offset of data output waveform edge and strobe output waveform are represented. The diagram above indicates the difference from data output edge to strobe output edge.

I/O Equivalent Circuit Diagram Equivalent circuit Symbol Equivalent circuit Symbol INCK XCLR TEST4 TEST5 TEST6 Vcap1 Vcap2 VRL VCP TEST2 DOx DCK XVS/XHS SDO SDI SCK XCE TEST1 TEST3 DATAPx DATAMx STRBPx STRBMx 1M Ω INCK V DD M V SS M : External pin XCLR V DD M V SS M V DD H1, 2 V SS H1, 2 Analog Output Schmitt Buffer V SS L1 V SS V SS H1, 2 VRL VCP TEST1 Pull-up V SS V SS V DD MV DD M TEST2 Pull-down V SS L1 V SS V DD M V DD M TEST3 V SS H1, 2 V DD M V SS M V DD M V SS M V DD M V SS M V DD M V SS M Digital I/O Digital output Digital input Digital output LVDS output P LVDS output M

Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics.) Relative response Wavelength [nm] 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 400 450 500 550 600 650 700 [Gr] [Gb] [R] [B]

Image Sensor Characteristics (VA DD = 2.7 V, OV DD = 1.8 V, DV DD = 1.2 V, Ta = 60 °C, All-pixel scan 12 bits 19.64 frame/s, Gain: 0 dB) Item Symbol Min. Typ. Max. Unit Measurement method Remarks G sensitivity Sg 1664 (370) 1911 (425) — Digit (mV) 1 1/30 s integration Sensitivity ratio Saturation signal Zone0-I Vsat01 3696 (822) — — Digit (mV)

3 Ta= 60 °C

Zone0-II’ Vsat2D 3651 (812) — — Digit (mV) Video signal shading Zone0-I SH01 — — 20 % Zone0-II’ SH2D — — 25 % Dark signal Vdt — — 0.67 (0.15) Digit (mV) 5 Ta = 60 °C, 1/30 s integration Dark signal shading ∆Vdt — — 0.67 (0.15) Digit (mV) 6 Ta = 60 °C, 1/30 s integration Line crawl R Lcr — — 6 % Line crawl B Lcb — — 6 % Lag Lag — — 0.5 % 8 *1 Conversion is executed with 1 digit = 0.890 mV for 10-bit output and 1 digit = 0.222 mV for 12-bit output. *2 The video signal shading is the measured value in the wafer status (including color filter) and does not include the seal gl ass characteristics. *3 See the Zone Definition of Video Signal Shading (diagram below) for Zone. Zone Definition of Video Signal Shading 1225 (V) 1984 (H) V H H V Zone 0, I Zone II, II’ Ignored region Effective pixel region

Image Sensor Characteristics Measurement Method Measurement Conditions In the following measurements, the device drive conditions are at the typical values of the bias conditions and clock voltage conditions. In the following measurements, spot pixels are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, which is taken as the value of the Gr/Gb channel signal output or the R/B channel signal output of the measurement system. Color Coding of this Image Sensor and Readout The primary color filters of this image sensor are arranged in the layout shown in the figure below. Gr and Gb represent the G signal on the same line as the R and B signals, respectively. The Gb signal and B signal lines and the R signal and Gr signal lines are output successively. Gb B Gb B RG rRG r Gb B Gb B RG rRG r Color Coding Diagram Definition of standard imaging conditions Standard imaging condition I: Use a pattern box (luminance: 706 cd/m color temperature of 3200 K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0 mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. Standard imaging condition II: Image a light source (color temperature of 3200 K) with a uniformity of brightness within 2 % at all angles. Use a testing standard lens with CM500S (t = 1.0 mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. Standard imaging condition III: Image a light source (color temperature of 3200 K) with a uniformity of brightness within 2 % at all angles. Use a testing standard lens (exit pupil distance -30 mm) with CM500S (t = 1.0 mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm.

1. Sensitivity Set the measurement condition to the standard imaging condition I. After setting the electronic shutter mode with a shutter speed of 1/100 s, measure the Gr and Gb signal outputs (VGr, VGb) at the center of the screen, and substitute the values into the following formula. Sg = (VGr + VGb)/2 × 100/30 [mV] 2. Sensitivity ratio Set the measurement condition to the standard imaging condition II. After adjusting the average value of the Gr and Gb signal outputs to 425 mV, measure the R signal output (VR [mV]), the Gr and Gb signal outputs (VGr, VGb [mV]) and the B signal output (VB [mV]) at the center of the screen in frame readout mode, and substitute the values into the following formulas. VG = (VGr + VGb)/2 Rr = VR/VG Rb = VB/VG 3. Saturation signal Set the measurement condition to t he standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with the average value of the Gr and Gb signal outputs, 425 mV, measure the average values of the Gr, Gb, R and B signal outputs. 4. Video signal shading Set the measurement condition to the standard imaging condition III. With the lens diaphragm at F2.8, adjust the luminous intensity so that the average value of the Gr and Gb signal outputs is 425 mV. Then measure the maximum value (Gmax [mV]) and the minimum value (Gmin [mV]) of the Gr and Gb signal outputs, and substitute the values into the following formula. SH = (Gmax – Gmin)/425 × 100 [%] 5. Dark signal With the device ambient temperature of 60 °C and the device in the light-obstructed state, divide the output difference between 1/30 s integration and 1/300 s integration by 0.9, and calculate the signal output converted to 1/30 s integration. Measure the average value of this output (Vdt [mV]). 6. Dark signal shading After the measurement item 5, measure the maximum value (Vdmax [mV]) and the minimum value (Vdmin [mV]) of the dark signal output, and substitute the values into the following formula. ∆Vdt = Vdmax – Vdmin [mV] 7. Line crawl Set the measurement condition to t he standard imaging condition II. After adjusting the average value of the Gr signal output to 400 mV, insert R and B filters and measure the difference between G signal lines ( ∆Glr, ∆Glb[mV]) as well as the average values of the G signal outputs (Gar, Gab). Substitute the values into the following formula. Lci = ( ∆Gli/Gai) × 100 [%] (i = r, b)

1. Lag Adjust the G signal output value generated by strobe light to 80 mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Glag), and substitute the value into the following formula. Lag = (Glag/80) × 100 [%] Glag (lag) VD Strobe light timing Output G signal output 80 mV

Setting Registers with Serial Communication Description of Setting Registers This sensor can write and read the setting values of the various registers shown in the Register Map by 3-wire serial communication. See the Register Map for the addresses and setting values to be set. The serial data input order is LSB-first transfer. The table below shows the various data types and descriptions. Type Description ChipID 02h: Write to the CID = 02h register 03h: Write to the CID = 03h register 82h: Read from the CID = 02h register 83h: Read from the CID = 03h register Address Designate the address according to the Register Map. When using a communication method that designates continuous addresses, the address is automatically incremented from the previously transmitted address. Data Input the setting values ac cording to the Register Map. Register Communication Timing Perform register communication within the 6H period after the falling edge of XVS. Register setting values are reflected at the following timing. When communication is performed during the communication period shown in the figure below, items noted as “V” in the “Reflection timing” column of the Register Map are output in the state with the setting value reflected in the N frame. However, note that although the integration time setting is reflected in the N frame, it is reflected to shutter control after N frame readout, so the setting value is reflected to the output in the N + 1 frame. Items that are reflected instantly are reflected at the timing when communication is performed. XVS XHS Communication period N frame N + 1 frame Register Reflection Timing

Follow the communication procedure below when writing registers. (1) Set XCE Low to enable the chip’s communication function. Serial data input is executed using SCK and SDI. (2) Transmit data in sync with SCK 1 bit at a time from the LSB using SDI. Transfer SDI in sync with the falling edge of SCK. (The data is loaded at the rising edge of SCK.) (3) Input the Chip ID (CID = 02h or 03h) to the first byte. If the Chip ID differs, subsequent data is ignored. (4) Input the start address to the second byte. The address is automatically incremented. (5) Input the data to the third and subsequent bytes. The data in the third byte is written to the register address designated by the second byte, and the register address is automatically incremented thereafter when writing the data for the fourth and subsequent bytes. Normal register data is loaded to the inside of the sensor and established in 8-bit units. (6) The register values starting from the register address designated by the second byte are output from the SDO pin. The register values before the write operation are output. The actual register values are the input data. (7) Set XCE High to end communication. Follow the communication procedure below when reading registers. (1) Set XCE Low to enable the chip’s communication function. Serial data input is executed using SCK and SDI. (2) Transmit data in sync with SCK 1 bit at a time from the LSB using SDI. Transfer SDI in sync with the falling edge of SCK. (The data is loaded at the rising edge of SCK.) (3) Input Chip ID (CID = 82h or 83h) to the first byte. If the Chip ID differs, subsequent data is ignored. (4) Input the start address to the second byte. The address is automatically incremented. (5) Input data to the third and subsequent bytes. Input dummy data in order to read the registers. The dummy data is not written to the registers. To read continuous data, input the necessary number of bytes of dummy data. (6) The register values starting from the register address designated by the second byte are output from the SDO pin. The input data is not written, so the actual register values are output. (7) Set XCE High to end communication. Note) Even when changing register setting values during imaging, communication should finish within the 6H communication period. When writing data to multiple registers with discontinuous addresses, access to undesired registers can be avoided by repeating the above procedure multiple times. The figures on the following page show examples of transmission.

Communication Timing to Registers with Continuous Addresses XCE SCK 01234567012345670123456701234567 01234567 SDI SDO 01234567 LSB MSB LSB MSB LSB MSB MSBLSB ChipID Address N Data N+1 Data N+2 Data LSB Reflection timing Communication Timing to Registers with Discontinuous Addresses XCE SCK SDI SDO LSB MSB LSB MSB LSB MSB MSBLSB ChipID ChipIDAddress N Data 012345670123456701234567 01234567 01234567 01234567 Reflection timing

ChipID: 02 Address Bit Register name Description Default value after reset Reflection timing By register By address 00h

0 STANDBY STANDBY control

0: Normal operation, 1: STANDBY 1 01h 1 Fixed to “0”. 0 2 Fixed to “0”. 0 3 Fixed to “0”. 0 TESTEN [1:0] Register write 0h: Invalid 3h: Valid Others: Invalid

0 Immediately

6 Fixed to “0”. 0 7 Fixed to “0”. 0 01h

0 VREVERSE

Vertical (V) scanning direction control 0: Normal 1: Inverted 00h V 1 Fixed to “0”. 0 2 Fixed to “0”. 0 3 Fixed to “0”. 0 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “0”. 0 02h MODE [3:0] Readout mode designation 0h: All pixels (2.3 M) 1h:HD720 p 2h: Window cropping 3h: 2 × 2 binning 4h: Vertical 1/2 subsampling Fh: HD1080 p Others: Invalid 00h V 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “0”. 0

Address Bit Register name Description Default value after reset Reflection timing By register By address 03h HMAX [13:0] LSB 044Ch 4Ch V In master mode Horizontal (H) direction clock number designation Default: All-pixel 10 bits 39.27 frame/s 04h 04h

5 MSB

6 Fixed to “0”. 0 7 Fixed to “0”. 0 05h VMAX [15:0] LSB 04E2h E2h V In master mode Vertical (V) direction line number designation Default: All-pixel 10 bits 39.27 frame/s 06h 04h

7 MSB

07h [7:0] Fixed to “00h” 00h 00h

Address Bit Register name Description Default value after reset Reflection timing By register By register 08h SHS1[15:0] LSB 0000h 00h V Integration time adjustment Designated in line units 09h 00h 0Ah [7:0] Fixed to “00h” 00h 00h 0Bh [7:0] Fixed to “00h” 00h 00h 0Ch [7:0] Fixed to “00h” 00h 00h 0Dh SPL[9:0] LSB 000h 00h V Integration time adjustment (Low-speed shutter) Designated in frame units 0Eh 00h

1 MSB

2 Fixed to “0”. 0 3 Fixed to “0”. 0 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “0”. 0

Address Bit Register name Description Default value after reset Reflection timing By register By register 0Fh SVS [9:0] LSB 000h 00h V Integration time adjustment (Low-speed shutter) Designated in frame units 10h 00h 2 Fixed to “0”. 0 3 Fixed to “0”. 0 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “0”. 0 11h FRSEL [2:0] Output data rate designation 0: 2 times INCK 1: Equal to INCK 2: 1/2 of INCK (2 × 2 binning mode only) 3: 1/4 of INCK (2 × 2 binning mode only) Others: Invalid 88h V OPORTSEL [1:0] Output system selection 0: Parallel CMOS SDR output 1: Parallel CMOS DDR output 2: Serial LVDS 1ch output 3: Serial LVDS 2ch output 1h Immediately M12BEN [1:0] The output resolution is set to 10 bit (2x2 binning mode only.) 0: disable 2:enable others: setting prohibited 0h V 7 Fixed to “0”.

1 Immediately

0 SSBRK Low-speed shutter forcible termination 0

1 ADRES AD gradation setting

0: 10 bits, 1: 12 bits 0 V 2 Fixed to “0”. 0 3 Fixed to “0”. 0 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “1”. 1 13h [7:0] Fixed to “40h”. 00h 00h Immediately

Address Bit Register name Description Default value after reset Reflection timing By register By register 14h WINPH [11:0] LSB 000h 00h V In window cropping mode Designation of upper left coordinate for cropping position (Horizontal position) 15h 00h

3 MSB

4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “0”. 0 16h WINPV [11:0] LSB 000h 00h V In window cropping mode Designation of upper left coordinate for cropping position (Vertical position) 17h 00h 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “0”. 0

Address Bit Register name Description Default value after reset Reflection timing By register By register 18h WINWH [11:0] LSB 7C0h C0h V In window cropping mode Cropping size designation (Horizontal direction) 19h 07h 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “0”. 0 1 Ah WINWV [11:0] LSB 4C9h C9h V In window cropping mode Cropping size designation (Vertical direction) 1Bh 04h 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “0”. 0 1Ch [7:0] Fixed to “50h” 50h 50h 1Dh [7:0] Fixed to “00h” 00h 00h

Address Bit Register name Description Default value after reset Reflection timing By register By register 1Eh GAIN [7:0] LSB 00h 00h V Gain setting 1Fh [7:0] Fixed to “31h”. 31h 31h 20h BLKLEVEL [8:0] LSB 03Ch 3Ch Immediately Black level offset value setting 21h MSB 00h 1 Fixed to “0”. 0 2 Fixed to “0”. 0 3 Fixed to “0”. 0 XHSLNG [1:0] XHS low level width setting 0h: 6 clk, 1h: 12 clk, 2h: 22 clk, 3h: 128 clk 0h Immediately 6 Fixed to “0”. 0 7 10BITA Setting registers for 10 bit. 0 Immediately 22h XVSLNG [2:0] XVS low level width setting. 0h: 1 line, 1h: 2line, 2h: 4line, 3h: 8 line, others: Invalid 00h Immediately 3 Fixed to “0”. 0 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “1”. 7 720PMODE Fixed to 1 for HD720 p mode. 0 V 23h to 26h [7:0] to [7:0] Do not communicate 27h [7:0] Fixed to “20”. 21h Immediately 28h to 2Bh [7:0] to [7:0] Do not communicate

Address Bit Register name Description Default value after reset Reflection timing By register By register 2Ch XMSTA Trigger for master mode operation start 0:Master mode operation start 1: Trigger standby 01h Immediately 1 Fixed to “0”. 0 2 Fixed to “0”. 0 3 Fixed to “0”. 0 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “0”. 0 2Dh 0 Fixed to “0”. 0 40h

1 DCKDLY

For SDR output ... 0: 0 °, 1: 180 ° For DDR output... 0: 0 °, 1: 90 ° 0 V

2 Fixed to “0” 0

3 BITSEL 10-bit output 2-bit shift

0: Left justified, 1: Right justified 0 V 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “1”. 1 7 Fixed to “0”. 0 2Eh to 3Ah [7:0] to [7:0] Do not communicate. 3Bh [7:0] SYNCCODE [7:0] Sync code setting E0h E0h V 3Ch to 79h [7:0] to [7:0] Do not communicate. 7Ah [7:0] 10BITB Setting registers for 10 bit. 00h 00h Immediately 7Bh [7:0] 10BITC Setting registers for 10 bit. 00h 00h Immediately 7Ch to 97h [7:0] to [7:0] Do not communicate.

Address Bit Register name Description Default value after reset Reflection timing By register By register 98h 10B1080 P [11:0] LSB 226h 26h Adjustment registers for each operation mode. 99h 02h 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “0”. 0 9Ah 12B1080 P [11:0] LSB 44Ch 4Ch Immediately Adjustment registers for each operation mode. 9Bh 04h 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “0”. 0

Address Bit Register name Description Default value after reset Reflection timing By register By register 9Ch to CDh [7:0] to [7:0] Do not communicate CEh PRES[6:0] LSB 16h 16h Immediately Adjustment registers for each operation mode.

6 MSB

7 Fixed to “0”. 0 CFh DRES LSB 082h 82h Immediately Adjustment registers for each operation mode. D0h

0 MSB 00h

1 Fixed to “0”. 0 2 Fixed to “0”. 0 3 Fixed to “0”. 0 4 Fixed to “0”. 0 5 Fixed to “0”. 0 6 Fixed to “0”. 0 7 Fixed to “0”. 0

ChipID: 03 Address Bit Register name Description Default value after reset Reflection timing By register By register 17h [7:0] Fixed to “0Dh” . 4Dh 4Dh Immediately *1 The STANDBY (Address 00h [0]) register is reflected at the following timings.

• When canceling standby mode: Reflected immediately
• When entering standby mode: Reflected immediately after the end of the frame during which the setting was made *2 The values must be changed from the default values, so initial setting after reset is required after power-on. Subsequent setting by communication is not needed unless the power is turned Off or the system is reset. *3 “V” in the “Reflection timing” column indicates that the setting value is reflected at the falling edge of the next XVS after the register communication is performed. *4 Do not perform communication to addresses not listed in the Register Map. Doing so may result in malfunction. However, other registers that require communication to addresses not listed above may be added, so addresses up to FFh should be supported for both CID = 02h and 03h.

The table below lists the operating modes available with this sensor. Drive mode Imaging conditions INCK [MHz] Frame rate [frame/s] Output Resolution [bit] Number of effective pixels Data width period [μs] H [pixels] V [lines] H [INCK] V [lines] All-pixel scan 54 19.64 10/12 1984 1225 2200 1250 40.74 39.27 10 1100 20.37 HD1080 p 37.125 15.00 10/12 1984 1105 2200 1125 59.26 25.00 10/12 1320 35.56 30.00 10/12 1100 29.63 HD720 p 37.125 30.00 10/12 1344 745 1650 750 44.44 60.00 10 825 22.22 Window cropping (UXGA) 54 14.985 10/12 1664 1225 2200 1638 40.74 29.97 10 1100 20.37 2 × 2 binning readout 54 14.985 10/12 992 612 4400 819 81.48 29.97 10/12 2200 40.74 Vertical 1/2 subsampling 54 29.97 10/12 1368 524 2200 819 40.74 59.94 10 1100 20.37 *1 The data width indicates the output sync signal period in master mode. In slave mode the data width is the input XVS and XHS clock interval. *2 In 2 × 2 binning readout mode, the pixel signals are converted to 10 bits and digitally added. The output gradation can be selected from 10 bits or 12 bits. Drive mode Imaging conditions Data rate INCK [MHz] Frame rate [frame/s] Output resolution [bit] Parallel CMOS output Serial LVDS output SDR DDR 1ch 2ch All-pixel scan 54 19.64 10/12 54 54 648 648 39.27 10 N/A 108 N/A 1296 HD1080 p 37.125 25.00 10/12 74.25 74.25 N/A 891 30.00 10/12 74.25 74.25 N/A 891 HD720 p 37.125 60.00 10 74.25 74.25 N/A 891 Window cropping (UXGA) 54 14.985 10/12 54 54 648 648 29.97 10 N/A 108 N/A 1296 2 × 2 binning readout 54 14.985 10/12 13.5 13.5 162 162 29.97 10/12 27 27 324 324 Vertical 1/2 sub sampling 54 29.97 10/12 54 54 648 648 59.94 10 N/A 108 N/A 1296

Sync Code (Parallel CMOS Output Mode) The sync code is added immediately before and after “dummy signal + OB signal + effective pixel data” and then output. The sync code is output in order of 1st, 2nd, 3rd and 4th. The fixed value is output for 1st to 3rd. (BLK: Blanking period) System delay 1st 2nd 3rd 4th SAV DATA EAV XHS System delay System delay DATA DATA DATA 1st 2nd 3rd 4th H.BLK H.BLK System delay XVS SAV (Invalid line) EAV (Invalid line) System delay System delay Dummy for communication H.BLK H.BLK H.BLK SAV (valid line) Frame information line System delay System delay H.OB/V.OB H.OB/V.OB H.OB/effective pixel System delay System delay EAV (Valid line) H.BLK H.BLK H.BLK H.BLK H.OB/effective pixel System delay H.BLK H.OB/effective pixel System delay H.BLK System delay V.BLK H.BLK System delay SAV (Invalid line) EAV (Invalid line) System delay System delay H.BLK H.BLK H.BLK Frame information line System delay System delay H.OB/V.OB H.BLK H.BLK SAV (Valid line) EAV (Valid line) SAV(Invalid line) SAV(Valid line) EAV(Valid line) EAV(Invalid line) Sync code 3FFh FFFh 000h 000h 000h 000h 200h 800h 3FFh FFFh 000h 000h 000h 000h 274h 9D0h 3FFh FFFh 000h 000h 000h 000h 2ACh AB0h 3FFh FFFh 000h 000h 000h 000h 2D8h B60h 10 bit 12 bit 10 bit 12 bit 10 bit 12 bit 10 bit 12 bit 1st code 2nd code 3rd code 4th code System delay H.BLK System delay H.BLK System delay H.BLK System delay System delay System delay H.BLK H.BLK H.BLK Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Sync Code Output Timing (Parallel CMOS Output)

Sync Code Output Timing (Parallel CMOS Output Mode) The sensor output signal passes through the internal circuits and is output with a latency time (system delay) relative to the horizontal sync signal. This system delay value is undefined for each line, so refer to the sync codes output from the sensor and perform synchronization. System delay SAV 1st code 2nd code 3rd code 4th code 1st code 2nd code 3rd code 4th code EAV 1234 ... Blanking XHS DCK DO[11:0]

Sync Code (Serial LVDS Output Mode) The sync code is added immediately before and after “dummy signal + OB signal + effective pixel data” and then output. The sync code is output in order of 1st, 2nd, 3rd and 4th. The fixed value is output for 1st to 3rd. (BLK: Blanking period) SOF System delay 1st 2nd 3rd 4th DATA XHS System delay System delay DATA DATA DATA 1st 2nd 3rd 4th H.BLK H.BLK System delay XVS SOD (Invalid line) EOD (Invalid line) System delay System delay H.BLK H.BLK H.BLK SOL (Valid line) System delay System delay H.OB/V.OB H.OB/V.OB H.OB/effective pixel System delay System delay EOL (Valid line) H.BLK H.BLK H.BLK H.BLK H.OB/effective pixel System delay H.BLK H.OB/effective pixel System delay H.BLK System delay V.BLK H.BLK System delay SOD (Invalid lind) EOD (Invalid line) System delay System delay H.BLK H.BLK H.BLK System delay System delay H.OB/V.OB H.BLK H.BLK SOL (Valid line) EOL (Valid line) SOD(Invalid line) Dummy start code EOD(Invalid line) Dummy end code Sync code 0Fh 00h 00h 80h 0Fh 00h 00h 88h 0Fh 00h 00h C8h Output 1st code 2nd code 3rd code 4th code System delay H.BLK System delay H.BLK System delay H.BLK System delay System delay System delay H.BLK H.BLK H.BLK H.OB/V.OB H.BLK System delay EOF H.OB/V.OB Frame information line SOF SOL(Valid line) Line start code 0Fh 00h 00h 00h DATA0 DATA1 0Fh 00h 00h C0h 0Fh 00h 00h 40h EOL(Valid line) Line end code 0Fh 00h 00h 08h 0Fh 00h 00h 48h SOF Frame start code 0Fh 00h 00h 10h 0Fh 00h 00h 50h EOF Frame end code 0Fh 00h 00h 18h 0Fh 00h 00h 58h Frame information line System delay H.BLK N/A xxh xxh xxh xxh * N/A : The minimum sensor output value is output. (Not 00h) N/A N/A DATA0 DATA1 DATA0 DATA1 DATA0 DATA1 DATA0 DATA1 DATA0 DATA1 DATA0/1 Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Sync Code 1 Output Timing (Serial LVDS Output)

H.BLK H.BLK System delay XVS System delay System delay H.BLK H.BLK H.BLK SOL (Valid line) System delay System delay H.OB/V.OB H.OB/V.OB H.OB/effective pixel System delay System delay EOL (Valid line) H.BLK H.BLK H.BLK H.BLK H.OB/effective pixel System delay H.BLK H.OB/effective pixel System delay H.BLK System delay V.BLK H.BLK System delay System delay System delay H.BLK H.BLK H.BLK System delay System delay H.OB/V.OB H.BLK H.BLK SOL EOL Sync code Output 1st code 2nd code 3rd code 4th code System delay H.BLK System delay H.BLK System delay H.BLK System delay System delay System delay H.BLK H.BLK H.BLK H.OB/V.OB H.BLK System delay SOF EOF H.OB/V.OB SOF SOL Line start code 0Fh 00h 00h 00h 0Fh 00h 00h 40h EOL Line end code 0Fh 00h 00h 08h 0Fh 00h 00h 48h SOF Frame start code 0Fh 00h 00h 10h 0Fh 00h 00h 50h EOF Frame end code 0Fh 00h 00h 18h 0Fh 00h 00h 58h System delay H.BLK N/A N/A N/A xxh xxh xxh xxh DATA0 DATA1 DATA0 DATA1 DATA0 DATA1 DATA0 DATA1 DATA0/1 Frame information line Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Frame information line Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication Dummy for communication * N/A : The minimum sensor output value is output. (Not 00h) Sync Code 2 Output Timing (Serial LVDS Output)

Sync Code Output Timing (Serial LVDS Output Mode) In serial LVDS output mode, the sync codes can be selected from sync code 1 that is output added to the effective signal line, and sync code 2 that are not added during the vertical blanking period. The figure below shows examples of the two sync code types. In addition, the sync codes are output in the order of 1st → 2nd → 3rd → 4th, and fixed values are output for the 1st to 3rd sync codes. (BLK: Blanking period) 8 bits of sync codes are added, from 1st to 4th, regardless of the number of output bits (10 bits or 12 bits). Codes supporting 1ch and 2ch are added in the 4th code and output. (See the figure below.) List of Sync Code Setting Registers Register details Initial value Setting value Function Register name ChipID Address Bit SYNCCODE 02h 3Bh [7:0] E0h E0h In parallel CMOS output mode 90h Operation using sync code 1 in serial LVDS output mode D0h Operation using sync code 2 in serial LVDS output mode When outputting SOL (Code when starting an effective line) DATA0 STROBE0 1st 0Fh 2nd 00h 3rd 00h 4th 00h OPB1 8b i t OPB2 8b i t OPB3 8b i t OPB4 8b i t OPB 1+2+3+4 8b i t OPB5 8b i t OPB1 8b i t OPB3 8b i t OPB5 8b i t OPB7 8b i t OPB 1+3+5+7 8b i t OPB9 8b i t OPB2 8b i t OPB4 8b i t OPB6 8b i t OPB8 8b i t OPB 2+4+6+8 8b i t OPB10 8b i t OPB1 8b i t OPB2 8b i t OPB 1+2 8b i t OPB 3+4 8b i t OPB3 8b i t OPB4 8b i t OPB1 8b i t OPB3 8b i t OPB 1+3 8b i t OPB 5+7 8b i t OPB5 8b i t OPB7 8b i t OPB2 8b i t OPB4 8b i t OPB 2+4 8b i t OPB 6+8 8b i t OPB6 8b i t OPB8 8b i t 1st 0Fh 2nd 00h 3rd 00h 4th 00h 1st 0Fh 2nd 00h 3rd 00h 4th 00h 1st 0Fh 2nd 00h 3rd 00h 4th 40h 1st 0Fh 2nd 00h 3rd 00h 4th 00h 1st 0Fh 2nd 00h 3rd 00h 4th 40h DATA0 STROBE0 DATA0 STROBE0 DATA1 STROBE1 DATA0 STROBE0 DATA1 STROBE1 RAW10 / 1ch RAW10 / 2ch RAW12 / 1ch RAW12 / 2ch Example of Sync Code Output

The all pixel signals of sensor are read. Register List of All-pixel Mode Setting Register details Initial value Setting value Function Register name Address Bit 10 bit 12 bit 19.64 [frame/s] 39.27 [frame/s] 19.64 [frame/s] MODE 02h [3:0] 00h 0h All-pixel mode HMAX 03h [7:0] 044Ch 0898h 044Ch 0898h Horizontal (H) direction clock number designation. 04h [5:0] VMAX 05h [7:0] 04E2h 04E2h Vertical (V) direction line number designation. 06h [7:0] FRSEL 11h [2:0] 0h 1h 0h 1h Output data rate designation. OPORTSEL [4:3] 1h N/A 0h Parallel CMOS SDR output. 1h 1h 1h Parallel CMOS DDR output N/A 2h Serial LVDS 1ch output. 3h 3h 3h Serial LVDS 2ch output. M12BEN [6:5] 0h 0h Output gradation setting ADRES 12h [1] 0h 0h 1h AD gradation setting. WINPH 14h [7:0] 000h 000h Designation of upper left coordinate for cropping position (Horizontal) 15h [3:0] WINPV 16h [7:0] 000h 000h Designation of upper left coordinate for cropping position (Vertical) 17h [3:0] WNIWH 18h [7:0] 7C0h 7C0h Cropping size designation (Horizontal) 19h [3:0] WINWV 1Ah [7:0] 4C9h 4C9h Cropping size designation (Vertical) 1Bh [3:0] 10BITA 21h [7] 0 1 0 Adjustments register for each operation mode. 720 P MODE 22h [7] 0 0 Sets in 720 p mode only. 10BITB 7Ah [7:0] 00h 40h 00h Adjustments register for each operation mode. 10BITC 7Bh [7:0] 00h 02h 00h 10B1080 P 98h [7:0] 226h 02h 00h 99h [3:0] 12B1080 P 9Ah [7:0] 44Ch 44Ch 9Bh [3:0] PRES CEh [6:0] 16h 16h 40h DRES CFh [7:0] 082h 082h 181h D0h [0]

G G B R G G B R G G B R G G B R G G B R G G B R G G B R G G B R 16 824 G G B R G G B R G G B R G G B R 82 4 4 1200 1920 HB XVS XHS 1250Number of lines in vertical direction Dummy for communication Frame information line OB side ignored area OB side ignored area Vertical direction effective OB Ignored area of effective pixel side Effective margin for color processing Effective margin for color processing Ignored area of effective pixel side Vertical blanking period Effective margin for color processing Ignored area of effective pixel side OB side ignored area Effective margin for color processing Ignored area of effective pixel side Sync code Sync code Horizontal blanking period System delay Recording pixel area Horizontal scan direction Horizontal scan direction 2200 Number of pixels In horizontal direction Pixel Array Image Drawing in All-pixel Scan Mode

1 Frame: 1250 [Lines]XVS

DCK (SDR) DCK (DDR) DO SD System delay 11 6 41 48 1968 1969 1976 1920 1977 2000 HB 2008 1H: 2200 [bits] Line No. during normal operation Line No. during inverted operation : Dummy for communicaiton : Frame information line : Ineffective OB : Effective OB : Blanking : Sync code : Ignored area of effective pixel side : Color processing margin : Recording pixel area * DCK is output asynchronously with INCK. * SD : Synstem delay * HB : Horizontal blanking Drive Timing Chart for Parallel CMOS Output in All-pixel Scan Mode

1 Frame: 1250 [Lines]

1H: 2200 [DATA] 26400 [bit] System Delay System Delay System Delay System Delay System Delay System Delay 4D A T A 32 bit

16 DATA

8 DATA

24 DATA

12 DATA

4 DATA

1920 DATA

960 DATA

2008 DATA 24064 bit

1008 DATA 12064 bit

2008 DATA 20064 bit

1008 DATA 10064 bit

Line No. during normal operation Line No. during inverted operation Sync code 1 Sync code 2 SOD/EOD(Invalid line) SOL/EOL(Valid line) SOL/EOL(Valid line) : Dummy for communicaiton : Frame information line : Ineffective OB : Effective OB : Blanking : Sync code : Ignored area of effective pixel side : Color processing margin : Recording pixel area Drive Timing Chart for Serial LVDS Output in All-pixel Scan Mode

The sensor signal is cut out with the angle of view for HD1080 p (1920 × 1080) and read. Input 37.125 MHz to INCK. Register List for HD1080 p Mode Setting Register details Initial value Setting value Function Register name Address Bit 10 bit 12 bit [frame/s] [frame/s] [frame/s] [frame/s] MODE 02h [3:0] 00h Fh HD1080 p mode HMAX 03h [7:0] 044Ch 0898h 044Ch 0898h 044Ch Horizontal (H) direction clock number designation 04h [5:0] VMAX 05h [7:0] 04E2h 0465h Vertical (V) direction line number designation 06h [7:0] FRSEL 11h [2:0] 0h 1h 0h 1h 0h Output data rate designation OPORTSEL [4:3] 1h 0h 0h 0h 0h Parallel CMOS SDR output 1h 1h 1h 1h Parallel CMOS DDR output N/A 2h N/A Serial LVDS 1ch output 3h 3h 3h 3h Serial LVDS 2ch output M12BEN [6:5] 0h 0h Output gradation setting ADRES 12h [1] 0h 0h 1h AD gradation setting WINPH 14h [7:0] 000h 000h Designation of upper left coordinate for cropping position (Horizontal) 15h [3:0] WINPV 16h [7:0] 000h 03Ch Designation of upper left coordinate for cropping position (Vertical) 17h [3:0] WNIWH 18h [7:0] 7C0h 7C0h Cropping size designation (Horizontal) 19h [3:0] WINWV 1Ah [7:0] 4C9h 451h Cropping size designation (Vertical) 1Bh [3:0] 10BITA 21h [7] 0 1 0 Adjustments register for each operation mode. 720PMODE 22h [7] 0 0 Sets in 720 p mode only. 10BITB 7Ah [7:0] 00h 40h 00h Adjustments register for each operation mode. 10BITC 7Bh [7:0] 00h 02h 00h 10B1080 P 98h [7:0] 226h 44Ch 226h 99h [3:0] 12B1080 P 9Ah [7:0] 44Ch 44Ch 226h 9Bh [3:0] PRES CEh [6:0] 16h 16h 40h 16h DRES CFh [7:0] 082h 082h 181h 082h D0h [0]

[frame/s] MODE 02h [3:0] 00h Fh HD1080 p mode HMAX 03h [7:0] 044Ch 0528h Horizontal (H) direction clock number designation. 04h [5:0] VMAX 05h [7:0] 04E2h 0465h Vertical (V) direction line number designation. 06h [7:0] FRSEL 11h [2:0] 0h 0h Output data rate designation. OPORTSEL [4:3] 1h 0h 0h Parallel CMOS SDR output. 1h 1h Parallel CMOS DDR output N/A N/A Serial LVDS 1ch output. 3h 3h Serial LVDS 2ch output. M12BEN [6:5] 0h 0h Output gradation setting ADRES 12h [1] 0h 0h 1h AD gradation setting. WINPH 14h [7:0] 000h 000h Designation of upper left coordinate for cropping position (Horizontal) 15h [3:0] WINPV 16h [7:0] 000h 03Ch Designation of upper left coordinate for cropping position (Vertical) 17h [3:0] WNIWH 18h [7:0] 7C0h 7C0h Cropping size designation (Horizontal) 19h [3:0] WINWV 1Ah [7:0] 4C9h 451h Cropping size designation (Vertical) 1Bh [3:0] 10BITA 21h [7] 0 1 0 Adjustments register for each operation mode. 720PMODE 22h [7] 0 0 Sets in 720 p mode only. 10BITB 7Ah [7:0] 00h 40h 00h Adjustments register for each operation mode. 10BITC 7Bh [7:0] 00h 02h 00h 10B1080 P 98h [7:0] 226h 294h 226h 99h [3:0] 12B1080 P 9Ah [7:0] 44Ch 44Ch 226h 9Bh [3:0] PRES CEh [6:0] 16h 40h 16h DRES CFh [7:0] 082h 181h 082h D0h [0]

G G B R G G B R G G B R G G B R G G B R G G B R G G B R G G B R 16 824 G G B R G G B R G G B R G G B R 82 4 4 1080 1920 HB XVS XHS 1125Number of lines in vertical direction Dummy for communication Frame information line OB side ignored area Vertical direction effective OB Ignored area of effective pixel side Effective margin for color processing Effective margin for color processing Ignored area of effective pixel side Vertical blanking period Effective margin for color processing Ignored area of effective pixel side OB side ignored area Effective margin for color processing Ignored area of effective pixel side Sync code Sync code Horizontal blanking period System delay Recording pixel area Horizontal scan direction Horizontal scan direction 2200 Number of pixels In horizontal direction Pixel Array Image Drawing in HD1080 p Mode

1 Frame: 1125 [Lines]XVS

DCK (SDR) DCK (DDR) DO SD System delay 11 6 41 48 1968 1969 1976 1920 1977 2000 HB 2008 1H: 2200 [bits] : Dummy for communicaiton : Frame information line : Ineffective OB : Effective OB : Blanking : Sync code : Ignored area of effective pixel side : Color processing margin : Recording pixel area * DCK is output asynchronously with INCK. * SD : Synstem delay * HB : Horizontal blanking Line No. during normal operation Line No. during inverted operation Drive Timing Chart for Parallel CMOS Output in HD1080 p Mode

SOD/EOD(Invalid line) 1234 1234 1241 1240 1239 1238 1237 1230 21 28 1229 29 30 1228 1228 1080 1229 1237 1241 1240 1239 1238 SOF SOF EOF EOF SOF

1 Frame: 1125 [Lines]

1H: 2200 [DATA] 26400 [bit] 1ch output RAW12 DATA0 STROBE0 System Delay 2ch output RAW12 DATA0 STROBE0 DATA1 STROBE1 1ch output RAW10 DATA0 STROBE0 System Delay System Delay System Delay 2ch output RAW10 DATA0 STROBE0 DATA1 STROBE1 System Delay System Delay 4D A T A 32 bit Line No. during normal operation Line No. during inverted operation Sync code 1 Sync code 2 SOL/EOL(Valid line) SOL/EOL(Valid line) : Dummy for communicaiton : Frame information line : Ineffective OB : Effective OB : Blanking : Sync code : Ignored area of effective pixel side : Color processing margin : Recording pixel area Drive Timing Chart for Serial LVDS Output in HD1080 p Mode

The sensor signal is cut out with the angle of view for HD720 p (1280 × 720) and read. However,set “1” to the register 720 P MODE (Address 22h [7] ) Input 37.125 MHz to INCK. Register List for HD720 p Mode Setting Register details Initial value Setting value Function Register name Address Bit 10 bit 12 bit [frame/s] [frame/s] [frame/s] MODE 02h [3:0] 00h 1h HD720 p mode HMAX 03h [7:0] 044Ch 0672h 0339h 0672h Horizontal (H) direction clock number designation. 04h [5:0] VMAX 05h [7:0] 04E2h 02EEh Vertical (V) direction line number designation. 06h [7:0] FRSEL 11h [2:0] 0h 1h 0h 1h Output data rate designation. OPORTSEL [4:3] 1h 0h 0h 0h Parallel CMOS SDR output. 1h 1h 1h Parallel CMOS DDR output N/A 2h Serial LVDS 1ch output. 3h 3h 3h Serial LVDS 2ch output. M12BEN [6:5] 0h 0h Output gradation setting ADRES 12h [1] 0h 0h 1h AD gradation setting. WINPH 14h [7:0] 000h 140h Designation of upper left coordinate for cropping position (Horizontal) 15h [3:0] WINPV 16h [7:0] 000h 0F0h Designation of upper left coordinate for cropping position (Vertical) 17h [3:0] WNIWH 18h [7:0] 7C0h 540h Cropping size designation (Horizontal) 19h [3:0] WINWV 1Ah [7:0] 4C9h 2E9h Cropping size designation (Vertical) 1Bh [3:0] 10BITA 21h [7] 0 1 0 Adjustments register for each operation mode. 720PMODE 22h [7] 0 1 Sets in 720 p mode only. 10BITB 7Ah [7:0] 00h 40h 00h Adjustments register for each operation mode. 10BITC 7Bh [7:0] 00h 02h 00h 10B1080 P 98h [7:0] 226h 226h 99h [3:0] 12B1080 P 9Ah [7:0] 44Ch 44Ch 9Bh [3:0] PRES CEh [6:0] 16h 00h 40h DRES CFh [7:0] 082h 000h 181h D0h [0]

G G B R G G B R G G B R G G B R G G B R G G B R G G B R G G B R 16 824 G G B R G G B R G G B R G G B R 82 4 4 720 1280 HB XVS XHS 750Number of lines in vertical direction Dummy for communication Frame information line OB side ignored area Vertical direction effective OB Ignored area of effective pixel side Effective margin for color processing Effective margin for color processing Ignored area of effective pixel side Effective margin for color processing Ignored area of effective pixel side OB side ignored area Effective margin for color processing Ignored area of effective pixel side Sync code Sync code Horizontal blanking period System delay Recording pixel area Horizontal scan direction Horizontal scan direction 1650 Number of pixels In horizontal direction Pixel Array Image Drawing in HD720 p Mode

1 Frame: 750 [Lines]XVS

DCK (SDR) DCK (DDR) DO SD System delay 11 6 337 360 361 368 3 6 9 1648 1649 1656 1920 1657 1680 HB 1368 1H: 1650 [bits] : Dummy for communicaiton : Frame information line : Ineffective OB : Effective OB : Blanking : Sync code : Ignored area of effective pixel side : Color processing margin : Recording pixel area * DCK is output asynchronously with INCK. * SD : Synstem delay * HB : Horizontal blanking Line No. during normal operation Line No. during inverted operation 990 268 992 266 992 266 993 265 990 268 Drive Timing Chart for Parallel CMOS Output in HD720 p Mode

SOD/EOD(Invalid line) 720 SOF SOF EOF EOF SOF

1 Frame: 750 [Lines]

1H: 1650 [DATA] 19800 [bit] 1ch output RAW12 DATA0 STROBE0 System Delay 2ch output RAW12 DATA0 STROBE0 DATA1 STROBE1 1ch output RAW10 DATA0 STROBE0 System Delay System Delay System Delay 2ch output RAW10 DATA0 STROBE0 DATA1 STROBE1 System Delay System Delay 4D A T A 32 bit

1280 DATA

640 DATA

1368 DATA 16384 bit

688 DATA 8224 bit

1368 DATA 13664 bit

688 DATA 6944 bit

Line No. during normal operation Line No. during inverted operation Sync code 1 Sync code 2 SOL/EOL(Valid line) SOL/EOL(Valid line) : Dummy for communicaiton : Frame information line : Ineffective OB : Effective OB : Blanking : Sync code : Ignored area of effective pixel side : Color processing margin : Recording pixel area Drive Timing Chart for Serial LVDS Output in HD720 p Mode

Sensor signals are cut out and read out in arbitrary positions. Use a fixed window cropping size and position. When changing the size or the position, set via the all-pixel scan mode. In addition, when returning to all-pixel scan mode after setting window cropping mode, return WINPH, WINPV, WINWH and WINWV to the initial values. List of Window Cropping Mode Setting Registers Register details Initial value Setting value Function Register name Address Bit 10 bit 12 bit 14.985 [frame/s] 29.97 [frame/s] 14.985 [frame/s] MODE 02h [3:0] 00h 2h Window cropping mode HMAX 03h [7:0] 044Ch 0898h 044Ch 0898h Horizontal (H) direction clock number designation. 04h [5:0] VMAX 05h [7:0] 04E2h 0666h Vertical (V) direction line number designation. 06h [7:0] FRSEL 11h [2:0] 0h 1h 0h 1h Output data rate designation. OPORTSEL [4:3] 1h N/A 0h Parallel CMOS SDR output. 1h 1h 1h Parallel CMOS DDR output N/A 2h Serial LVDS 1ch output. 3h 3h 3h Serial LVDS 2ch output. M12BEN [6:5] 0h 0h Output gradation setting. ADRES 12h [1] 0h 0h 1h AD gradation setting. WINPH 14h [7:0] 000h 0A0h(UXGA)* 1,3 Designation of upper left coordinate for cropping position (Horizontal) 15h [3:0] WINPV 16h [7:0] 000h 000h(UXGA)* 1,3 Designation of upper left coordinate for cropping position (Vertical) 17h [3:0] WNIWH 18h [7:0] 7C0h 680h(UXGA)* 2,3 Cropping size desi gnation (Horizontal) 19h [3:0] WINWV 1Ah [7:0] 4C9h 4C9h(UXGA)* 2,3 Cropping size designation (Vertical) 1Bh [3:0] 10BITA 21h [7] 0 1 0 Adjustments register for each operation mode. 720PMODE 22h [7] 0 0 Sets in 720 p mode only. Adjustments register for each operation mode. 10BITB 7Ah [7:0] 00h 40h 00h 10BITC 7Bh [7:0] 00h 02h 00h 10B1080 P 98h [7:0] 226h 44Ch 226h 99h [3:0] 12B1080 P 9Ah [7:0] 44Ch 44Ch 9Bh [3:0] PRES CEh [6:0] 16h 16h 40h DRES CFh [7:0] 082h 082h 181h D0h [0]

*1 The start position designation should satisfy the following conditions. WINPH + WINWH < 7C0h WINPV + WINWV < 4C9h *2 Set the cropping size setting values as follows. Horizontal direction: Multiple of 16 Vertical direction: Multiple of 4 *3 Return to the initial values when transitioning from window cropping mode to all-pixel scan mode. 390 SD 4 G G B R G G B R G G B R G G B R G G B R G G B R G G B R G G B R 16 824 G G B R G G B R G G B R G G B R 82 4 4 HB XVS XHS 1638Number of lines in vertical direction Dummy for communication Frame information line OB side ignored area OB side ignored area Vertical direction effective OB Ignored area of effective pixel side Effective margin for color processing Effective margin for color processing Ignored area of effective pixel side Vertical blanking period Effective margin for color processing Ignored area of effective pixel side OB side ignored area Effective margin for color processing Ignored area of effective pixel side Sync code Sync code Horizontal blanking period System delay Recording pixel area Horizontal scan direction Horizontal scan direction 2200 Number of pixels In horizontal direction WINWV WINWH Pixel Array Image Drawing in Window Cropping Mode

1 Frame: 1638 [Lines]XVS

DCK (SDR) DCK (DDR) DO SD System delay 11 6 HB 1H: 2200 [bits] WINWH WINWV WINWH + 24 1615-(WINWV) Line No. during normal operation Line No. during inverted operation : Dummy for communicaiton : Frame information line : Ineffective OB : Effective OB : Blanking : Sync code : Ignored area of effective pixel side : Color processing margin : Recording pixel area * DCK is output asynchronously with INCK. * SD : Synstem delay. * HB : Horizontal blanking. Drive Timing Chart for Parallel CMOS Output in Window Cropping Mode SOD 1234 1234 13 14 15 16 13 14 15 16 SOF SOF EOF EOF SOF

1 Frame: 1638 [Lines]

1H: 2200 [DATA] 26400 [bit] System Delay System Delay System Delay System Delay System Delay System Delay 4D A T A 32 bit (WINWH + 24) DATA (WINWH * 12 + 256) bit 26400 bit (WINWH / 2 + 16) DATA (WINWH / 2 * 12 + 160) bit 13200 bit 26400 bit 13200 bit WINWV 1615 - WINWV (WINWH + 24) DATA (WINWH * 10 + 224) bit (WINWH / 2 + 16) DATA (WINWH / 2 * 10 + 144) bit : Dummy for communicaiton : Frame information line : Ineffective OB : Effective OB : Blanking : Sync code : Ignored area of effective pixel side : Color processing margin : Recording pixel area 1ch output RAW12 DATA0 STROBE0 2ch output RAW12 DATA0 STROBE0 DATA1 STROBE1 1ch output RAW10 DATA0 STROBE0 2ch output RAW10 DATA0 STROBE0 DATA1 STROBE1 SOD/EOD(Invalid line) Line No. during normal operation Line No. during inverted operation Sync code 1 Sync code 2 SOL/EOL(Valid line) SOL/EOL(Valid line) Drive Timing Chart for Serial LVDS Output in Window Cropping Mode

2 × 2 Binning Readout Mode Sensor signals are read out by binning of 2 vertical pixels and 2 horizontal pixels. Note) The pixel signals are A/D converted to 10 bits, and 12-bit output is performed by digital binning of 4 same-color pixels. List of 2 × 2 Binning Readout Mode Setting Registers Register details Initial value Setting value Function Register name Address Bit 10 bit 12 bit 14.985 [frame/s] 29.97 [frame/s] 14.985 [frame/s] 29.97 [frame/s] MODE 02h [3:0] 00h 3h All-pixel mode HMAX 03h [7:0] 044Ch 1130h 0898h 1130h 0898h Horizontal (H) direction clock number designation. 04h [5:0] VMAX 05h [7:0] 04E2h 0333h Vertical (V) direction line number designation. 06h [7:0] FRSEL 11h [2:0] 0h 3h 2h 3h 2h Output data rate designation. OPORTSEL [4:3] 1h 0h 0h 0h 0h Parallel CMOS SDR output. 1h 1h 1h 1h Parallel CMOS DDR output 2h 2h 2h 2h Serial LVDS 1ch output. 3h 3h 3h 3h Serial LVDS 2ch output. M12BEN [6:5] 0h 2h 0h Output gradation setting ADRES 12h [1] 0h 0h AD gradation setting. WINPH 14h [7:0] 000h 000h Designation of upper left coordinate for cropping position (Horizontal) 15h [3:0] WINPV 16h [7:0] 000h 000h Designation of upper left coordinate for cropping position (Vertical) 17h [3:0] WNIWH 18h [7:0] 7C0h 7C0h Cropping size designation (Horizontal) 19h [3:0] WINWV 1Ah [7:0] 4C9h 4C9h Cropping size designation (Vertical) 1Bh [3:0] 10BITA 21h [7] 0 1 0 Adjustments register for each operation mode. 720PMODE 22h [7] 0 0 Sets in 720 p mode only. 10BITB 7Ah [7:0] 00h 40h 00h Adjustments register for each operation mode. 10BITC 7Bh [7:0] 00h 02h 00h 10B1080 P 98h [7:0] 226h 44Ch 226h 44Ch 226h 99h [3:0] 12B1080 P 9Ah [7:0] 44Ch 44Ch 9Bh [3:0] PRES CEh [6:0] 16h 16h DRES CFh [7:0] 082h 082h D0h [0]

G G B R G G B R G G B R G G B R 8 412 G G B R G G B R G G B R G G B R 41 2 4 600 960 HB XVS XHS 819Number of lines in vertical direction Dummy for communication Frame information line OB side ignored area OB side ignored area Vertical direction effective OB Ignored area of effective pixel side Effective margin for color processing Effective margin for color processing Ignored area of effective pixel side Vertical blanking period Effective margin for color processing Ignored area of effective pixel side OB side ignored area Effective margin for color processing Ignored area of effective pixel side Sync code Sync code Horizontal blanking period System delay Recording pixel area Horizontal scan direction Horizontal scan direction 1100 Number of pixels In horizontal direction G G B R G G B R G G B R G G B R Pixel Array Image Drawing in 2 × 2 Binning Readout Mode 31 6 43 48 1968 1971 1976 1979 2000 15 16 1239 1238 1227 1226 30 27 31 32 1228 1240 1239 XVS 13 14 15 16 13 14 19 20 1241 1240 1229 29 30 1228 1226 600 1238 1237 192 XHS DCK (SDR) DCK (DDR) DO SD System delay 11 4 41 46 1966 1969 1974 960 1977 1998 HB 1008 1H: 1100 [bits]

1 Frame: 819 [Lines]

: Dummy for communicaiton : Frame information line : Ineffective OB : Effective OB : Blanking : Sync code : Ignored area of effective pixel side : Color processing margin : Recording pixel area * DCK is output asynchronously with INCK. * SD : Synstem delay * HB : Horizontal blanking Line No. during normal operation Line No. during inverted operation Drive Timing Chart for Parallel CMOS Output in 2 × 2 Binning Readout Mode

6 DATA

1H: 1100 [DATA] 13200 [bit] System Delay System Delay System Delay System Delay System Delay System Delay 4D A T A 32 bit

2 DATA

480 DATA

508 DATA 6064 bit

508 DATA 5064 bit

SOD/EOD(Invalid line) Line No. during normal operation Line No. during inverted operation Sync code 1 Sync code 2 SOL/EOL(Valid line) SOL/EOL(Valid line) 1ch output RAW12 DATA0 STROBE0 2ch output RAW12 DATA0 STROBE0 DATA1 STROBE1 1ch output RAW10 DATA0 STROBE0 2ch output RAW10 DATA0 STROBE0 DATA1 STROBE1 : Dummy for communicaiton : Frame information line : Ineffective OB : Effective OB : Blanking : Sync code : Ignored area of effective pixel side : Color processing margin : Recording pixel area Drive Timing Chart for Serial LVDS Output in 2 × 2 Binning Readout Mode

Vertical 1/2 Subsampling Mode The sensor signal is read by eliminating it in vertical direction. Register List of Vertical 1/2 Subsampling Mode Setting Register details Initial value Setting value Function Register name Address bit 10 bit 12 bit 29.97 [frame/s] 59.94 [frame/s] 29.97 [frame/s] MODE 02h [3:0] 00h 4h Vertical 1/2 subsampling mode HMAX 03h [7:0] 044Ch 0898h 044Ch 0898h Horizontal (H) direction clock number designation 04h [5:0] VMAX 05h [7:0] 04E2h 0333h Vertical (V) direction line number designation 06h [7:0] FRSEL 11h [2:0] 0h 1h 0h 1h Output data rate designation OPORTSEL [4:3] 1h N/A 0h Parallel CMOS SDR output 1h 1h 1h Parallel CMOS DDR output N/A 2h Serial LVDS 1ch output 3h 3h 3h Serial LVDS 2ch output M12BEN [6:5] 0h 0h Output gradation setting ADRES 12h [1] 0h 0h 1h AD gradation setting WINPH 14h [7:0] 000h 000h Designation of upper left coordinate for cropping position (Horizontal) 15h [3:0] WINPV 16h [7:0] 000h 000h Designation of upper left coordinate for cropping position (Vertical) 17h [3:0] WNIWH 18h [7:0] 7C0h 7C0h Cropping size designation (Horizontal) 19h [3:0] WINWV 1Ah [7:0] 4C9h 4C9h Cropping size designation (Vertical) 1Bh [3:0] 10BITA 21h [7] 0 1 0 Adjustments register for each operation mode. 720PMODE 22h [7] 0 0 Sets in 720 p mode only. 10BITB 7Ah [7:0] 00h 40h 00h Adjustments register for each operation mode. 10BITC 7Bh [7:0] 00h 02h 00h 10B1080 P 98h [7:0] 226h 44Ch 226h 99h [3:0] 12B1080 P 9Ah [7:0] 44Ch 44Ch 9Bh [3:0] PRES CEh [6:0] 16h 16h 40h DRES CFh [7:0] 082h 082h 181h D0h [0]

G G B R G G B R G G B R G G B R G G B R G G B R G G B R G G B R 16 824 G G B R G G B R G G B R G G B R 82 4 4 600 1920 HB XVS XHS 819Number of lines in vertical direction Dummy for communication Frame information line OB side ignored area OB side ignored area Vertical direction effective OB Ignored area of effective pixel side Effective margin for color processing Effective margin for color processing Ignored area of effective pixel side Vertical blanking period Effective margin for color processing Ignored area of effective pixel side OB side ignored area Effective margin for color processing Ignored area of effective pixel side Sync code Sync code Horizontal blanking period System delay Recording pixel area Horizontal scan direction Horizontal scan direction 2200 Number of pixels In horizontal direction Pixel Array Image Drawing in Vertical 1/2 Subsampling Mode

1 Frame: 819 [Lines]XVS

DCK (SDR) DCK (DDR) DO SD System delay 11 6 41 48 1968 1969 1976 1920 1977 2000 HB 2008 1H: 2200 [bits] 1237 1236 1232 1229 1237 191 1233 : Dummy for communicaiton : Frame information line : Ineffective OB : Effective OB : Blanking : Sync code : Ignored area of effective pixel side : Color processing margin : Recording pixel area * DCK is output asynchronously with INCK. * SD : Synstem delay * HB : Horizontal blanking Line No. during normal operation Line No. during inverted operation Drive Timing Chart for Parallel CMOS Output in Vertical 1/2 Subsampling Mode

1H: 2200 [DATA] 26400 [bit] System Delay System Delay System Delay System Delay System Delay System Delay 4D A T A 32 bit : Dummy for communicaiton : Frame information line : Ineffective OB : Effective OB : Blanking : Sync code : Ignored area of effective pixel side : Color processing margin : Recording pixel area 1ch output RAW12 DATA0 STROBE0 2ch output RAW12 DATA0 STROBE0 DATA1 STROBE1 1ch output RAW10 DATA0 STROBE0 2ch output RAW10 DATA0 STROBE0 DATA1 STROBE1 SOD/EOD(Invalid line) Line No. during normal operation Line No. during inverted operation Sync code 1 Sync code 2 SOL/EOL(Valid line) SOL/EOL(Valid line) Drive Timing Chart for Serial LVDS Output in Vertical 1/2 Subsampling Mode

Description of Various Functions Standby mode This sensor stops its operation and goes into standby mode which reduces the power consumption by writing “1” to the standby control register STANDBY (address 00h, Bit [0]). (Standby mode immediately after power-on and reset) Standby mode is reflected after V. OB after the set frame. Write to register is possible because the serial communication function operates even in standby mode. Set the STANDBY register to “0” to cancel standby mode. The standby cancel is immediately reflected from the communication. List of Standby Mode Setting Register details Initial value Setting value Status Remarks Register name Address Bit Digital circuit Analog circuit STANDBY 00h [0] 1 (Standby) Stop Stop Register communication is executed even in standby mode.

0 Operate Operate

SOD/EOD(Invalid line) SOF SOF EOF EOF Front OB Ignored area of effective pixel side Standby Standby setting STANDBY=0 XVS Sync code 1 Sync code 2 Output data SOL/EOL (Valid line) SOL/EOL (Valid linde) SOD/EOD(Invalid line) SOF SOF EOF EOF Front OB Standby Standby cancel STANDBY = 1 XVS SOL/EOL (Valid line) SOL/EOL (Valid line) SOD/EOD SOF Ignored area of effective pixel side Color processing margin Color processing margin Recommended Recording pixel area Blanking Ignored area of effective pixel side Ignored area of effective pixel side Color processing margin Color processing margin Recommended Recording pixel area Blanking Sync code 1 Sync code 2 Output data >220 µs Standby Mode Change Timing

Slave Mode and Master Mode The sensor can be switched between slave mode and master mode. The switching is made by the XMASTER pin. Set the XMSTA register (address 2Ch [0]) to “0” in order to start the operation after setting to master mode. In addition, set the count number of sync signal in vertical direction by the VMAX register (address 05h [7:0], 06h [7:0]) and the clock number in horizontal direction by the HMAX register (address 03h [7:0], 04h [5:0]). See the description of Operation Mode for details of drive mode. List of Slave and Master Mode Setting (e.g. All pixels 19.64 frame/s) Pin name Pin processing Operation mode Remarks XMASTER pin Low fixed Master Mode High: 1.8 V Low: GND High fixed Slave Mode Description of register Initial value Setting value Status Remarks Register name Address Bit Master Mode XMSTA 2Ch [0] 1

0 Master operation start The master operation

starts by setting to 0.

1 Master operation ready

XHSLNG 21h [5:4] 0 See the diagram. XHS width designated (XVS reference output) XVSLNG 22h [2:0] 0 XVS width designated VMAX 05h [7:0] 4E2h See the each item in Operation Mode. Line number per frame designated 06h [7:0] HMAX 03h [7:0] 44Ch Clock number per frame designated 04h [5:0]

The signal of horizontal sync signal XHS is set by the XHSLNG register. The output has system delay from the XHS fall to effective data (sync code) output. DCK DO[11:0] SAV 1st 2nd 3rd 4th 1st 2nd 3rd 4th 12345 EAV System delay 67 9 8 6c l k 12 clk 22 clk 128 clk XHSLNG = 0h XHSLNG = 1h XHSLNG = 2h XHSLNG = 3h List of XHS Pulse Width Setting XVSLNG Selection The signal of vertical sync signal XVS is set. List of XVS Pulse Width Setting

The Programmable Gain Control (PGC) of this device consists of the analog block and digital block. The total of analog gain and digital gain can be set up to 42 dB by the GAIN register (address 1Eh [7:0]) setting. See the List of Gain Setting Register Value for Each Register. 0.0 3.0 6.0 9.0 12.0 15.0 18.0 21.0 24.0 27.0 30.0 33.0 36.0 39.0 42.0 Gain [dB] Register setting value [Hex] Analog Gain Analog + Digital Gain List of PGC Register Register details Initial value Setting value Remarks Register name Address Bit Min. Max. GAIN 1Eh [7:0] 00h 00h 8Ch See the next page.

List of Gain Setting Register Value Gain [dB] GAIN [7:0] Gain [dB] GAIN [7:0] Gain [dB] GAIN [7:0] 0.0 0h 14.1 2Fh 28.2 5Eh 0.3 1h 14.4 30h 28.5 5Fh 0.6 2h 14.7 31h 28.8 60h 0.9 3h 15.0 32h 29.1 61h 1.2 4h 15.3 33h 29.4 62h 1.5 5h 15.6 34h 29.7 63h 1.8 6h 15.9 35h 30.0 64h 2.1 7h 16.2 36h 30.3 65h 2.4 8h 16.5 37h 30.6 66h 2.7 9h 16.8 38h 30.9 67h 3.0 Ah 17.1 39h 31.2 68h 3.3 Bh 17.4 3Ah 31.5 69h 3.6 Ch 17.7 3Bh 31.8 6Ah 3.9 Dh 18.0 3Ch 32.1 6Bh 4.2 Eh 18.3 3Dh 32.4 6Ch 4.5 Fh 18.6 3Eh 32.7 6Dh 4.8 10h 18.9 3Fh 33.0 6Eh 5.1 11h 19.2 40h 33.3 6Fh 5.4 12h 19.5 41h 33.6 70h 5.7 13h 19.8 42h 33.9 71h 6.0 14h 20.1 43h 34.2 72h 6.3 15h 20.4 44h 34.5 73h 6.6 16h 20.7 45h 34.8 74h 6.9 17h 21.0 46h 35.1 75h 7.2 18h 21.3 47h 35.4 76h 7.5 19h 21.6 48h 35.7 77h 7.8 1Ah 21.9 49h 36.0 78h 8.1 1Bh 22.2 4Ah 36.3 79h 8.4 1Ch 22.5 4Bh 36.6 7Ah 8.7 1Dh 22.8 4Ch 36.9 7Bh 9.0 1Eh 23.1 4Dh 37.2 7Ch 9.3 1Fh 23.4 4Eh 37.5 7Dh 9.6 20h 23.7 4Fh 37.8 7Eh 9.9 21h 24.0 50h 38.1 7Fh 10.2 22h 24.3 51h 38.4 80h 10.5 23h 24.6 52h 38.7 81h 10.8 24h 24.9 53h 39.0 82h 11.1 25h 25.2 54h 39.3 83h 11.4 26h 25.5 55h 39.6 84h 11.7 27h 25.8 56h 39.9 85h 12.0 28h 26.1 57h 40.2 86h 12.3 29h 26.4 58h 40.5 87h 12.6 2Ah 26.7 59h 40.8 88h 12.9 2Bh 27.0 5Ah 41.1 89h 13.2 2Ch 27.3 5Bh 41.4 8Ah 13.5 2Dh 27.6 5Ch 41.7 8Bh 13.8 2Eh 27.9 5Dh 42.0 8Ch

Black Level Adjustment Function The black level offset (offset variable range: 03Ch to 1FFh) can be added relative to the data in which the digital gain modulation was performed by the BLKLEVEL register (address: 20h [7:0], 21h [0]). When the BLKLEVEL setting is increased by 1 LSB, the black level is increased by 1 LSB. Use with values shown below is recommended. 10-bit output: 3Ch (60d) 12-bit output: F0h (240d) List of Black Level Adjustment Register Register details Initial value Setting value Register name Address Bit Min. Max. BLKLEVEL 20h [7:0] 03Ch 03Ch 1FFh 21h [0]

Vertical Normal Operation and Inverted Drive The sensor readout direction (normal/inverted) in vertical direction can be switched by the VREVERSE (address 01h [0]) register setting. See the item of “Drive mode” for the order of readout lines in normal and inverted modes. One invalid frame is generated when reading immediately after the readout direction change in order to switch the normal operation and inversion between frames. List of Vertical Drive Direction Setting Register Register details Initial value Setting value Register name Address Bit Normal Inverted VREVERSE 01h [0] 0 0 1 V (+) H (+) A1-Pin V (+) H (+) L1-Pin A10-PinL10-Pin A1-PinL1-Pin A10-PinL10-Pin In normal drive In inverted drive (Chip outline) (Chip outline) Normal and Inverted Drive Outline in Vertical Direction

Shutter and Integration Time Settings This sensor has a variable electronic shutter function that can control the integration time in line units. In addition, this sensor performs rolling shutter operation in which electronic shutter and readout operation are performed sequentially for each line. Note) For integration time control, an image which reflects the setting is output from the frame after the setting changes. Example of Integration Time Setting The sensor's integration time is obtained by the following formula. Integration time = 1 frame period × (SVS + 1 - SPL) - (SHS1) × (1H period) - t OFFSET (However, SVS > SPL) Note) 1. The frame period is determined by the input X VS when the sensor is operating in slave mode, or the register VMAX value in master mode. The frame period is designated in 1H units, so the time is determined by (Number of lines × 1H period). 2. See “Drive Modes” for the 1H period. 3. t OFFSET is the integration time error. Substitute the value below in the formula of integration time. Operation mode t OFFSET [H] All-pixel scan mode HD1080 p mode (10 bit-15 frame/s, 10 bit-30 frame/s, 12 bit-15 frame/s) Window cropping mode Vertical 1/2 subsampling mode 0.3 HD1080 p mode (12 bit 30 frame/s) 2 x 2 binning mode 0.1 In this item, the shutter operation and integration time are shown as in the figure below with the time sequence on the horizontal axis and the vertical address on the vertical axis. For simplification, shutter and readout operation are noted in line units. Readout timing (valid) Shutter timing Integration time Blanking Frame information line SOF (Start of frame) EOF (End of frame) SOD (Start of dummy) SOL (Start of line) Time base XVS Nf r a m e Nf r a m e N + 1 frame N + 1 frame lines Last line Last-1 line Last-2 line 1 line 2 line 3 line 4 line Chip Top side Chip bottom side Sensor Output Dummy/blanking Effective signal Dummy/blanking Effective signal Sync code 1 Sync code 2 Image Drawing of Shutter Operation

Normal Exposure Operation (Controlling the Integration Time in 1H Units) The integration time can be controlled by varying the electronic shutter timing. In the electronic shutter settings, the integration time is controlled by the SHS1 register (address: 08h [7:0], 09h [7:0]). Set SHS1 to a value between 0 and (Number of lines per frame - 1). When the sensor is operating in slave mode, the number of lines per frame is determined by the XVS interval (number of lines), using the input XHS interval as the line unit. When the sensor is operating in master mode, the number of lines per frame is determined by the VMAX register (address: 05h [7:0], 06h [7:0]). The number of lines per frame varies according to the drive mode. Registers Used to Set the Integration Time in 1H Units Register details Initial value Description Register name Address Bit SHS1 08h [7:0] 0000h Sets the shutter sweep time. 09h [7:0] VMAX 05h [7:0] 04E2h Sets the number of lines per frame (only in master mode). See “Operating Modes” for the setting value in each mode. 06h [7:0] V-BLK χ SOF (Start of frame) EOF (End of frame) SOD (Start of dummy) SOL/EOL Integration timeReadout timing (Valid) Readout timing (Invalid) Shutter timing Register reflection timing Time base XVS Sync code 1 Sync code 2 lines SHS1= SHS1 set to α Frame2 Integration time χ Frame3 Integration time α Frame4 Integration time α Frame5 Integration time α Frame2 Frame1 V-BLK Output timing V-BLK Frame3 V-BLK Frame4 V-BLK Frame5 V-BLK Image Drawing of Integration Time Control within a Frame

Long Exposure Operation (Control by Expanding the Number of Lines per Frame) Long exposure operation can be performed by lengthening the frame period. When the sensor is operating in slave mode, this is done by lengthening the input vertical sync signal (XVS) pulse interval. When the sensor is operating in master mode, it is done by designating a larger register VMAX (address: 05h [7:0], 06h [7:0]) value compared to normal operation. Likewise, in slave mode the integration time can be increased by lengthening the input XVS signal pulse interval. When the integration time is extended by increasing the number of lines, the rear V blanking increases by an equivalent amount. The maximum VMAX and SHS1 values are 65535d. When the number of lines per frame is set to the maximum value, the integration time in all-pixel scan mode at 19.64 frame/s is approximately 2.7 s. When set to a number of V lines or more than that noted for each readout drive mode, the imaging characteristics are not guaranteed during long exposure operation. V-BLK SOF (Start of frame) EOF (End of frame) SOD (Start of dummy) SOL/EOL Integration timeReadout timing (Valid) Readout timing (Invalid) Shutter timing Register reflection timing Time base XVS Sync code 1 Sync code 2 lines SHS1= VMAX set to1500 α Frame2 Integration time α Frame3 Integration time α Frame2 Frame1 V-BLK Output timing V-BLK Frame3 V-BLK Frame4 VMAX=1250 α Frame4 Integration time V-BLK Frame5 α Frame5 Integration time Image Drawing of Long Exposure Time Control by Adjusting the Frame Period

Long Exposure Operation (Controlling the Integration Time in Frame Units) When setting a long exposure that extends the integration time to one frame or more, set the SVS register (address: 06h [7:0], 07h [1:0]) to the value of (Number of integration frames - 1). In addition, the frame in which the shutter operates is designated by the SPL register (address: 0Dh [7:0], 0Eh [1:0]). To further adjust the integration time in 1H units within the frame set by SPL, set the SHS1 register. However, note that performing long integration causes the readout timing and the setting reflection timing to be eliminated according to the value set by SVS, so the frame rate drops. The blanking signal is output in data corresponding to the drop in the frame rate. This description is for the settings in master mode. In slave mode, long integration is set by eliminating the input vertical sync signal (XVS) pulse. When set so that SVS < SPL, the SPL setting value is ignored, and the signal is stored for the number of frames designated by SVS. Set SHS1 to a value between 0 and (Number of lines per frame - 7). During long exposure operation, register communication is also reflected at the eliminated timing. To forcibly end operation partway, use the shutter break function. The imaging characteristics are not guaranteed during long exposure operation that performs integration for two frames or more. Registers Used to Set the Integration Time in Frame Units Register details Initial value Description Register name Address Bit SSBRK 1Bh [0] 1h Shutter break function Set both SVS and SPL to “0” simultaneously with this setting. SVS 07h [7:0] 000h Designates the number of integration frames. Integration time = Setting value + 1 frame 08h [1:0] SPL 0Dh [7:0] 000h Designates the number of sweep frames. 0Eh [1:0] SHS1 08h [7:0] 0000h Sets the shutter sweep time. Note) When SVS is set to more than 1h, SHS1 is limited to less than VMAX-7. 09h [7:0] * Integration time control is reflected to the next readout frame after the frame during which the setting was made. V-BLK χ SOF (Start of frame) EOF (End of frame) SOD (Start of dummy) SOL/EOL Integration timeReadout timing (Valid) Readout timing (Invalid) Shutter timing Register reflection timing Time base XVS Sync code 1 Sync code 2 lines SHS1= SHS1 set to α Frame2 Integration time χ SPL1 Frame3 Integration time α Frame2 Frame1 V-BLK Output timing V-BLK Frame3 V-BLK SVS = 2 SPL1 = 1 SVS = 2 Image Drawing of Long Exposure Control in Frame Units

Example of Integration Time Setting The example of register setting for controlling the integration time is shown below. Example of Integration Time Setting (in all-pixel mode, t OFFSET =0.3H) Operation Sensor setting (Register) Integration time VMAX* SVS SPL SHS1 Normal frame rate 1250 0 0 1249 0.7H period 1248 1.7H period : : N (1250 – N – 0.3) H period : : 1 1248.7H period 0 1249.7H period Long-time exposure operation (control by expanding the number of lines per frame) 1251 0 0 0 1250.7H period 1252 1251.7H period : : M N (M – N – 0.3) H period : : : Long-time exposure operation (integration time control in frame units) 1250 N (2499.7 – N) H period 2 (3269.7 – N) H period : : V {(V + 1) × VMAX – N – 0.3} H period : : (12499.7 – N) H period 1 (11249.7 – N) H period 2 (9999.7 – N) H period : : L {VMAX × (10 – L) – N – 0.3} H period : : V L {VMAX × (V + 1 – L) – N – 0.3} H period * In sensor master mode. XHS interval to be input in slave mode. * The SHS1 setting value (N) is set to the VMAX value (M) of -7 to 0.

When changing the integration time setting before the next reflection timing (readout timing) during long integration operation, the setting can be reflected at the normal XVS timing (when the register SVS is set to “0h”) by setting the SSBRK register (address: 12h [0]) to “01h”. The timing at which the SSBRK register is reflected conforms to the frame sequence before SVS is set. V-BLK χ SOF (Start of frame) EOF (End of frame) SOD (Start of dummy) SOL/EOL Integration timeReadout timing (Valid) Readout timing (Invalid) Shutter timing Register reflection timing Time base XVS Sync code 1 Sync code 2 lines SHS1= Frame2 Integration time χ Frame3 Integration time Frame2 Frame1 V-BLK Output timing V-BLK V-BLK SVS = 2 A Set to long exposureExposure setting at point A χ Frame3 V-BLK χ XVS Sync code 1 Sync code 2 lines SHS1= Frame2 Integration time χ Frame3 Integration time Frame2 Frame1 V-BLK Output timing V-BLK V-BLK SVS = 2 χ Frame3 SSBRK = 1 * Frame3 becomes an invalid frame The readout and communication periods become valid in the frame when the SSBRK register is changed from “0d” to “1d”. Output timing changed by shutter break Image Drawing of Shutter Break Function Depending on the value set when long integration operation starts (point “A” on the time base), the scheduled output can be stopped partway and settings can be changed as shown in the figure above. In this case, readout occurs in the frame when the SSBRK register is transmitted, and the signal stored up to that point is output. In this case the signal output in the frame when SSBRK is set becomes an invalid signal. In addition, perform communication at the next communication timing to return the SSBRK register to “0d”.

β Frame4 Integration time β SOF (Start of frame) EOF (End of frame) SOD (Start of dummy) SOL/EOL Integration timeReadout timing (Valid) Readout timing (Invalid) Shutter timing Register reflection timing Time base XVS Sync code 1 Sync code 2 Frame1 V-BLK Output timing A Set to long exposureExposure setting at point A line V-BLK SSBRK = 0d, SVS = 4d SPL = 2d, SHS1 = α SVS=4 Frame2 V-BLK SPL = 2 α Frame2 Integration time Sync code 1 Sync code 2 Frame1 V-BLK Output timing line V-BLK SVS = 4 Frame3 V-BLK α Frame2 Integration time Frame2 SPL = 2 XVS Frame3 Integration time B SSBRK=1d V-BLK * Frame2 becomes an invalid frame Long exposure stopped 1 C Long exposure stopped 2 When SSBRK = 1d is transmitted at point B and long exposure is performed again When SSBRK = 1d is transmitted at point C but long exposure is not performed thereafter Sync code 1 Sync code 2 XVS SSBRK = 1d, SVS = 0d SPL = 0d SHS1 = β SPL = 2 α Frame2 Integration time Frame3 Integration time β Frame1 V-BLK Frame2 V-BLK Frame3 V-BLK Frame4 V-BLK V-BLK Frame6 Integration time β Frame5 Integration time Frame5 V-BLK Frame6 * Frame2 becomes an invalid frame Output timing Example Showing Application of the Shutter Break Function When the SVS and SPL register values are left unchanged after the shutter break, readout is performed and then long integration starts again. To stop long integration with shutter break, the SVS and SPL register values must both be set to “0d” during the communication period of the frame during which shutter break is performed.

Output Signal Interface Control This sensor supports the following output formats. See “Image Data Output Format” for the data rate. Shaded areas in the figure indicate invalid data with regards to the AC characteristics. See “AC Characteristics” for details. Parallel CMOS SDR Output DCK DCKDLY = 0h High level = OV DD Low level = GND DCK DCKDLY = 1h High level = OV DD Low level = GND DO[11:0] High level = OV DD Low level = GND Valid data N Valid data N+1 Valid data N+2 Example of Pin Waveform in CMOS 1-port SDR Output Mode The sensor signal is output in sync with the falling edge of the data clock (DCK). (When DCKDLY is set to “0h”) Output in sync with the rising edge is possible by setting DCKDLY to “1h”. Parallel CMOS DDR Output DCK DCKDLY = 0h High level = OV DD Low level = GND DCK DCKDLY = 1h High level = OV DD Low level = GND DO[11:0] High level = OV DD Low level = GND Valid data N Valid data N+1 Valid data N+2 Example of Pin Waveform in CMOS 1-port DDR Output Mode The sensor signal is output in sync with both rising and falling edges of the data clock (DCK). (When DCKDLY is set to “0h”) Output can be performed with the DCK phase shifted by 90 ° relative to the data by setting DCKDLY to “1h”.

Serial LVDS uses a different format depending on whether the output gradation is 10 bits or 12 bits. The data is divided into a DATA line and a STROBE line, and is output on 1 channel or divided into 2 channels. IMX122 DATAP0 (DO0) / DATAM0 (DO1) Sync code (Ch1) [11:4] [11:4] [11:4] [11:4] [11:4] [11:4] P0[3:0] P1[3:0] P2[3:0] P3[3:0] P4[3:0] P5[3:0] STRBP0 (DO2) / STRBM0 (DO3) IMX122 DATAP0 (DO0) / DATAM0 (DO1) Sync code (Ch1) [9:2] [9:2] [9:2] [9:2] [9:2] STRBP0 (DO2) / STRBM0 (DO3) [9:2] [9:2] P0[1:0] P1[1:0] P2[1:0] P3[1:0] IMX122 DATAP0 (DO0) / DATAM0 (DO1) DATAP1 (DO6) / DATAM1 (DO7) Sync code (Ch1) [11:4] [11:4] [11:4] [11:4] P0[3:0] P2[3:0] P7[3:0] P4[3:0] Sync code (Ch2) [11:4] [11:4] [11:4] [11:4] P1[3:0] P6[3:0] P5[3:0] STRBP0 (DO2) / STRBM0 (DO3) STRBP1 (DO4) / STRBM1 (DO5) IMX122 DATAP0 (DO0) / DATAM0 (DO1) DATAP1 (DO6) / DATAM1 (DO7) Sync code (Ch1) [9:2] [9:2] [9:2] [9:2] [9:0] Sync code (Ch2) [9:2] [9:2] [9:2] P1[1:0] STRBP0 (DO2) / STRBM0 (DO3) STRBP1 (DO4) / STRBM1 (DO5) P3[1:0] P5[1:0] P7[1:0] P0[1:0] P2[1:0] P4[1:0] P6[1:0] [9:2] A) 1ch-RAW12 (12 bit) B) 1ch-RAW10 (10 bit) C) 2ch-RAW12 (12 bit) D) 2ch-RAW10 (10 bit) Strobe signal Strobe signal Strobe signal 0 Strobe signal 1 Strobe generation Strobe generation Strobe generation Strobe generation Strobe signal 0 Strobe signal 1 List of Serial LVDS Output Formats

XOR (Exclusive OR) Reception timing signal STROBE DATA The STROBE signal inverts when the DATA signal does not change. DATA-Strobe Method LVDS output uses the DATA-Strobe method. The DATA signal outputs the output data in binary format, but the STROBE signal performs toggle operation when the DATA signal does not change (0 → 0, 1 → 1). The signal switching timing is obtained by taking the XOR (exclusive OR) of the DATA and STROBE signals. Data is output LSB first at both the rising and falling edges of the waveform obtained by the XOR operation. Example: When outputting 01h, 12h, 23h and 34h in order DATA 01h 12h 23h 34h STROBE Output sequence Output Formats and Setting Methods Register details Initial value Setting value Description Register name Address Bit OPORTSEL 11h [4:3] 0

0 Parallel CMOS output, SDR output

1 Parallel CMOS output, DDR output

2 Serial LVDS 1ch output

3 Serial LVDS 2ch output

ADRES 12h [1] 0

0 In parallel CMOS output mode: 10-bit output

In serial LVDS output mode: 10-bit RAW10 output

1 In parallel CMOS output mode: 12-bit output

In serial LVDS output mode: 12-bit RAW12 output DCKDLY 2Dh [1] 0 In CMOS SDR output mode: Output in sync with the falling edge In CMOS DDR output mode: Output in sync with the edge (0 °) In LVDS output mode: Setting invalid In CMOS SDR output mode: Output in sync with the rising edge In CMOS DDR output mode: Output with the phase delayed by 90 ° In LVDS output mode: Setting invalid

The output gradation of this sensor can be switched to 10 bits or 12 bits. However, the output gradation is fixed for some drive modes. In parallel CMOS output mode, the output 10 bits or 12 bits are assigned to 10 pins or 12 pins, respectively. When set to 10 bits, the data is output from DO11 to DO2, and the unused pins are fixed Low. Bit Assignment for Each Output Gradation DO pin Output bit assignment 10 bit 12 bit DO [11] DO [9] DO [11] DO [10] DO [8] DO [10] DO [9] DO [7] DO [9] DO [8] DO [6] DO [8] DO [7] DO [5] DO [7] DO [6] DO [4] DO [6] DO [5] DO [3] DO [5] DO [4] DO [2] DO [4] DO [3] DO [1] DO [3] DO [2] DO [0] DO [2] DO [1] Fixed to “0” DO [1] DO [0] Fixed to “0” DO [0] In serial LVDS output mode, output uses the RAW10 format when the sensor gradation is 10 bits, or the RAW12 format when the sensor gradation is 12 bits. P0 P1 P2 P3 [4 ] [5] [6] [7] [8] [9] [1 0] [1 1] [4] [5] [6] [7] [8] [9] [1 0] [1 1] [0] [1] [2] [3 ] [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [4] [5] [6] [7] [8] [9] [0] [1] [2 ] [3] [0] [1 ] [2] [3] [4] [5 ] [6] [7] [8] [9] [2] [3 ] [4 ] [5] [6] [7] [8] [9] [2 ] [3] [0] [1] [0 ] [1] [4 ] [5] [6] [7] [8] [9] [1 0] [1 1] [4] [5] [6] [7 ] [8] [9] [1 0] [1 1] → RAW12 Format → RAW10 Format ... ... Example of RAW12 and RAW10 Format Output Output Range Output method Output gradation Output range Minimum value Maximum value Parallel CMOS output 10 bit 000h 3FEh 12 bit 000h FFEh Serial LVDS output 10 bit 004h 3FFh 12 bit 010h FFFh The range of the minimum and maximum values of the output data differs in parallel CMOS output mode and serial LVDS output mode. In parallel CMOS output mode, the output pins do not go to “All 1” except for the sync code. In serial LVDS output mode, the sensor signal may go to “All 1”, but not to “All 0”.

When changing the drive mode during sensor drive operation, first set the sensor to all-pixel scan mode, and then set it again to the desired drive mode. The table below shows the number of invalid frames generated by transition between the various modes. Data is output from sensor during the invalid frame period, but the output values may not reflect the integration time or may not be uniform on the screen, or a partially saturated image may be output. Number of Invalid Frames Generated during Mode Transitions Mode transition Number of invalid frames All-pixel scan mode Window cropping mode All-pixel scan mode 2 × 2 binning mode All-pixel scan mode Vertical 1/2 subsampling mode All-pixel scan mode All-pixel scan mode, vertical value inversion Window cropping mode All-pixel scan mode 2 × 2 binning mode All-pixel scan mode Vertical 1/2 subsampling mode All-pixel scan mode All-pixel scan mode, vertical value inversion All-pixel scan mode Note) When transitioning from window cropping mode to all-pixel scan mode, return the cropping range setting registers WINWH and WINWV to the initial values (7C0h, 4C9h). V-BLK SOF (Start of frame) EOF (End of frame) SOD (Start of dummy) SOL/EOL Readout timing Register reflection timing Time base XVS Sync code 1 Sync code 2 lines HMAX(only in master mode) VMAX(only in master mode) FRSEL MODE Frame N Frame N-1 V-BLK Output timing V-BLK Frame N+1 V-BLK Frame N+2 Valid frame Invalid frame Valid frame Valid frame *When changing the drive mode also changes the frame period , the number of invalid frames is counted according to the frame period after the change . Invalid Frame Generation Timing

Follow the sequence below to turn on the power supplies. 1. Turn on the power supplies so that the power supplies rise in order of 1.2 V power supply (DV DD ) →

1.8 V power supply (OV

) → 2.7 V power supply (AV DD ). In addition, all power supplies should finish rising within 200 ms. 2. Start master clock (INCK) input after turning on the power supplies. 3. The register values are undefined immediately after power-on, so the system must be cleared. Hold XCLR at Low level for 500 ns or more after all the power supplies have finished rising. (The register values after a system clear are the default values.) In addition, hold XCE at High level during this period. The XCE rise timing differs according to the 1.8 V power supply (OV DD ), so hold XCE at High level until INCK is input. The system clear is applied by setting XCLR to High level. However, the master clock needs to stabilize before setting the XCLR pin to High level. 4. Make the sensor settings by register communication after the system clear. A period of 100 ns or more should be provided after setting XCLR High before inputting the communication enable signal XCE.

2.7 V power supply (AV

200 ms＜

1.2 V power supply (DV

0 ns＞ 500 ns＞ t LOW * Wait for the clock to stabilize before setting XCLR High. 100 ns＞ t XCE XCLR XCE Depend on the 1.8 V power supply rise XVS XHS Hi-Z * In slave mode, hold the high impedance state until the power supplies have finished rising . Power-on Sequence

Turn Off the power supplies so that the power supplies fall in order of 2.7 V power supply (AV DD ) → 1.8 V power supply (OV DD ) → 1.2 V power supply (DV DD ). In addition, all power supplies should finish falling within 200 ms. Set each digital input pin (INCK, XCE, SCK, SDI, XCLR, XMASTER, XVS, XHS) to 0 V or high impedance before the 1.8 V power supply (OV DD ) falls.

The initial setting flow chart of sensor is shown below. The initial setting should be made after the sensor reset immediately after the power-on. See the items of the operation description shown in “Remarks” for control method. Fh Master Mode Slave Mode XMASTER 0h 1h Register OPORTSEL 3hRegister TESTEN Register MODE WINPV WINPH WINWV WINWH HD1080p Register VREVERSE 00h 01h Register ADRES 00h 01h 10 bit 12 bit CMOS logic (only DDR)

108 Mpixel/s

648 Mbps

Slave Mode: XHS/XVS = Input Master Mode: XHS/XVS = Output 00h 01h 0° 90° Register DCKDLY CMOS Logic SDR Input INCK = 37.125 MHz in HD1080p mode. FRSEL = 0: 74.25 Mpixel/s FRSEL = 1: 37.125 Mpixel/s 00h 01h 0hRegister STANDBY xxRegister Initial setting 2h 3h Master Mode 12B1080P PRES DRES Register 00h 02h 02h CMOS logic

54 Mpixel/s

324 Mbps

(Only for 2x2 addition) CMOS logic

27 Mpixel/s

162 Mbps

(Only for 2x2 addition) CMOS logic

13.5 Mpixel/s

81 Mbps

Window setting Window setting Window cropping 2x2 addition Vertical 1/2 elimination See “Drive mode” See “Output Signal Interface Control” and “Drive mode” for drive mode. Output resolution, each description of data rate and combination of setting . Turn the power supply on according to the power -on sequence. Connect XVS or XHS according to the operation mode . Set according to the output resolution and the frame rate . Scan direction Normal Inverted Output resolution See “Shutter and Storage Time Setting”. See “Gain Adjustment Function”. See “Black Level Adjustment Function”. Operation Mode See “Slave Mode and Master Mode”. Storage time setting Sensor internal gain setting Black level (effective OB) setting: In master mode, the operation starts by changing the XMSTA register from 01h (initial value) to 00h. Standby mode cancel Register which is set after the power -on (See the Register map.) Setting end Data rate HD720p Window setting

Serial Communication Period after Sensor Reset Slave mode The communication period is set at the timing shown below for the sensor initial settings immediately after power-on. In slave mode, the vertical and horizontal sync signals (XVS, XHS) become valid only from the falling edges 100 ns or more after sensor reset (after XCLR is set Low). The 6H serial communication period is from the falling edge of the first valid XVS to the sixth XHS falling edge thereafter. Note) XVS and XHS signals input when XCLR is Low are ignored. At this time the sensor is in standby mode until the next XVS signal. Register communication is possible in standby mode. INCK XCLR XVS XHS SCK t WLXCLR 500 ns 1H 2H 3H 4H 5H 6H t VHHLD 5n s t VHSU 0n s XCE t ENXCE 100 ns t SUXCE 20ns 0n s 100 ns Hi-Z Hi-Z t VHSU 0n s t VHHLD 5n s t HDXCE 20 ns 220μs Communication period Power-on Communication Period after Sensor Reset in Slave Mode

In master mode, the HMAX register (address 03h [7:0], 04h [5:0]) initial value is “44Ch” and the VMAX register (address 05h [7:4], 06h [7:0]) initial value is “4E2h”, so both XVS and XHS are output at these initial setting V and H widths until the setting values are reflected 6H later. When the VMAX and HMAX registers are set to arbitrary values by serial communication at the initial setting, and the master mode start register XMSTA (address 26h [0]) setting is changed from “1” to “0”, XVS and XHS start output according to the set values from the 7th H after the register settings are reflected. However, when VMAX and HMAX are set during the standby period, XVS and XHS are output according to the set values after standby is canceled. V-blanking V-blanking INCK XCLR XVS XHS SCK t WLXCLR 500 ns 1H 2H 3H 4H 5H 6H t HFDLY 15 ns t VFDLY 15 ns XCE t ENXCE 100 ns 0n s SOF t HDXCE 20 ns SOF t SUXCE 20 ns XVS and XHS start output when the XMSTA register setting is changed from “1” to “0”. In addition, the XVS and XHS pulse intervals are set by the VMAX and HMAX registers, respectivery. SOD (invalid line) SOD (valid line) Power-on Communication Period after Sensor Reset in Master Mode

1.2 V 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF VDDM VSSM Digital power supply 1.8 V 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF VDDH VSSH Analog power supply 2.7 V 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF F10 E10 0.1 uF 1 uF H10 G10 0.1 uF 1 uF 0.1 uF 1 uF 0.1 uF 1 uF GND AVDD AVDD DVDD DVDD OVDD OVDD Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

10 kΩ XMASTER VCP VRL C10 1 uF GND 10 uF GND 0.22 uF GND OVDD OVDD 10 kΩ 10 kΩ Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

Parallel CMOS output Serial LVDS output 100 Ω 100 Ω 100 Ω 100 Ω OPEN OPEN OPEN OPEN OPEN DATA0 STRB0 STRB1 DATA1 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same

(VA DD = 2.7 V, OV DD = 1.8 V, DV DD = 1.2 V, Ta = 60 °C, 30 frame/s, Gain: 0 dB) Type of distortion Level Maximum distorted pixels in each zone Measurement method Remarks 0 to II’ Effective OB III Ineffective OB Black or white pixels at high light 30 % ≤ D 17 No evaluation criteria applied 1 White pixels in the dark 5.6 mV ≤ D 200 No evaluation criteria applied

2 Ta = 60 °C

D ≤ 649 mV 0 No evaluation criteria applied 3 Note) 1. Zone is specified based on all-pixel drive mode. 3. See the Spot Pixel Pattern Specifications for the specifications in which white pixel and black pixel are close. Zone Definition OB side ignored area ZoneIII ZoneII' ZoneII ZoneI Zone0 (2000, 16) (2000, 1241) (1976, 1238) (1900, 1176) (1752, 1116) (1316, 936) 180 616 616 180 436 148 76 2424 76 148 43616 (1, 1) (41, 5) (1976, 12) (17, 17) (41, 21) (117, 81) (265, 141) (701, 321) OB side ignored area Vertical (V) direction effective OB (V.OB)

Notice on White Pixels Specifications After delivery inspection of CMOS image sensors, cosmic radiation may distort pixels of CMOS image sensors, and then distorted pixels may cause white point effects in dark signals in picture images. (Such white point effects shall be hereinafter referred to as "White Pixels". ) Unfortunately, it is not possible with current scientific technology for CMOS image sensors to prevent such White Pixels. It is recommended that when you use CMOS image sensors, you should consider taking measures ag ainst such White Pixels, such as adoption of automatic compensation systems for White Pixels in dark sign als and establishment of quality assurance standards. Unless the Seller's liability for White Pixels is otherwi se set forth in an agreement between you and the Seller, Sony Corporation or its distributors (hereinafter collec tively referred to as the "Seller") will, at the Seller's expense, replace such CMOS image sensors, in the event the CMOS image sensors delivered by the Seller are found to be to the Seller's satisfaction, to have over the allowable range of White Pixels as set forth as set forth above under the heading "Spot Pixe ls Specifications", within the period of three months after the delivery date of such CMOS image sensors from the Seller to you; provided that the Seller disclaims and will not assume any liability after if you have incorporat ed such CMOS image sensors into other products. Please be aware that Seller disclaims and will not assume any liability for (1) CMOS image sensors fabricated, altered or modified after delivery to you, (2) CMOS image sensors incorporated into other products, (3) CMOS image sensors shipped to a third party in any form whatsoever, or (4) CMOS image sensors delivered to you over three months ago. Except the above mentioned repl acement by Seller, neither Sony Corporation nor its distributors will assume any liability for White Pixels. Please resolve any problem or trouble arising from or in connection with White Pixels at your costs and expenses. [For Your Reference] The Annual Number of White Pixels Occurrence The chart below shows the predictable data on the annual number of white pixels occurrence in a single-story building in Tokyo at an altitude of 0 meters. It is recommended that you should consider taking measures against the annual White Pixels, such as adoption of automatic compensation systems appropriate for each annual number of White Pixels occurrence. The data in the chart is based on records of past fiel d tests, and signifies estimated number of White Pixels calculated according to structures and electrical proper ties of each device. Moreover, the data in the chart is for your reference purpose only, and is not to be us ed as part of any CMOS image sensor specifications. Example of Annual Number of Occurrence 2.4 p.c.s 1.6 p.c.s 0.8 p.c.s 0.5 p.c.s 0.4 p.c.s 24.0 mV or higher 50.0 mV or higher 72.0 mV or higher White Pixel Level (in case of integration time = 1/30 s) (Ta = 60 ℃) 5.6 mV or higher 10.0 mV or higher Annual number of occurrence Note 1) The above data indicates the number of White Pixels occurrence when a CMOS image sensor is left for a year. Note 2) The annual number of White Pixels occurrence fluctuates depending on the CMOS image sensor storage environment (such as altitude, geomagnetic latitude and building structure), time (solar activity effects) and so on. Moreover, there may be statistic erro rs. Please take notice and understand that this is an example of test data with experiments that ha ve being conducted over a specific time period and in a specific environment. Note 3) This data does not guarantee the upper limits of the number of White Pixels occurrence. For Your Reference: The annual number of White Pixels occurrence at an altitu de of 3,000 meters is from 5 to 10 times more than that at an altitude of 0 meters because of the density of the cosmic rays. In addition, in high latitude geographical areas such as London and New York, the density of cosmic rays increases due to a difference in the geomagnetic density, so the annual number of White Pixels occurrenc e in such areas approximately doubles when compared with that in Tokyo.

Measurement Method for Spot Pixels After setting the measurement condition to the standard imaging condition II, and the device drive conditions are within the bias and clock voltage conditions. Configure the drive circuit according to the example and measure. 1. Black or white pixels at high light After adjusting the average value of the Gr/Gb signal output to 425 mV, measure the local dip point (black pixel at high light, ViB) and the peak point (white pixel at high light, ViK) in the Gr/Gb/R/B signal output Vi (i = Gr/Gb/R/B), and substitute the values into the following formula. Spot pixel level D = {(Vi B or Vi K )/Vi average value} × 100 [%] V iK V iB Vi (i = R, G, B, VG = 425 mV) White pixel Black pixel Signal output waveform of R/G/B channel 2. White pixels in the dark Set the device to a dark setting and measure the local peak point of the signal output waveform using the average value of the dark signal output as a reference. 3. Black pixels at signal saturated Set the device to operate in saturation and measure the local dip point using the OB output as a reference. Vsat (MiN. = 812 mV)OF Black pixelLevel D OB output Signal output waveform of R/G/B channel

Spot Pixel Pattern Specifications Spot pixel patterns are counted as shown below. List of Spot Pixel Patterns No. Pattern White pixel Bright spot Black pixel Rejected Rejected Rejected Rejected Rejected Rejected Allowed Allowed Allowed Rejected Allowed Allowed Allowed Allowed Allowed Note) 1. : Black circles indicate the positions of spot pixels. The patterns are specified separately for white pixels, black pixels and bright spots. (Example: Even when a black pixel and a white pixel are arranged as shown by pattern No. 1, this is not judged as a defect (Allowed).) 2. Sensors exhibiting one or more patterns indicated as “Rejected” are sorted and removed. 3. Sensors exhibiting patterns indicated as “Allowed” are not subject to sorting and removal, and these pixels are instead counted in the number of allowable spot pixels by zone. 4. White pixels and black pixels other than the patterns noted in the table above are all counted in the number of allowable spot pixels by zone.

Zone Allowable pixels Size Level Lens aperture 0 to II 0 L ≥ 3 R ≥ 8 % F = 16 Means no stain over three lines or more. Stain Zone Definition 1225 (V) 1984 (H) V20 H V H V V V Zone0 ZoneI ZoneII 2H – V 2H – V Stain Measurement Method In the following measurement, set the measurement condition to the standard imaging condition II, set the lens diaphragm to F16, and adjust the luminous intensity so that the average value of the G channel signal output is 150 mV. Measure the local dip in the average value of the R/G/B channel signal output (ViBL), and then calculate the stain level (R) as the ratio of ViBL to the average value of the R/G/B channel signal output (Vi). Stain level R = (Vi BL At the same time, the size (L) of the area where the stain level is 8 % or more is determined by line number conversion. The distance from one center of a stain to another is the stain interval, and is also determined in the same way by line number conversion. Vi × 0.08 OB output L V iBL Signal output waveform of R/G/B channel

(Exit pupil distance: -30 mm) The recommended CRA characteristics is 0.0 degrees all over the image height (0 – 100 %), because the target E.P.D. is infinite. described below. The real CRA should be smaller than the table below. CRA [deg] Image height [%] 0 1 02 03 04 05 06 07 08 09 0 1 0 0

1. Static charge prevention Image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. (1) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. (2) Use a wrist strap when handling directly. (3) Install grounded conductive mats on the floor and working table to prevent the generation of static electricity. (4) Ionized air is recommended for discharge when handling image sensors. (5) For the shipment of mounted boards, use boxes treated for the prevention of static charges. 2. Protection from dust and dirt Image sensors are packed and delivered with care taken to protect the element glass surfaces from harmful dust and dirt. Clean glass surfaces with the following operations as required before use. (1) Perform all lens assembly and other work in a clean environment (class 1000 or less). (2) Do not touch the glass surface with hand and make any object contact with it. If dust or other is stuck to a glass surface, blow it off with an air blower. (For dust stuck through static electricity, ionized air is recommended.) (3) Clean with a cotton swab with ethyl alcohol if grease stained. Be careful not to scratch the glass. (4) Keep in a dedicated case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. (5) When a protective tape is applied before shipping, remove the tape applied for electrostatic protection just before use. Do not reuse the tape. 3. Installing (attaching) (1) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. (2) The adhesive may cause the marking on the rear surface to disappear. (3) If metal, etc., clash or rub against the package surface, the package may chip or fragment and generate dust. (4) Acrylate anaerobic adhesives are generally used to attach this product. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives to hold the product in place until the adhesive completely hardens. (reference) (5) Note that the sensor may be damaged when using ultraviolet ray and infrared ray on mounting it.

1. Recommended reflow soldering conditions The following items should be observed for reflow soldering. (1) Temperature profile for reflow soldering (2) Reflow conditions (a) Make sure the temperature of the upper surface of the seal glass resin adhesive portion of the package does not exceed 245 °C. (b) Perform the reflow soldering only one time. (c) Finish reflow soldering within 72 h after unsealing the degassed packing. Store the products under the condition of temperature of 30 °C or less and humidity of 70 % RH or less after unsealing the package. (d) Perform re-baking only one time under the condition at 125 °C for 24 h. (3) Others (a) Carry out evaluation for the solder joint reliability in your company. (b) After the reflow, the paste residue of protective tape may remain around the seal glass. (The paste residue of protective tape should be ignored except remarkable one.) (c) Note that X-ray inspection may damage characteristics of the sensor. 5. Others (1) Do not expose to strong light (sun rays) for long periods, as the color filters of color devices will be discolored. (2) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or use in such conditions. (3) This product is precision optical parts, so care should be taken not to apply excessive mechanical shocks or force. (4) Note that imaging characteristics of the sensor may be affected when approaching strong electromagnetic wave or magnetic field during operation. (5) Note that image may be affected by the light leaked to optical black when using an infrared cut filter that has transparency in near infrared ray area during shooting subjects with high luminance. Control item 1. Preheating 2. Temperature up (down) 3. Reflow temperature 4. Peak temperature Profile (at part side surface) 150 to 180 °C 60 to 120 s Over 230 °C 10 to 30 s Max. 5 °C/s Max. 240 ± 5 °C +4 °C/s or less (–6 °C/s or less) Temperature Peak 240 ± 5°C 230 °C Max. 5 °C/s –6 °C/s or less +4°C/s or less 180 °C 150 °C 10 to 30 s 60 to 120 s Reflow Time Preheating

(Unit: mm)

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.