ILX751A

ILX751A SONY | Alldatasheet

Document overview

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Technical content

Features

• Number of effective pixels: 2048 pixels
• Pixel size: 14µm
• 14µm (14µm pitch)
• Built-in timing generator and clock-drivers
• Shutter function
• Ultra low lag
• Maximum clock frequency: 5MHz Absolute Maximum Ratings
• Supply voltage V DD1 11 V VDD2 6V
• Operating temperature –10 to +55 °C
• Storage temperature –30 to +80 °C Pin Configuration(Top View) Block Diagram – 1 – E00440-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. ILX751A 22 pin DIP (Cer-DIP) 22 20 17 16 15 14 13 12 10 91142119587632 1VOUT Output amplifier Sample-and-hold circuit V DD2 NC V DD1 GND NC NC NC NC GND NC φSHUTφROGSHSWVDD2GNDφCLKVDD2NCNCNCNC Clock pulse generator Sample-and-hold pulse generator Mode selector Read out gate pulse generator Shutter gate pulse generator Clock-drivers CCD analog shift register Read out gate Shutter gate D14 D15 D33 S2047 S2048 D34 D35 D36 D37 D38 D39 Shutter drain 1 22VOUT 2NC 3NC 4SHSW 5φCLK 6NC 7NC 8VDD2 9φSHUT 10NC 12φROG VDD2 VDD2 VDD1 GND NC GND NC NC NC NC GND 2048

– 2 – ILX751A Unit pF pF pF Max. Typ. Min. Symbol C f CLK C fROG C fSHUT Item Input capacity of fCLK pin Input capacity of fROG pin Input capacity of fSHUT pin Input Capacity of Pins Item Unit V V Max. 9.5 5.25 Typ. 9.0 5.0 Min. 8.5 4.75 Item VDD1 VDD2 Recommended Supply Voltage Pin condition Pin 4 SHSW GND VDD2 Mode in use S/H Yes No Mode Description Unit V V Max. 5.5 0.5 Typ. 5.0 Min. 4.5 0.0 Input clock high level Input clock low level Recommended Input Pulse Voltage Pin Description Pin No. Symbol Description V OUT NC NC SHSW fCLK NC NC V DD2 fSHUT NC fROG Signal output NC NC with S/H fi GNDSwitch without S/H fi V DD 2 Clock pulse NC NC 5V power supply Shutter pulse NC Clock pulse Pin No. Symbol Description GND NC NC NC NC GND NC GND' V DD1 VDD2 VDD2 GND NC NC NC NC GND NC GND 9V power supply 5V power supply 5V power supply Note) Rules for raising and lowering power supply voltage To raise power supply voltage, first raise V DD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).

– 3 – ILX751A Unit RemarksMax. 8.0 2.0 3.0 8.0 5.0 5.0 Typ. 2.0 1.8 0.3 0.5 0.02 6000 0.045 4.0 1.8 97.0 600 4.0 1.0 Min. 1.5 92.0 Symbol R PRNU V SAT VDRK DSNU IL DR SE I VDD1 IVDD2 TTE Z O VOS SHUT Item Electrooptical Characteristics (Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Clock frequency = 1MHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm)) Notes) 1. For the sensitivity test light is applied with a uniform intensity of illumination. 2. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. PRNU = · 100 [%] The maximum output is set to VMAX , the minimum output to VMIN and the average output to VAVE . 3. Integration time is 10ms. 4. VOUT = 500mV 5. DR = When optical accumulated time is shorter, the dynamic range gets wider because dark voltage is in proportion to optical accumulated time. 6. SE = 7. Vos is defined as indicated below. (VMAX – VMIN )/2 VAVE VSAT R G N D O S D 31 D 32 D 33 S1 VO S V/(lx · s) V mV mV lx · s mA mA Ω V Note 1 Note 2 Note 3 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Secsitivity Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure 9V supply current 5V supply current Total transfer efficiency Output impedance Offset level Shutter lag V SAT VDRK

– 4 – ILX751A 8. To stipulate the lag during shutter operation, use the formula below. Place the output voltage average value during shutter operation at VSHUT and the output voltage average value when the shutter is not in operation at VAVE . (Refer to Fig. 5.) SHUT = · 100 [%] Please note that the shutter pulse at this time accord with Fig. 5. VSHUT VAVE

– 5 – ILX751A Fig. 1. Clock Timing Diagram (without S/H mode) D um m y signal (33 pixels) O ptical black (18 pixels) D um m y signal (6 pixels) Effective picture elem ents signal (2048 pixels) 1-line output period (2087 pixels) D11 D12 D13 D14 D15 D31 D32 D33 S2045 S2046 S2047 S2048 D34 D35 D36 S37 S38 D39 2087 φR O G φC LK VO U T

– 6 – ILX751A Fig. 2. fCLK, VOUT Timing /,/,/#01/#02 /#03 /#04/#05 /#07/#08 /#08 /,/,/#01/#02 /#03 /#03 /#04 /#04 /#05 /#05 /#06/#07 /#08/#08 /#08 φC LK t3 t4 t2t1 VO U T Item fCLK pulse rise/fall time fCLK pulse duty *1 fCLK – VOUT 1 fCLK – VOUT 2 Symbol t1, t2 Min. Typ. Max. 110 120 Unit ns ns ns Fig. 3. fROG, fCLK Timing φR O G φC LK t7 t11 t8 t10t9 Item fROG, fCLK pulse timing fROG pulse rise/fall time fROG pulse period Symbol t7, t11 t8, t10 Min. 500 500 Typ. 1000 1000 Max. Unit ns ns ns

– 7 – ILX751A Fig. 4. fSHUT Timing φSH U T t12 t14t13 Item fSHUT pulse rise/fall time fSHUT pulse period Symbol t12, t13 t14 Min. 500 Typ. 1000 Max. Unit ns ns

– 8 – ILX751A Fig. 5. Shutter Operation Mode Clock 2087 bits or m ore Light source O N 1m s φR O G φC LK ∗ D uring shutter lag evaluation, the light source w ill be accom panied by a flash. φSH U T Illum ination∗

– 9 – ILX751A Fig. 6. Shutter Pulse and Output Voltage O N 0VφR O G Illum ination φSH U T VO U T O FF O N O N Shutter O N VAVE VSH U T O FF O FF

– 10 – ILX751A * Description of Shutter Pin 9 1) The state at 5V is when the shutter is not in operation. 2) When dropped to 0V, the shutter gate will open, letting the accumulated charge of the sensor be thrown away to the shutter drain. /#01 /#02 /#03 /#05 /#06/#07 /#02 /#03 /#05 /#06/, /#01 /#01 /#02 /#02 /#03 /#03 /#04 /#04 /#05 /#05 /#06 /#06 /#07 /#07 /#08 /#08 /#01 /#07 The charge is sent to the transfer register as signal charge. The charge up to this point w ill be throw n aw ay to the shutter drain. Shutter gate O N φR O G φSH U T Accum ulated charge of the sensor

– 11 – ILX751A Example of Representative Characteristics D ark signal voltage rate vs. A m bient tem perature (Standard characteristics) D ark signal voltage rate 0.5 0.1 0 10 20 30 Ta – Am bient tem perature [°C ] 40 50 60 VD D 1, VD D 2 supply current vs. C lock frequency (Standard characteristics) IVD D 1 Ta = 25°C IVD D 2 IVD D 1, IVD D 2 – VD D 1, VD D 2 supply current [m A] 0.5 0.1 0.1M 1M C lock frequency [H z] Spectral sensitivity characteristics (Standard characteristics) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 R elative sensitivity 400 500 600 700 800 900 1000 W avelength [nm ]

– 12 – ILX751A Application Circuit VOUT NC NC SHSW φCLK NC NC VDD2 (D) φSHUT NC φROG VDD2 (D) VDD2 (D) 0.01µ 10µ/16V 2SA1175 φC LK φSH U T φR O G 22µ/10V0.01µ O utput signal 3kΩ VDD1 (A) GND (A) NC GND (A) NC NC NC NC GND (D) 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 13 – ILX751A Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. U pper ceram ic layer 39N Low er ceram ic layer Low -m elting glass (1) 29N (3) 0.9N m (4) 29N (2) /,/#01/#02/#04 /#05/#07/#08 /,/#01/#02/#04 /#05/#07/#08 /#01 /#03 /#05/#07/#08 /#01 /#03 /#05/#07/#08 /#01/#02/#04 /#07/#08 /#01/#02/#04 /#07/#08

– 14 – ILX751A 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

– 15 – ILX751A Package Outline Unit: mm 1. The height from the bottom to the sensor surface is 2.45 ± 0.3m m . 2. The thickness of the cover glass is 0.7m m , and the refractive index is 1.5. V H 7.35 ± 0.5 28.672 (14µm X 2048Pixels) 41.6 ± 0.5 1 11 N o.1 Pixel 2.54 0.51 3.65 4.35 ± 0.5 0.25 0° to 9° 10.0 ± 0.5 0.3 22pin D IP (400m il) M C er-D IP TIN PLATIN G

42 ALLO Y

5.20g PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS D R AW IN G N U M BER LS-A18-01(E) Sony Corporation