ILX703A SONY | Alldatasheet

Document overview

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Technical content

Features

  • Number of effective pixels: 2048 pixels
  • Pixel size: 14µm · 14µm (14µm pitch)
  • Built-in timing generator and clock-drivers
  • Shutter function
  • Ultra low lag
  • Maximum clock frequency: 5MHz Absolute Maximum Ratings
  • Supply voltage V DD1 11 V VDD2 6V
  • Operating temperature –10 to +55 °C
  • Storage temperature –30 to +80 °C Pin Configuration (Top View) – 1 – E93124D78-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. ILX703A 22 pin DIP (Ceramic) 1VOUT 2GND 3GND 4SHSW 5φCLK 6VDD1 7GND 8VDD2 9SHUT 10NC 11φROG 12 GND VDD2 EXRS VDD1 RSSW V GG GND GND V DD1 NC NC 2048

– 2 – ILX703A Block Diagram /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines VOUT GND GND SHSW φCLK VDD1 GND VDD2 SHUT NC φROG GND VDD2 EXRS VDD1 RSSW VGG GND GND VDD1 NC NC 2 3 456 7 8 9 121314151617 Shutter gate Shutter drain Read out gate CCD analog shift register Clock-drivers Clock pulse generator Sample-and-hold pulse generator Mode selector Read out gate pulse generator Shutter gate pulse generator Output amplifier Sample-and-hold circuit D39 D38 D37 D36 D35 D34 S2048 S2047 D33 D15 D14

– 3 – ILX703A Pin Description Pin No. Symbol V OUT GND GND SHSW fCLK V DD1 GND V DD2 SHUT NC fROG GND NC NC V DD1 GND GND V GG RSSW VDD1 EXRS VDD2

Description

with S/H fi GNDSwitch without S/H fi V DD2 Clock pulse 9V power supply GND 5V power supply Shutter pulse NC Clock pulse GND NC NC 9V power supply GND GND Output circuit gate bias Reset pulse swithover pin (External RS fi V DD2 , Internal RS fi GND) 9V power supply RS input pin during external RS pulse usage 5V power supply

– 4 – ILX703A Item Input capacity of fCLK pin Input capacity of fROG pin Input capacity of SHUT pin Input capacity of EXRS pin Min. Typ. Max. Unit pF pF pF pF Symbol C f CLK C fROG C SHUT C EXRS Input Capacity of Pins Parameter Input clock high level Input clock low level Min. 4.5 0.0 Typ. 5.0 Max. 5.5 0.5 Unit V V Recommended Input Pulse Voltage Item VDD1 VDD2 Min. 8.5 4.75 Typ. 9.0 5.0 Max. 9.5 5.25 Unit V V Recommended Voltage Note) Rules for raising and lowering power supply voltage To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V). Mode in use Pin condition Internal Externel 21 pin EXRS VDD2 VDD2 fRS 19 pin RSSW GND GND VDD2 4 pin SHSWS/HRS GND VDD2 VDD2 Yes No No Mode Description

– 5 – ILX703A Item Sensitivity 1 Sensitivity 2 Sensitivity 3 Sensitivity 4 Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure 9V supply current 5V supply current Total transfer efficiency Output impedance Offset level Shutter lag Min. 22.5 1.5 92.0 Typ. 500 2.0 1.8 0.3 0.5 0.02 6000 0.060 8.0 3.0 97.0 600 4.5 1.0 Max. 37.5 8.0 2.0 3.0 14.0 6.0 5.0 Unit V/(lx · s) V/(lx · s) V/(lx · s) V/(lx · s) V mV mV lx · s mA mA Ω V Remarks Note 1 Note 2 Note 3 Note 4 Note 5 Note 6 Note 6 Note 7 Note 8 Note 9 Note 10 Note 11 Symbol PRNU V SAT VDRK DSNU IL DR SE I VDD1 IVDD2 TTE Z O VOS SHUT Electro-optical Characteristics (Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Clock frequency: 1MHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm)), When Internal RS (Pin 19 = GND, Pin 21 = VDD2 ) Notes) 1) For the sensitivity test light is applied with a uniform intensity of illumination. 2) W lamp (2854K) 3) Light source: LED l = 570nm 4) Light source: LED l = 660nm 5) PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 1. PRNU = · 100 [%] The maximum output is set to V MAX , the minimum output to VMIN and the average output to VAVE . 6) Integration time is 10ms. 7) V OUT = 500mV 8) DR = VSAT /VDRK When optical accumulated time is shorter, the dynamic range gets wider because dark voitage is in proportion to optical accumulated time. 9) SE = V SAT /R1 (VMAX – VMIN )/2 VAVE

– 6 – ILX703A 10) VOS is defined as indicated below. 11) To stipulate the lag during shutter operation, use the formula below. Place the output voltage average value during shutter operation at VSHUT and the output voltage average value when the shutter is not in operation at VAVE . (Refer to Figure 7.) Please note that the shutter pulse at this time accord with Figure 6. VSHUTSHUT = · 100 [%]VAVE OS GND D32 D33 S1D31 VOS

Figure 1. Clock Timing Diagram (For internal RS mode)

Figure 2. Clock Timing Diagram (For external RS mode)

Figure 3. fCLK, VOUT Timing (For internal RS mode)

Figure 4. fCLK, fRS, VOUT Timing (For external RS mode)

Figure 5. fROG, fCLK Timing

Figure 6. Shutter Operation Mode Clock ∗ During shutter lag evaluation, the light source will be accompanied by a flash.

Figure 7. Shutter Pulse and Output Voltage

– 14 – ILX703A * Description of Shutter Pin 9 1) The state at 5V is when the shutter is not in operation. 2) When dropped to 0V, the shutter gate will open, letting the accumulated charge of the sensor be thrown away to the shutter drain. φROG φSHUT /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines Accumulated charge of the sensor The charge up to this point will be thrown away to the shutter drain. Shutter gate ON The charge is sent to the transfer register as signal charge.

– 15 – ILX703A Spectral sensitivity characteristics (Standard characteristics) 400 500 600 700 800 900 1000 Wavelength [nm] 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Relative sensitivity 0.2 0.4 0.6 0.8 1.0 X-MTF MTF of main scanning direction (Standard characteristics) Normalized spatial frequency Spatial frequency [cycles/mm] 0.2 0.4 0.6 0.8 1.0 Y-MTF MTF of sub scanning direction (Standard characteristics) Normalized spatial frequency Spatial frequency [cycles/mm] Ta = 25°C Example of Representative Characteristics

– 16 – ILX703A 0.5 0.1 Dark signal voltage rate Dark signal voltage rate vs. Ambient temperature (Standard characteristics) Ta – Ambient temperature [°C] 10 20 30 40 50 0.1M 0.5 0.1 IVDD1 , I VDD2 – V DD1 , V DD2 supply current [mA] VDD1 , VDD2 supply current vs. Clock frequency (Standard characteristics) Clock frequency [Hz] 1M 5M IVDD1 IVDD2

– 17 – ILX703A Application Circuit(When internal RS) 0.01µ 1 2 3 4 5 6 7 8 9 10 11 1222 21 20 19 18 17 16 15 14 13 VOUT (D) GND (A) GND SHSW φCLK (A) VDD1 (D) GND (D) VDD2 SHUT NC φROG NC GND (D) VDD2 (D) EXRS V DD1 (A) RSSW V GG GND (A) GND (A) VDD1 (A) NC 22 pin DIP 10µ/16V φCLK φSHUT φROG 22µ/10V0.01µ Output signal 3kΩ 10µ/16V 2SA1175 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 18 – ILX703A Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Regulation for raising and lowering the power supply voltage When raising the supply voltage, first raise V DD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and then VDD1 (9V). 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

– 19 – ILX703A Package Outline Unit: mm PACKAGE STRUCTURE 22pin DIP (400mil) V H 41.6 ± 0.5 7.35 ± 0.8 5.0 ± 0.5 11 1 1222 No.1 Pixel 40.2 9.0 10.16 0° to 9° 0.25 0.512.54 4.0 ± 0.5 0.32.6 28.672 (14µm × 2048Pixels) 1. The height from the bottom to the sensor surface is 1.61 ± 0.3mm. 2. The thickness of the cover glass is 0.7mm, and the refractive index is 1.5 . (AT STAND OFF) M PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT Cer-DIP TIN PLATING

42 ALLOY

3.9g