ILX532A

ILX532A SONY | Alldatasheet

Document overview

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Technical content

Features

• Number of effective pixels: 7500 pixels
• Pixel size: 7µm · 7µm (7µm pitch)
• Clamp circuit are on-chip
• Signal output phase of two-output simultaneous-output (alternate-output is available)
• Ultra high sensitivity/Ultra low lag
• Max Data Rate: 40MHz
• Single 12V power supply
• Input Clock Pulse: CMOS 5V drive
• Package: 28 pin Cer-DIP (400mil) Absolute Maximum Ratings
• Supply voltage V DD 15 V
• Operating temperature –10 to +60 °C
• Storage temperature –30 to +80 °C Pin Configuration(Top View) Block Diagram – 1 – E98344-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. ILX532A 28 pin DIP (Cer-DIP) 1718 192023 25262728 φCLP-ODD φRS-ODD φLH-ODD GND VOUT -ODD VGG φ2-ODD φ1-ODD VDD φROG φCLP-EVEN φRS-EVEN φLH-EVEN VDD VOUT -EVEN VDD φ2-EVEN GNDφ1-EVEN VDD GND /n00 CCD analog shift register 1 2 34 10 11 1216 CCD analog shift register Read out gate Read out gate D25 D26 D74 S7499 S7500 D75 D94 /n00 Output amplifier Output amplifier φROG pulse generator 14 15 NC φCLP-ODD φRS-ODD φLH-ODD GND 7500 VOUT -ODD VGG NC NC φ2-ODD φ1-ODD VDD φROG NC NC φCLP-EVEN φRS-EVEN φLH-EVEN VDD VOUT -EVEN VDD NC NC φ2-EVEN GND φ1-EVEN VDD GND

– 2 – ILX532A Unit pF pF pF pF pF Max. Typ. 500 Min. Symbol C f1, Cf2 C f LH C fRS C fCLP C fROG Item Input capacity of f1*1, f2*1 Input capacity of fLH *1 Input capacity of fRS *1 Input capacity of fCLP *1 Input capacity of fROG Clock Characteristics Unit MHz MHz Max. Typ. Min. Symbol ff1, ff2, ffLH , ffRS , ffCLP ffR f1, f2, fLH, fRS, fCLP Data rate Clock Frequency Unit V Max. 12.6 Typ. Min. 11.4 Item VDD Recommended Supply Voltage Unit V V Max. 0.1 5.25 Typ. 5.0 Min. 4.75 Low level High level f1, f2, fLH, fRS, fCLP, fROG pulse voltage Input Clock Pulse Voltage Condition *1 It indicates that f1-ODD , f1-EVEN as f1, f2-ODD , f2-EVEN as f2, fLH-ODD , fLH-EVEN as fLH, fRS-ODD , fRS-EVEN as fRS, fCLP-ODD , fCLP-EVEN as fCLP. Pin Description Pin No. Symbol Description fCLP- ODD fRS-ODD fLH-ODD GND VOUT-ODD VGG NC NC f2- ODD f1-ODD VDD fROG NC NC Clock pulse input (odd pixel) Clock pulse input (odd pixel) Clock pulse input (odd pixel) GND Signal out (odd pixel) Output circuit gate bias NC NC Clock pulse input (odd pixel) Clock pulse input (odd pixel) 12V power supply Readout gate clock pulse input NC NC Pin No. Symbol Description NC GND V DD f1-EVEN GND f2-EVEN NC NC V DD VOUT-EVEN VDD fLH-EVEN fRS-EVEN fCLP-EVEN NC GND 12V power supply Clock pulse input (even pixel) GND Clock pulse input (even pixel) NC NC 12V power supply Signal out (even pixel) 12V power supply Clock pulse input (even pixel) Clock pulse input (even pixel) Clock pulse input (even pixel)

– 3 – ILX532A Unit V/(lx · s) V/(lx · s) V lx · s mV mV mA Ω V Remarks Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Note 9 Note 10 Note 11 Max. 13.8 2.0 5.0 Typ. 25.1 2.5 0.23 0.3 0.6 0.02 150 6.5 Min. 8.2 1.8 0.13 Symbol PRNU V SAT SE RI V DRK DSNU IL I VDD TTE Zo V OS Item Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Saturation exposure Register imbalance Dark voltage average Dark signal nonuniformity Image lag Supply current Total transfer efficiency Output impedance Offset level Electrooptical Characteristics(Note 1) (Ta = 25°C, V DD = 12V, ffR = 2MHz, Input clock = 5Vp-p, Light source = 3200K, IR cut filter CM-500S (t = 1.0mm)) Notes) 1. In accordance with the given electrooptical characteristics, the even black level is defined as the average value of D6, D8, to D24. The odd black level is defined as the average value of D5, D7, to D23. 2. For the sensitivity test light is applied with a uniform intensity of illumination. 3. W lamp (2854K) 4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. V OUT = 500mV (Typ.) PRNU = · 100 [%] The maximum output of each odd and even pixels is set to VMAX , the minimum output to VMIN and the average output to VAVE . 5. Use below the minimum value of the saturation output voltage. 6. Saturation exposure is defined as follows. SE = 7. RI is defined as indicated bellow. V OUT = 500mV (Typ.) RI = · 100 [%] Where average of odd pixels output is set to VODD-AVE , even pixels to VEVEN-AVE . 8. Optical signal accumulated time t int stands at 10ms. 9. The difference between the maximum and average values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time t int stands at 10ms. 10. V OUT = 500mV (Typ.) 11. VOS is defined as indicated below. (VMAX – VMIN )/2 VAVE | VODD-AVE – VEVEN-AVE | VODD-AVE + VEVEN-AVE VSAT /n00 /n00 /n00 /n00 VOS VOUT GND

– 4 – ILX532A Clock Timing Chart 1 (simultaneous output) Note) The transfer pulses (f1, f2, fLH) must have more than 3797 cycles. /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 1-line output period (7594 pixels) Dummy signal (74 pixels) Optical black (48 pixels) 3797 φROG φ1-ODD φ1-EVEN φLH-ODD φLH-EVEN 5φ2-ODD φ2-EVEN 0 5φRS-ODD φRS-EVEN 0 5φCLP-ODD φCLP-EVEN 0 VOUT -ODD VOUT -EVEN S7495 S7497 S7499 D75 D73 D71 D69 D27 D25 D23 D77 D79 D81 D83 D93 S7496 S7498 S7500 D76 D74 D72 D70 D28 D26 D24 D78 D80 D82 D84 D94

– 5 – ILX532A Clock Timing Chart 2 t4 t5 φROG t6 t7 φLH t1 t3 Clock Timing Chart 3 /n00/n00 /n00 φLH φRS φCLP VOUT t10 t11 t12 t14 t13 t17t16 t7 t6 t15 /n00/n00 /n00/n00/n00 /n00/n00 Clock timing of f1, f2, fLH, fRS, fCLP and VOUT at odd or even are the same as timing chart 3 in the case of alternate output.

– 6 – ILX532A Clock Timing Chart 4 Cross point φ1 and φ2 φ20 V 1.5V (Min.) 1.5V (Min.) Cross point φLH and φ2 φLH 0V 2.0V (Min.) 1.5V (Min.)

– 7 – ILX532A Clock Timing Chart 5 (alternate output*1) Note) The transfer pulses (f1, f2, fLH) must have more than 3797 cycles. *1 Alternate output is available by making f1-EVEN , f2-EVEN , fLH-EVEN , fRS-EVEN , fCLP-EVEN delayed to f1-ODD , f2-ODD , fLH-ODD , fRS-ODD , fCLP-ODD for half a cycle. /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n00 /n001-line output period (7594 pixels) Dummy signal (74 pixels) Optical black (48 pixels) 3797 S7495 S7497 S7499 D75 D73 D71 D69 D27 D25 D23 φROG 5φ1-ODD φLH-ODD 0 φ2-ODD 5φ1-EVEN φLH-EVEN 0 φ2-EVEN φRS-ODD φCLP-ODD φRS-EVEN VOUT -ODD φCLP-EVEN VOUT -EVEN D77 D79 D81 D83 D93 S7496 S7498 S7500 D76 D74 D72 D70 D28 D26 D24 D78 D80 D82 D84 D94

– 8 – ILX532A Clock Pulse Recommended Timing Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Max. Typ. 100 1500 1500 200* 200*1 200*1 50*1 Min. 1000 1000 Symbol t10 t11 t12 t13 t14 t15 t16 t17 Item fROG, f1 pulse timing fROG pulse high level period fROG, f1 pulse timing fROG pulse rise time fROG pulse fall time f1 pulse rise time/f2 pulse fall time f1 pulse fall time/f2 pulse rise time fRS pulse high level period fRS, fCLP pulse timing fRS pulse rise time fRS pulse fall time fCLP pulse high level period fCLP, fLH pulse timing fCLP pulse rise time fCL pulse fall time Signal output delay time 1 These timing is the recommended condition under ff1 = 1MHz.

– 9 – ILX532A Application Circuit*1 *1 Data rate ffR = 2MHz. φROG 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1528 27 26 25 24 23 22 21 20 19 18 17 16 NC φCLP-ODD φCLP φRS-ODD φLH-ODD GND VOUT-ODD VOUT -ODD VGG NC NC φ2- ODD φ1-ODD VDD φROG NC NC φCLP-EVEN φRS-EVEN φLH-EVEN VDD VOUT-EVEN VDD NC NC φ2-EVEN GND φ1-EVEN VDD GND 100Ω 100Ω 5.1kΩ Tr1 100Ω 100Ω φRS φLH IC1 0.1µF IC1 IC1: 74AC04 Tr1: 2SC2785 12V 47µF 16V 0.1µF VOUT -EVEN 100Ω 5.1kΩ Tr1 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 10 – ILX532A Example of Representative Characteristics(VDD = 12V, Ta = 25°C) Spectral sensitivity characteristics (Standard characteristics) Wavelength [nm] Relative sensitivity 700 800 9004000 0.2 0.4 0.6 0.8 1.0 500 600 1000 Dark signal output temperature characteristics (Standard characteristics) Ta – Ambient temperature [°C] Output voltage rate 30 40 5000.1 0.5 10 20 60 Integration time output voltage characteristics (Standard characteristics) τ int – integration time [ms] Output voltage rate 510.1 0.5 Offset level vs. Temperature characteristics (Standard characteristics) Ta – Ambient temperature [°C] Vos – Offset level [V] 30 40 5000 10 20 60 ΔVos ΔTa –2mV/°C Offset level vs. VDD characteristics (Standard characteristics) VDD [V] Vos – Offset level [V] 12.011.40 12.6 ΔVos ΔV DD 0.6 Ta = 25°C

– 11 – ILX532A Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-DIP Packages The following points should be observed when handling and installing cer-DIP packages. a) Remain within the following limits when applying static load to the ceramic portion of the package: (1) Compressive strength: 39N/surface (Do not apply load more than 0.7mm inside the outer perimeter of the glass portion.) (2) Shearing strength: 29N/surface (3) Tensile strength: 29N/surface (4) Torsional strength: 0.9Nm b) In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c) Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1) Applying repetitive bending stress to the external leads. (2) Applying heat to the external leads for an extended period of time with soldering iron. (3) Rapid cooling or heating. (4) Rapid cooling or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5) Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an imaging device, do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. Upper ceramic layer 39N Lower ceramic layer Low-melting glass(1) 29N (3) 0.9Nm (4) 29N (2) /n00/n00/n00 /n00/n00/n00 /n00/n00/n00 /n00 /n00 /n00 /n00

– 12 – ILX532A 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

– 13 – ILX532A Package Outline Unit: mm Cer-DIP TIN PLATING

42 ALLOY

8.8g H V 28pin DIP (400mil) (AT STAND OFF)1 7 28 22 8 14 1521 10.12±0.5 52.5(7µmX7500pixels) 71.00±0.8 68.0 9.0 10.0±0.5 10.16 0.250 to 9˚ 5.0±0.5 No. 1 Pixel 4.0±0.5 2.54 0.46 3.60 4.40±0.516.5 16.5 1. The height from the bottom to the sensor surface is 2.4mm±0.3. 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5. 3. The notches of the package must not be used for reference of fixing. PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE MASS DRAWING NUMBER LS-C5(E)