ILX508A SONY | Alldatasheet

Document overview

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Technical content

Features

  • Number of effective pixels: 7926 pixels
  • Pixel size: 7µm · 7µm (7µm pitch)
  • Built-in timing generator and clock-drivers
  • Ultra high sensitivity
  • Ultra low lag/low dark voltage
  • Output method
  • Maximum operating frequency: 12.5MHz Absolute Maximum Ratings
  • Supply voltage V DD1 11 V VDD2 6V
  • Operation temperature –10 to +60 °C
  • Storage temperature –30 to +80 °C Pin Configuration(Top View) – 1 – ILX508A E96X33-PS 7926-pixel CCD Linear Image Sensor (B/W) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. 24 pin DIP (Ceramic) φCLK24

22 RS/SH

20 VDD1

19 GND

17 GND

V GG VDD1 VOUT GND φROG VDD2 VDD2 RSSW GND NC GND 7926

– 2 – ILX508A Block Diagram D17 D184 13141516171819202123 2 3 5 67 8 9 10 112224 Clock-drivers Clock-drivers /LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines VDD1GND V DD2GND φCLKVDD2 RSSW RS/SH T1 GND φROG NCT2T3T4GNDVDD2GNDVDD1VDD1VDD1

  • Output amplifier
  • Sample-and-hold circuit
  • Feed through suppression circuit D98 S7925 S7926 D99 D115 D116 CCD analog shift register CCD analog shift register Read out gate Read out gate Clock-pulse generator Sample-and-hold pulse generator Mode selector Read out gate pulse generator NC VOUT VGG

– 3 – ILX508A Pin Description Pin No. Symbol V GG GND VDD1 VOUT GND fROG V DD2 VDD2 RSSW * GND NC NC GND V DD2 GND V DD1 VDD1 RS/SH * VDD1 fCLK

Description

RS pulse external, internal selection (External RS fi V DD1 , Internal RS fi GND) Test pin (5V) GND NC NC Test pin (GND) Test pin (5V) Test pin (GND) GND 5V power supply GND 9V power supply 9V power supply Clock pulse or S/H switch 9V power supply Clock pulse 22pin 9pin GND VDD1 GND Internal RS without S/H VDD1 Internal RS with S/H fRS External RS without S/H * Output mode is changeable as follows.

– 4 – ILX508A Item Input capacity of fCLK Input capacity of fROG Input capacity of RS/SH fCLK frequency fRS frequency Min. Typ. Max. 12.5 12.5 Unit pF pF pF MHz MHz Symbol C fCLK C fROG C RS/SH ffCLK ffRS Clock Characteristics Item VDD1 VDD2 Min. 8.5 4.75 Typ. 9.0 5.0 Max. 9.5 5.25 Unit V V Recommended Voltage Note) Rules for raising and lowering power supply voltage. To raise power supply voltage, first raise VDD1 (9V) and then VDD2 (5V). To lower voltage, first lower VDD2 (5V) and then VDD1 (9V).

– 5 – ILX508A Item Sensitivity1 Sensitivity2 Sensitivity nonuniformity Saturation output voltage Saturation exposure Even and odd black level DC difference Dark voltage average Dark signal nonuniformity Image lag 9V supply current 5V supply current Total transfer efficiency Output impedance Offset level Dynamic range Min. 7.5 1.0 0.072 500 Typ. 10.8 24.6 1.5 0.139 1.0 0.3 0.6 0.02 600 3.0 5000 Max. 13.9 12.5 10.0 Unit V/(lx · s) V/(lx · s) V lx · s mV mV mV mA mA Ω V Remarks *10 *12 Symbol PRNU V SAT SE VDRK DSNU IL I VDD1 IVDD2 TTE Z O VOS DR Electrooptical Characteristics*1 (Ta = 25°C, VDD1 = 9V, VDD2 = 5V, Light source = 3200K, fCLK = 1MHz, Internal fRS mode without S/H, IR cut filter, CM-500S (t = 1.0mm)) *1 In accorcance with the given electrooptical characteristics, the even black level is defined as the mean value of D8, D10, D12, D14, and D16. *2 For the sensitivity test light is applied with a uniform intensity of illumination. *3 W lamp (2854K). *4 PRNU is defined as indicated below. Ray incidence conditions are the same as for *2. PRNU = · 100 [%] Where the 7926 pixels are divided into blocks of 102, even and odd pixels, respectively (Even and odd last blocks are 87.) The maximum output of each block is set to VMAX , the minimum output to VMIN and the average output to VAVE . *5 Use below the minimum value of the saturation output voltage. *6 Saturation exposure is defined as follows. SE = *7 Indicates the DC difference in value between odd black level and even black level. *8 optical signal accumulated time t int stands at 10ms. *9 The difference between the maximum and mean values of the dark output voltage is calculated for even and odd respectively. The larger value is defined as the dark signal nonuniformity. Optical signal accumulated time t int stands at 10ms. 10 VOUT = 500mV (Typ.) (VMAX – VMIN )/2 VAVE VSAT

– 6 – ILX508A *11 VOS is defined as indicated below. *12 Dynamic range is defined as follows. DR = When the optical signal accumulated time is shorter, the dynamic range gets wider because the optical signal accumulated time is in proportion to the dark voltage. Vout GND VOS VSAT VDRK

– 7 – ILX508A Application Circuit(External fRS) * When noise influence into output signal is large, connect pins indicated by (A) to the analog power supply and pins indicated by (D) to the digital power supply, and also use a decoupling capacitor of large capacitance. 131415161718192021222324 VGG (A) GND (A) VDD1 (A) VOUT (A) GND (A) φROG VDD2 (D) VDD2 (D) PSSW (D) T1 (D) GND (A) NC φCLK VDD1 (D) RS/SH (D) VDD1 (A) VDD1 (A) GND (D) VDD2 (D) GND (D) T4 (D) T3 (D) T2 (D) NC φROG 10µ/10V0.01µ 0.01µ 0.01µ 10µ/16V 1kΩ 10µ/16V 2SA1175 φRS φCLK Output signal 2 3 4 5 6 7 8 9 10 11 121 Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 8 – ILX508A Clock Timing Diagram(External fRS) /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines /LiteDiagLines 1 line output period (8042 pixels) Dummy signal (98 pixels) Effective picture elements signal (7926 pixels) Dummy signal (18 pixels) Optical black (80 pixels) D16 D17 D18 D19 D20 D96 D97 D98 D7923 D7924 D7925 D7926 D99 D100 D106 D107 D108 D109 D116 VOUT φRS φCLK φROG 8042

– 9 – ILX508A Clock pulse Waveform Conditions fCLK, fROG pulse related Internal fRS mode External fRS mode φROG t8 t9 t3t1 φCLK /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines t5t4 φCLK t8 t9 t11 t10t10 Vout /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines t6t7 t9 t8 t5t4 t12 t13 t10 φCLK φRS

– 10 – ILX508A *1 The frequency of fCLK is 1MHz. Unit ns ns ns ns ns ns ns ns V V ns ns ns ns Item fROG, fCLK pulse timing fROG, fCLK pulse timing fROG pulse high level period fCLK pulse high level period fCLK pulse low level period fRS pulse low level period fCLK, fRS pulse timing Input clock pulse rise/fall time Input clock pulse voltage Signal output delay time High level Low level Internal fRS External fRS Max. 10 + t 4 + t5 5.5 0.5 Typ. 300 1500 1500 500* 500*1 100*1 550*1 5.0 Min. 200 1200 1200 4.5 Symbol t t8, t9 VfCLK, VfROG VfRS t10 t11 t12 t13

– 11 – ILX508A 400 500 600 700 800 900 1000 1.0 0.8 0.6 0.4 0.2 Wavelength [nm] Relative sensitivity Spectral sensitivity characteristics (Standard characteristics) 0.1 10 20 30 40 60 0.5 Output voltage rate Ta – Ambient temperature [°C] Dark signal output temperature characteristics (Typical characteristics) 50 1 0.1 0.5 Output voltage rate τ int – integration time [ms] 0.2 0.4 0.6 0.8 1.0 MTF Normalized spatial frequency Spatial frequency [cycle/mm] MTF of main scanning direction (Standard characteristics) Integration time output voltage characteristics (Typical characteristics) Example of Representative Characteristics(VDD1 = 9V, VDD2 = 5V, Ta = 25°C)

– 12 – ILX508A 2 4 6 8 12.5 IV DD1 – V DD1 supply current [mA] fφCLK – φCLK clock frequency [MHz] Operational frequency characteristics of the VDD1 supply current (Typical characteristics) 8.5 9 9.5 V OS – Offset level [V] VDD1 [V] Ta = 25°C 0.35ΔVOS ΔVDD 1 4.75 5 5.25 V OS – Offset level [V] VDD2 [V] Ta = 25°C ΔVOS ΔVDD 2 2 4 6 8 12.5 IV DD2 – V DD2 supply current [mA] fφCLK – φCLK clock frequency [MHz] 10 20 30 40 60 V OS – Offset level [V] Ta – Ambient temperature [°C] Offset level vs. Temperature characteristics (Typical characteristics) ΔVOS ΔTa – 0.8mV/°C Operational frequency characteristics of the VDD2 supply current (Typical characteristics) Offset level vs. VDD1 characteristics (Typical characteristics) Offset level vs. VDD2 characteristics (Typical characteristics)

– 13 – ILX508A Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates use boxes treated for the prevention of static charges. 2) Regulation for raising and lowering the power supply voltage. When raising the supply voltage, first raise V DD1 (9V) and then VDD2 (5V). Similarly, lower VDD2 (5V) first and then VDD1 (9V). 3) Soldering a) Make sure the package temperature does not exceed 80°C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficienty. c) To dismount an imaging device do not use a solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. 4) Dust and dirt protection a) Operate in clean environments. b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface blow it off with an air blow. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks.

– 14 – ILX508A Package Outline Unit: mm V H 71.0 ± 0.9 9.21 ± 0.8 55.482 (7µm × 7926Pixels) No.1 Pixel 5.0 ± 0.5 68.0 ± 0.15 24Pin DIP (400mil) 1st. pin Index 4.0 ± 0.5 2.29 3.1 ± 0.5 M0.3 9.0 ± 0.15 10.0 ± 0.5 (AT STAND OFF) 10.16 ± 0.3 +0.1 0.25 -0.05 0 ° to 9 ° PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT Ceramic GOLD PLATING 42ALLOY 5.8g 1 12 1324 0.97 ± 0.3 1.27 0.8 ± 0.1 1. The height from the bottom to the sensor surface is 1.42 ± 0.3mm. 2. The thickness of the cover glass is 0.8mm, and the refractive index is 1.5.