ILX103A SONY | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 12

Technical content

Features

  • Number of effective pixels: 3000 pixels
  • Pixel size: 7µm
  • 200µm (7µm pitch)
  • S/H output
  • Built-in timing generator and clock-drivers
  • Output amplifier gain switching function (2-level: switching gain ratio 1:4)
  • SIP small package
  • Clock frequency: 500kHz (Typ.), 100kHz (Min.), 1MHz (Max.) Absolute Maximum Ratings
  • Supply voltage V DD 6V
  • Operating temperature –10 to +60 °C
  • Storage temperature –30 to +80 °C Pin Configuration(Top View) Internal Structure – 1 – E98X48A91-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. ILX103A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1VDD GND Vout Vgg φCLK SWG NC NC φROG φSHUT GND V DD VDD GND NC 3000 /#02 /#03 Vgg GND VDD VDD GND VDD GND D24 D25 D54 D55 S2999 S3000 D56 D65Output Amplifier Driver Readout gate Readout gate CCD analog shift register CCD analog shift register Driver Readout gate pulse generator Shutter pulse generator Timing generator 4 2 1 12 11 14 15 6 13 5 9 10 φSHUT φROG φCLK SWG Vout 3 16 pin SIP (Ceramic)

– 2 – ILX103A Pin Description Pin No. Symbol Description V DD GND Vout Vgg fCLK SWG NC NC fROG fSHUT GND V DD V DD GND NC Power supply GND Signal output Output circuit gate bias Clock pulse input Control (Output circuit amplification factor ·4/·1) NC NC Readout gate pulse input Electrical shutter pulse input GND Power supply TEST (Connect to GND with 1000pF capacitor) Power supply GND NC Recommended Voltage Item VDD Min. 4.5 Mode Description Output circuit gain High Low Pin 6 SWG VDD GND Typ. 5.0 Max. 5.5 Unit V Input Pin Capacity Symbol C fCLK C fROG C fSHUT Min. Typ. Max. Unit pF pF pF Item Input capacity of fCLK pin Input capacity of fROG pin Input capacity of fSHUT pin

– 3 – ILX103A Electro-optical Characteristics (Analog Characteristic) (Note 1) Ta = 25°C, VDD = 5V, Clock frequency: 500kHz, Light source = 3200K, IR cut filter: CM-500S (t = 1.0mm), Output circuit gain low mode Item Symbol Min. Typ. Max. Unit Remarks Sensitivity 1 Sensitivity 2 Sensitivity nonuniformity Saturation output voltage Dark voltage average Dark signal nonuniformity Image lag Dynamic range Saturation exposure 5V current consumption Total transfer efficiency Output impedance Offset level PRNU V SAT VDRK DSNU IL DR SE I VDD TTE Z O VOS 52.5 0.6 92.0 925 5.0 0.8 2.5 5.0 5.0 320 0.01 7.0 97.0 250 2.5 97.5 10.0 6.0 12.0 17.0 V/(lx · s) V/(lx · s) V mV mV lx · s mA Ω V Note 2 Note 3 Note 4 Note 5 Note 6 Note 7 Note 8 Note 9 Note 10 Note) 1. In accordance with the given electro-optical characteristics, the even black level is defined as the average value of D24, D25 to D53. 2. For the sensitivity test light is applied with a uniform intensity of illumination. 3. Light source: LED l = 660nm 4. PRNU is defined as indicated below. Ray incidence conditions are the same as for Note 2. PRNU = · 100 [%] The maximum output of the effective pixels is set to V MAX , the minimum output to VMIN and the average output to VAVE . 5. Integration time is 10ms. 6. The difference between the maximum and average values and the difference between the minimum and average values of the dark output voltage is calculated. The larger value is defined as dark signal nonuniformity. Integration time is 10ms. 7. Typical value is used for clock pulse and readout pulse. V OUT = 500mV. 8. DR = VSAT /VDRK When optical integration time is shorter, the dynamic range sets wider because dark output voltage is in proportion to optical integration time. 9. SE = VSAT /R1 10.Vos is defined as indicated below. (VMAX – VMIN )/2 VAVE D 51 D 52 Vout VO S G N D D 53 D 54 D 55 S1

– 4 – ILX103A φR O G φSH U T φC LK VO U T O ptical black (30 pixels) D um m y signal (55 pixels) 1-Line output period (3066 pixels) 3100 or m ore clock pulses are required. Effective picture elem ents signal (3000 pixels) D um m y signal (10 pixels) D21 D22 D23 D24 D53 D54 D55 S2998 S2997 S2999 S3000 D56 D57 D58 D59 D61 D60 D62 D63 D64 D65 Clock Timing Diagram

– 5 – ILX103A Input Clock Voltage Condition Min. 3.0 0.0 Typ. VDD Max. 5.5 0.1 Unit V V Item VIH VIL Symbol t1, t2 Min. Typ. Max. 100 Unit ns Item fCLK pulse rise/fall time fCLK pulse Duty*1 Symbol t6, t8 Min. 1/8t 1/8t Typ. 1/4t 1/4t 10t Max. 3/8t 3/8t 100 20t Unit ns ns ns ns Item fROG, fCLK pulse timing 1 fROG, fCLK pulse timing 2 fROG pulse rise/fall time fROG pulse period * This is applied to the all external pulses. (fCLK, fROG, fSHUT) fCLK Timing (For all modes) t3 t4 φC LK fROG, fCLK Timing t6 t7 t8 φR O G φC LK t9t5 Note)t is the period of fCLK.

– 6 – ILX103A fSHUT, fCLK Timing Symbol t11, t13 t12 t14 t15 Min. 4000 150 150 Typ. 5000 200 200 Max. 100 250 250 Unit ns ns ns ns Item fSHUT pulse rise/fall time fSHUT pulse period fSHUT, fCLK pulse timing 1 fSHUT, fCLK pulse timing 2 φSH U T φC LK t11 t12 t13 t15 t14 Symbol t16 Min. Typ. 230 Max. Unit ns Item fCLK-Vout output delay time1 φC LK Vout t16 *1 fck = 500kHz, fCLK Duty = 50%, fCLK rise/fall time = 10ns *2 is data period. fCLK Output Signal Timing *1 Note)The high periods of fROG and fSHUT are separated for 10t or more.

– 7 – ILX103A Application Circuit(Output gain low mode)*1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VD D 3kΩ 1µ/16V 0.01µ 1000p 22µ/10V φC LK φR O G φSH U T 2SA1175 Signal output G N D Vout Vgg φC LK SW G N C N C φR O G φSH U T G N D VD D VD D G N D N C *1 This circuit diagram is the case when output circuit gain is low. *2 Connect T1 (Pin 13) to GND with 1000pF capacitor. Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 8 – ILX103A Example of Representative Characteristics(VDD = 5V, Ta = 25°C) 0400 500 600 700 W avelength [nm ] Spectral sensitivity characteristics (Standard characteristics) R elative sensitivity 800 900 1000 0.5 0.1 0.05 0.01–10 0 10 20 Ta – Am bient tem perature [°C ] O utput voltage vs. Tem perature characteristics (Standard characteristics) O utput voltage rate 30 40 50 60

– 9 – ILX103A 0–10 0 10 20 Ta – Am bient tem perature [°C ] O ffset level vs. Tem perature characteristics (Standard characteristics) VO S – O ffset level [V] 30 40 50 60 ∆Vos ∆Ta ~– –2.1m V/°C 04.5 V D D [V] O ffset level vs. VD D characteristics (Standard characteristics) VO S – O ffset level [V] 5 5.5 ∆Vos ∆VD D ~– 0.49 Ta = 25°C 04.5 5 V D D [V] Supply current vs. VD D characteristics (Standard characteristics) IVD D – Supply current [m A] 5.5 Ta = 25°C 110 τ – Integration tim e [m s] O utput voltage vs. Integration tim e (Standard characteristics) O utput voltage rate 50 100

– 10 – ILX103A Notes of Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a)Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b)When handling directly use an earth band. c)Install a conductive mat on the floor or working table to prevent the generation of static electricity. d)Ionized air is recommended for discharge when handling CCD image sensor. e)For the shipment of mounted substrates, use boxes treated for prevention of static charges. 2) Notes on Handling CCD Cer-SIP Packages The following points should be observed when handling and installing cer-SIP packages. a)Remain within the following limits when applying static load to the ceramic portion of the package: (1)Compressive strength:39N/surface (Do not apply load more than 0.5mm inside the outer perimeter of the glass portion.) (2)Shearing strength: 29N/surface (3)Tensile strength: 29N/surface (4)Torsional strength: 0.9Nm b)In addition, if a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portion. Therefore, for installation, either use an elastic load, such as a spring plate, or an adhesive. c)Be aware that any of the following can cause the glass to crack: because the upper and lower ceramic layers are shielded by low-melting glass, (1)Applying repetitive bending stress to the external leads. (2)Applying heat to the external leads for an extended period of time with a soldering iron. (3)Rapid cooling or heating. (4)Applying a load or impact to a limited portion of the low-melting glass with a small-tipped tool such as tweezers. (5)Prying the upper or lower ceramic layers away at a support point of the low-melting glass. Note that the preceding notes should also be observed when removing a component from a board after it has already been soldered. 3) Soldering a)Make sure the package temperature does not exceed 80°C. b)Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a grounded 30W soldering iron and solder each pin in less then 2 seconds. For repairs and remount, cool sufficiently. c)To dismount an image sensor, do not use solder suction equipment. When using an electric desoldering tool, ground the controller. For the control system, use a zero cross type. U pper ceram ic layer 39N Low er ceram ic layer Low -m elting glass(1) 29N (3) 0.9N m (4) 29N (2)

– 11 – ILX103A 4) Dust and dirt protection a)Operate in clean environments. b)Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c)Clean with a cotton bud and ethyl alcohol if the glass surface is grease stained. Be careful not to scratch the glass. d)Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. 5) Exposure to high temperatures or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. 7) Normal output signal is not obtained immediately after device switch on.

– 12 – ILX103A Package Outline Unit: mm 1. The height from the bottom to the sensor surface is 1.6 ± 0.3m m . 2. The thickness of the cover glass is 0.8m m , and the refractive index is 1.5. 16pin SIP 30.3 ± 0.3 21.0 (7µm × 3000Pixels) N o.1 Pixel 1 16 H V 5.08 0.41.27 4.65 ± 0.8 2.23 ± 0.3 4.04.2 5.0 ± 0.2 3.2 ± 0.5 2.4 0.25 1.325 ± 0.3 0.3 M C er-SIP TIN PLATIN G

42 ALLO Y

1.3g PAC KAG E STR U C TU R E PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS D R AW IN G N U M BER LS-D 4(E)