ILD1150 INFINEON | Alldatasheet
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Technical content
Rev. 1.1, 2012-04-11 ILD1150 Multitopology High Power LED DC/DC Controller IC for Industrial Applications
Datasheet 2 Rev. 1.1, 2012-04-11 ILD1150 Table of Contents Table of Contents
ILD1150 PG-SSOP-14 ILD1150 Datasheet 3 Rev. 1.1, 2012-04-11 Multitopology High Power LED DC/DC Controller IC for Industrial Applications ILD1150 ILD1150 1O v e r v i e w
Features
- Wide Input Voltage Range from 4.75 V to 45 V
- Constant Current or Constant Voltage Regulation
- Drives LEDs in Boost, Buck , Buck-Boost, SEPIC and Flyback Topology
- Very Low Shutdown Current: IQ< 10 µA
- Flexible Switching Frequency Range, 100 kHz to 500 kHz
- Synchronization with external clock source
- Output Open Circuit Diagnostic Output
- P W M D i m m i n g
- Internal Soft Start
- 300mV High Side Current Sens e to ensure highest flexibility and LED current accuracy
- Internal 5 V Low Drop Out Voltage Regulator
- Wide LED current range via simple adaptation of external components
- Available in a small thermally enhanced PG-SSOP-14 package
- Output Overvoltage Protection
- Over Temperature Shutdown
- Green Product (RoHS) Compliant
Description
The ILD1150 is a Multitopology High Power DC/DC Controller IC with built in protection features . The main function of this device is to regulate a constant LED current. Th e constant current regulation is especially beneficial for LED color accuracy and longer lifetime. The controller concept of the ILD1150 allows a multi-purpose usage such as Boost, Buck, Buck-Boost, SEPIC and Flyback configuration with various load current levels by simply adjusting the external components. The ILD1150 has a PWM output for dimming a LED load. The diagnostics are communicated on a status output (pin ST) to indicate a fault condition such as an LED open circuit. The switching frequency is adjustable in the range of 100 kHz to 500 kHz and can be synchronized to an external clock source. The ILD1150 features an enable function reducing the shut-down current consumption to <10 µA. The current mode regulation scheme of this device provides a stable regulation loop maintained by small exte rnal compensation components. The integrated soft-start feature limits the current peak as well as voltage overshoot at start-up. This IC provides protection functions such as output overvoltage protection and overtemperature shutdown.
Datasheet 4 Rev. 1.1, 2012-04-11 ILD1150 Overview
Applications
- LED Controller for Industrial Applications
- Universal Constant Current and Voltage Source
- General Illumination e.g. Halogen Replacement
- Residential Architectural and Industrial Commercial Lighting for in- and outdoor
- Signal and Marker Lights for Orientation or Navigation (e.g. steps, exit ways, etc.) For automotive and transportation applications, please refer to the Infineon® Auto LED products.
Datasheet 5 Rev. 1.1, 2012-04-11
2 Block Diagram
Comp. Internal Supply On/Off Logic Leading Edge Blanking PWMO EN_INT/ PWM_INT Thermal Protection Open Load Detection Over Volage Protection PWM Generator Power Switch Gate Driver Feedback Voltage Error Amplifier Dimming Switch Gate Driver Power On Reset EN_INT/ PWM_INT BlockDiagram .vsd Switch Current Error Amplifier
Datasheet 6 Rev. 1.1, 2012-04-11 ILD1150 Pin Configuration
3 Pin Configuration
3.1 Pin Assignment
Figure 2 Pin Configuration
3.2 Pin Definitions and Functions
1I V C C Internal LDO Output; Used for internal biasing and gate drive. Bypass with external capacitor. Pin must not left open. 2S W O Switch Output; Connect to gate of external switching MOSFET 3S G N D Current Sense Ground; Ground return for current sense switch 4S W C S Current Sense Input; Detects the peak current through switch 5P W M O PWM Dimming Output; Connect to gate of external MOSFET 6F B H Voltage Feedback Positive; Non inverting Input (+) 7F B L Voltage Feedback Negative; Inverting Input (-) 8C O M P Compensation Input; Connect R and C network to pin for stability IN COMP OVFB ST FREQ/SYNC GND EN/PWMI IVCC FBL PWMO SGND SWCS SWO FBH EP
Datasheet 7 Rev. 1.1, 2012-04-11 9O V F B Output Overvoltage Protection Feedback; Connect to resistive voltage divider to set overvoltage threshold.
10 ST Status Output;
Open drain diagnostic output to indicate fault condition. Connect pull up resistor to pin.
11 FREQ / SYNC Frequency Select or Synchronization Input;
Connect external resistor to GND to set frequency. Or apply external clock signal for synchronization within frequency capture range.
12 GND Ground;
Connect to system ground.
13 EN / PWMI Enable or PWM Input;
Apply logic high signal to enable device or PWM signal for dimming LED.
14 IN Supply Input;
Supply for internal biasing. EP Exposed Pad; Connect to external heatspreading Cu area with electrically GND (e.g. inner GND layer of multilayer PCB with thermal vias) Pin Symbol Function
Datasheet 8 Rev. 1.1, 2012-04-11 ILD1150 General Product Characteristics
4 General Product Characteristics
4.1 Absolute Maximum Ratings
Absolute Maximum Ratings1) Tj = -40 ⋅C to +125 ⋅C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. Voltages 4.1.1 IN Supply Input VIN -0.3 45 V
4.1.2 EN / PWMI
4.1.3 FBH-FBL;
Feedback Error Amplifier Differential VFBH-VFBL -5.5 5.5 V
4.1.4 FBH;
Feedback Error Amplifier Positive Input VFBH -0.3 45 V
4.1.5 FBL
Feedback Error Amplifier Negative Input VFBL -0.3 45 V
4.1.6 OVFB
Over Voltage Feedback Input VOVP -0.3 5.5 V 4.1.7 -0.3 6.2 V t < 10s
4.1.8 SWCS
Switch Current Sense Input VSWCS -0.3 5.5 V 4.1.9 -0.3 6.2 V t < 10s
4.1.10 SWO
VSWO -0.3 5.5 V 4.1.11 -0.3 6.2 V t < 10s
4.1.12 SGND
VSGND -0.3 0.3 V
4.1.13 COMP
VCOMP -0.3 5.5 V 4.1.14 -0.3 6.2 V t < 10s
4.1.15 FREQ / SYNC; Frequency and
VFREQ / SYNC -0.3 5.5 V 4.1.16 -0.3 6.2 V t < 10s
4.1.17 PWMO
VPWMO -0.3 5.5 V 4.1.18 -0.3 6.2 V t < 10s 4.1.19 ST VST -0.3 45 V
4.1.20 Diagnostic Status Output IST -5 5 mA
4.1.21 IVCC
Internal Linear Voltage Regulator Output VIVCC -0.3 5.5 V 4.1.22 -0.3 6.2 V t < 10s Temperatures
4.1.23 Junction Temperature
Tj -40 150 °C–
4.1.24 Storage Temperature Tstg -55 150 °C–
4.1.25 ESD Resistivity to GND
VESD,HBM -2 2 kV HBM 2)
General Product Characteristics Datasheet 9 Rev. 1.1, 2012-04-11 Note: Stresses above the ones listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation.
4.2 Functional Range
Note: Within the functional range the IC operates as described in the circuit description. The electrical characteristics are specified within the conditions given in the related electrical characteristics table.
4.3 Thermal Resistance
Note: This thermal data was generated in accordance with JEDEC JESD51 standards. For more information, go to www.jedec.org.
4.1.26 ESD Resistivity to GND VESD,CDM -500 500 V CDM 3)
4.1.27 ESD Resistivity Pin 1, 7, 8, 14 (corner
pins) to GND VESD,CDM,C -750 750 V CDM 3) 1) Not subject to production test, specified by design. 2) ESD susceptibility, Human Body Model “HBM” according to ANSI/ESDA/JEDEC JS-001 (1.5kΩ, 100pF) Pos. Parameter Symbol Limit Values Unit Conditions Min. Max. 4.2.1 Supply Voltage Input VIN 4.75 45 V VIVCC > VIVCC,RTH,d
4.2.2 Feedback Voltage Input VFBH;
4.5 45 V –
4.2.3 Junction Temperature Tj -40 125 °C–
Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
4.3.1 Junction to Case 1) 2)
1) Not subject to production test, specified by design. 2) Specified RthJC value is simulated at natural convection on a cold plate setup (all pins and exposed pad are fixed to ambient temperature). Ta=25°C, IC is dissipating 1W. RthJC –1 0 –K / W
4.3.2 Junction to Ambient 1) 3)
3) Specified RthJA value is according to JEDEC 2s2p (JESD 51-7) + (JESD 51-5) and JEDEC 1s0p (JESD 51-3) + heatsink area at natural convection on FR4 board; The device was simulated on a 76.2 x 114.3 x 1.5mm board. The 2s2p board has 2 outer copper layers (2 x 70µm Cu) and 2 inner copper layers (2 x 35µm Cu), A thermal via (diameter = 0.3mm and 25µm plating) array was applied under the exposed pad and connected the first outer layer (top) to the first inner layer and second outer layer (bottom) of the JEDEC PCB. Ta=25°C, IC is dissipating 1W. RthJA –4 7 –K / W 2 s 2 p
4.3.3 RthJA – 54 – K/W 1s0p + 600 mm 2
4.3.4 RthJA – 64 – K/W 1s0p + 300 mm 2
Absolute Maximum Ratings1) Tj = -40 ⋅C to +125 ⋅C; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Max.
Datasheet 10 Rev. 1.1, 2012-04-11 ILD1150 Regulator
5 Regulator
5.1 Description
The ILD1150 regulator is suitable for Boost, Buck, Buck-Boost, SEPIC and Flyback configurations. The constant output current is especially useful for light emitting diode (LED) applications. The multitopology regulator function is implemented by a pulse width modulated (PWM) current mode controller. The PWM current mode controller uses the peak current through the external power switch and error in the output current to determine the appropriate pulse width duty cycle (on time) for constant output current. The current mode controller it provides a PWM signal to an internal gate driver which then outputs the same PWM signal to external n-channel enhancement mode metal oxide field effect transistor (MOSFET) power switch. The current mode controller also has built-in slope compensation to prevent sub-harmonic oscillations which is a characteristic of current mode controllers operating at high duty cycles (>50% duty). An additional built-in feature is an in tegrated soft start that limits the cu rrent through the inductor and external power switch during initialization. The soft start function gradually increases the inductor and switch current over 1 ms (typical) to minimize potential overvoltage at the output. Figure 3 Boost Regulator Block Diagram Oscillator FREQ / SYNC R Q S OFF when H Q Clock Error-FF Low when Tj > 175 °C EA FBH COMP H when OVFB >1.25V Output Stage OFF when Low NOR NAND 2 R Q S Q PWM-FF INV Gate Driver Gate Driver Supply SWO IVCC Current SenseI Soft startVRef 0.3V = Slope Comp t FBL gmEA VRef 1.25V SGND SWCS Current Comp OVFB I SLOPE IEA ICS High when l EA -I SLOPE -I CS >0 VRef 4. 0V High when IVCC < 4.0V UV IVCC OV FB
Datasheet 11 Rev. 1.1, 2012-04-11
5.2 Electrical Characteristics
All parameters have been tested at 25°C, unless otherwise specified. VIN = 24V, Tj = -40 ⋅C to +125 ⋅C, all voltages with respect to ground, posi tive current flowing into pin; (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. Regulator:
5.2.2 Voltage Line Regulation ΔVREF
/ΔVIN IBO = 500 mA Figure 25
5.2.3 Voltage Load Regulation (ΔVREF
/ VREF) /ΔIBO ––5% / A VBO = 30V; IBO = 100 to 500 mA Figure 25
5.2.4 Switch Peak Over Current
VSWCS 130 150 170 mV VFBH = VFBL = 5 V VCOMP = 3.5V
5.2.5 Maximum Duty Cycle DMAX,fixed 90 93 95 % Fixed frequency mode
5.2.6 Maximum Duty Cycle DMAX,sync 88 – – % Synchronization mode
5.2.7 Soft Start Ramp tSS 350 1000 1500 µs VFB rising from 5% to
95% of VFB, typ. 5.2.8 Feedback Input Current IFBx -10 -50 -100 µA VFBH - VFBL = 0.3 V
5.2.9 Switch Current Sense Input
ISWCS 10 50 100 µA VSWCS = 150 mV 5.2.10 Input Undervoltage Shutdown VIN,off 3.75 – – V VIN decreasing 5.2.11 Input Voltage Startup VIN,on – – 4.75 V VIN increasing Gate Driver for external Switch
5.2.12 Gate Driver Peak Sourcing
Current1) ISWO,SRC –3 8 0 –m A VSWO = 3.5V
5.2.13 Gate Driver Peak Sinking
Current1) ISWO,SNK –5 5 0 –m A VSWO = 1.5V 5.2.14 Gate Driver Output Rise Time tR,SWO –3 0 6 0 n s CL,SWO = 3.3nF; VSWO = 1V to 4V 5.2.15 Gate Driver Output Fall Time tF,SWO –2 0 4 0 n s CL,SWO = 3.3nF; VSWO = 1V to 4V 1) Not subject to production test, specified by design
Datasheet 12 Rev. 1.1, 2012-04-11 ILD1150 Oscillator and Synchronization
6 Oscillator and Synchronization
6.1 Description
The internal oscillator is used to deter mine the switching frequency of the mu ltitopology regulator. The switching frequency can be selected from 100 kHz to 500 kHz wit h an external resistor to GND. To set the switching frequency with an external resistor the following formula can be applied. In addition, the oscillator is capable of changing from the frequency set by the external resistor to a synchronized frequency from an external clock source. If an external clock source is provided on the pin FREQ/SYNC, then the internal oscillator synchronizes to this external cl ock frequency and the multitopol ogy regulator switches at the synchronized frequency. The synchronization frequency capture range is 250 kHz to 500 kHz. Figure 4 Oscillator and Synchronization Block Diagram and Simplified Application Circuit Figure 5 Synchronization Timing Diagram Oscillator Clock Frequency Detector FREQ / SYNC Multiplexer PWM Logic Gate Driver SWO RFREQVCLK Oscillator_BlkDiag_SyncFixedMode .vsd VSYNC t tSYNC,TR tSYNC,TR VSYNC,H VSYNC,L TSYNC = 1 / fSYNC tSYNC,PWH 4.5 V 0.5 V Oscillator_Timing.svg Ω − 3 112 105.3 10141 sFREQ s f R FREQ
Oscillator and Synchronization Datasheet 13 Rev. 1.1, 2012-04-11
6.2 Electrical Characteristics
All parameters have been tested at 25°C, unless otherwise specified. VIN = 24V, Tj = -40 ⋅C to +125 ⋅C, all voltages with respect to ground, posi tive current flowing into pin; (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. Oscillator:
6.2.1 Oscillator Frequency fFREQ 250 300 350 kHz RFREQ = 20kΩ
6.2.2 Oscillator Frequency
fFREQ 100 – 500 kHz 17% internal tolerance + external resistor tolerance
6.2.3 FREQ / SYNC Supply
IFREQ – – -700 µA VFREQ = 0 V Synchronization
6.2.5 Synchronization Frequency
fSYNC 250 – 500 kHz –
6.2.6 Synchronization Signal
VSYNC,H 3.0 – – V 1) 1) Synchronization of external PWM ON signal to falling edge
6.2.7 Synchronization Signal
VSYNC,L ––0 . 8 V 1)
6.2.8 Synchronization Signal
tSYNC,PWH 200 – – ns 1)
Datasheet 14 Rev. 1.1, 2012-04-11 ILD1150 Oscillator and Synchronization Typical Performance Characteristics of Oscillator Switching Frequency fSW versus Frequency Select Resistor to GND RFREQ/SYNC 100 200 300 400 500 600 0 1 02 03 04 05 06 07 08 0 RFREQ/SY NC [kohm] fFREQ [kHz] T j = 25 °C
Enable and Dimming Function Datasheet 15 Rev. 1.1, 2012-04-11
7 Enable and Dimming Function
7.1 Description
The enable function powers on or off the device. A valid logic low signal on enable pin EN/PWMI powers off the device and current consumption is less than 10 µA. A valid logic high enable signal on enable pin EN/PWMI powers on the device. The enable function features an integrated pull down resistor which ensures that the IC is shut down and the power switch is off in case the enable pin EN is left open. In addition to the enable function described above, the EN/PWMI pin detects a pulse width modulated (PWM) input signal that is fed through to an internal gate driver. T he internal gate driver outputs the same PWM signal on the PWMO pin to an external n-channel enhancement mode MOSFET for PWM dimming an LED load. PWM dimming an LED is a commonly practiced dimming method to prevent color shift in an LED light source. Moreover the PWM output function may also be used for to drive other types of loads besides LED. The enable and PWM input function share the same pin. Therefore a valid logic low signal at the EN/PWMI pin needs to differentiate between an enable power off signal or an PWM low signal. The device differentiates between an enable off command and PWM dimming signal by requir ing the signal at the EN/PWMI pin to stay low for a minimum of 8 ms. Figure 6 Block Diagram and Simplified Application Circuit Enable and LED Dimming EN / PWMI IN SWO IVCC 1LDO Enable / PWMI Logic PWMO EN_PWMI_BlockDiagram.svg Gate DriverMicrocontroller Gate Driver Enable Enable PWMI
Datasheet 16 Rev. 1.1, 2012-04-11 ILD1150 Enable and Dimming Function Figure 7 Timing Diagram Enable and LED Dimming
7.2 Electrical Characteristics
All parameters have been tested at 25°C, unless otherwise specified. VIN = 24V, Tj = -40 ⋅C to +125 ⋅C, all voltages with respect to ground, posi tive current flowing into pin; (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. Enable/PWM Input:
7.2.1 Enable/PWMI
VEN/PWMI,ON 3.0 – V –
7.2.2 Enable/PWMI
VEN/PWMI,OFF ––0 . 8 V –
7.2.3 Enable/PWMI Hysteresis VEN/PWMI,HYS 50 200 400 mV –
VEN/PWMI,ON VIVCC VIVCC,ON VPWMO VSWO VEN/PWMI,OFF tEN,OFF,DEL t t t t VIVCC,RTH Power Off Iq < 10 μA Power Off Delay TimeNormal SWO On PWMO On Dim PWMO Off SWO Off EN_PWMI_Timing.svg tPWMI,HTPWMI Dim PWMO Off SWO Off Power On Normal SWO On PWMO On Normal SWO On PWMO On TFREQ = 1 fFREQ tEN,START
Enable and Dimming Function Datasheet 17 Rev. 1.1, 2012-04-11
7.2.4 Enable/PWMI
IEN/PWMI,H ––3 0 µ A VEN/PWMI = 16.0 V
7.2.5 Enable/PWMI
IEN/PWMI,L –0 . 1 1µ A VEN/PWMI = 0.5 V
7.2.6 Enable Turn Off
tEN,OFF,DEL 8 1 01 2m s –
7.2.7 PWMI Min Duty Time tPWMI,H 4––µ s
7.2.8 Enable Startup Time tEN,START 100 – – µs
Gate Driver for Dimming Switch:
7.2.9 PWMO Gate Driver Peak
Sourcing Current1) IPWMO,SRC – 230 – mA VPWMO = 3.5V
7.2.10 PWMO Gate Driver Peak
Sinking Current1) IPWMO,SNK – 370 – mA VPWMO = 1.5V
7.2.11 PWMO Gate Driver
tR,PWMO – 50 100 ns CL,PWMO = 3.3nF; VPWMO = 1V to 4V
7.2.12 PWMO Gate Driver
tF,PWMO – 3 06 0n s CL,PWMO = 3.3nF; VPWMO = 1V to 4V
7.2.13 PWMO Gate Driver
VPWMO 4.5 – 5.5 V CL,PWMO = 3.3nF; Current Consumption
7.2.14 Current Consumption,
Iq_off ––1 0 µ A VEN/PWMI = 0.8 V; Tj ≤ 105C; VIN = 16V
7.2.15 Current Consumption,
Active Mode2) Iq_on ––7m A VEN/PWMI ≥ 4.75 V; IBO = 0 mA; VIN = 16V VSWO = 0% Duty 1) Not subject to production test, specified by design 2) Dependency on switching frequency and gate charge of external switches. VIN = 24V, Tj = -40 ⋅C to +125 ⋅C, all voltages with respect to ground, posi tive current flowing into pin; (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max.
Datasheet 18 Rev. 1.1, 2012-04-11 ILD1150 Linear Regulator
8 Linear Regulator
8.1 Description
The internal linear voltage regulator supplies the internal gate drivers with a typical voltage of 5 V and current up to 50 mA. An external output capacito r with low ESR is required on pin IVCC for stability and buffering transient load currents. During normal operation the external MOSFET switches will draw transient currents from the linear regulator and its output capacitor. Prope r sizing of the output capacitor must be considered to supply sufficient peak current to the gate of the external MOSFET switches. Integrated undervoltage protection for the external switching MOSFET: An integrated undervoltage reset threshold circui t monitors the linear regulator output voltage (V IVCC) and resets the device in case the output voltage falls belo w the IVCC undervoltage reset switch OFF threshold (V IVCC,RTH,d). The undervoltage reset threshold for the IVCC pin helps to protect the external switches from excessive power dissipation by ensuring the gate drive voltage is sufficient to enhance the gate of an external logic level n-channel MOSFET. Figure 8 Voltage Regulator Block Diagram and Simplified Application Circuit EN / PWMI IN IVCC Linear Regulator LinReg_BlckDiag.vsd Gate Drivers
Datasheet 19 Rev. 1.1, 2012-04-11
8.2 Electrical Characteristics
VIN = 24V, Tj = -40 ⋅C to +125 ⋅C, all voltages with respect to ground, posi tive current flowing into pin; (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. 8.2.1 Output Voltage VIVCC 4.6 5 5.4 V 6 V ≤ VIN ≤ 45 V 0.1 mA ≤ IIVCC ≤ 50 mA 8.2.2 Output Current Limitation ILIM 51 90 mA VIN = 13.5 V VIVCC = 4.5V 8.2.3 Drop out Voltage VDR 1.4 V IIVCC = 50mA 1) 1) Measured when the output voltage VCC has dropped 100 mV from its nominal value. 8.2.4 Output Capacitor CIVCC 0.47 – µF 2) 2) Minimum value given is needed for regulator stability; a pplication might need higher capacitance than the minimum. 8.2.5 Output Capacitor ESR RIVCC,ESR 0.5 Ω f = 10kHz
8.2.6 Undervoltage Reset Headroom VIVCC,HDRM 100 – – mV VIVCC decreasing
VIVCC - VIVCC,RTH,d 8.2.7 Undervoltage Reset Threshold VIVCC,RTH,d 4.0 – – V VIVCC decreasing 8.2.8 Undervoltage Reset Threshold VIVCC,RTH,i ––4 . 5 V VIVCC increasing
Datasheet 20 Rev. 1.1, 2012-04-11 ILD1150 Protection and Diagnostic Functions
9 Protection and Diag nostic Functions
9.1 Description
The ILD1150 has integrated circuits to diagnose and protect against output overvoltage, open load, open feedback and overtemperature faults. In case any of the four fault conditions occur the Status output ST will output an active logic low signal to communicate that a fault has occurred . During an overvoltage or open load condition the gate driver outputs SWO an d PWMO will turn off. Figure 11 illustrates the various ope n load and o pen feedback conditions. In the event of an overtemperature condition ( Figure 14) the integrated thermal shutdown function turns off the gate drivers and internal linear voltage regulator. The typical junction shutdown temperature is 175°C. After cooling down the IC will automa tically restart operation . Thermal shutdown is an integrated protection function designed to prevent immediate IC destruction and is not intended for continuous use in normal operation. Figure 9 Protection and Diagnostic Function Block Diagram Figure 10 Status Output Truth Table Output Overvoltage Open Load Overtemperature Protection and Diagnostic Circuit SWO and PWMO Gate Driver Off Linear Regualtor Off Input Output Pro_Diag_BlckDiag.vsd Open Feedback Input Undervoltage OR OR Output SWO PWMO IVCCST Input Overvoltage Open Load Overtemperature L LL Pro_Diag_TT.vsd Level* False True Condition H H or Sw *Sw* Active L LL H H or Sw *Sw* L LL Shutdown H H or Sw *Sw* *Note: Sw = Switching False = Condition does not exist True = Condition does exist False True False True Open Feedback L LL H H or Sw *Sw*False True Active Active Active Active Active Active
Datasheet 22 Rev. 1.1, 2012-04-11 ILD1150 Protection and Diagnostic Functions Figure 13 Status Output Timing Diagram ShutdownNormal Thermal Shutdown Overvoltage Open Load / Feedback Startup VIVCC VFBH -VFBL t VST t TJ t tSD tSD tSD t VREF,2 VREF,1 TJ,SD TJ,SD,HYST VIVCC,RTH,i VIVCC ,RTH,d
0.3 V Typ
t VOVFB ≥ VOVFB,TH Status Output Timing Diagram VOVFB < VOVFB,T L
Protection and Diagnostic Functions Datasheet 23 Rev. 1.1, 2012-04-11 Figure 14 Device overtemperature protection behavior VSWO t ILED t ΔΤ VEN/PWMI t H L Tj tTa TjSD TjSO Ipeak t Normal OperationDevice OFF Overtemp Fault ON Overtemp Fault ON Overtemp Fault ON Overtemp Fault VST and VIVCC VPWMO t
Datasheet 24 Rev. 1.1, 2012-04-11 ILD1150 Protection and Diagnostic Functions
9.2 Electrical Characteristics
All parameters have been tested at 25°C, unless otherwise specified. Note: Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuous repetitive operation. VIN = 24V, Tj = -40 ⋅C to +125 ⋅C, all voltages with respect to ground, posi tive current flowing into pin; (unless otherwise specified) Pos. Parameter Symbol Limit Values Unit Conditions Min. Typ. Max. Status Output: 9.2.1 Status Output Voltage Low VST,LOW ––0 . 4 V IST = 1mA
9.2.2 Status Sink Current Limit IST,MAX 2––m A VST = 1V
9.2.3 Status Output Current IST,HIGH ––1µ A VST = 5V
9.2.4 Status Delay Time tSD 81 0 1 2 m s –
Temperature Protection:
9.2.5 Over Temperature Shutdown Tj,SD 160 175 190 °C –
9.2.6 Over Temperature Shutdown
Tj,SD,HYST –1 5 –° C – Overvoltage Protection:
9.2.7 Output Over Voltage Feedback
VOVFB,TH 1.21 1.25 1.29 V –
9.2.8 Output Over Voltage Feedback
VOVFB,HYS 50 – 150 mV Output Voltage decreasing
9.2.9 Over Voltage Reaction Time tOVPRR 2 – 10 µs Output Voltage
9.2.10 Over Voltage Feedback Input
IOVFB -1 0.1 1 µA VOVFB = 1.25 V Open Load and Open Feedback Diagnostics
9.2.11 Open Load/Feedback
VREF,1,3 -100 – -20 mV VREF = VFBH - VFBL Open Circuit 1 or 3 9.2.12 Open Feedback Threshold VREF,2 0.5 – 1 V VREF = VFBH - VFBL Open Circuit 2
Application Information
Datasheet 25 Rev. 1.1, 2012-04-11 Note: The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. Figure 15 Boost to Ground Application Circuit - B2G (Boost configuration) Figure 16 Bill of Materials for B2G Application Circuit EN / PWMI COMP IN FBH FBL OVFB SWO SWCS FREQ / SYNC PWMO GND SGND IC1 ILD1150 ST IVCC CIN LBO DBO TSW RCS RFREQ RCOMP CCOMP CIVCC ROVH ROVL CBO RFB TDIM D10 VREF ILED IC2 Microcontroller (e.g. XC866) Digital Dimming Spread Spectrum 10STATUS RST VCC or VIVCC Classic Boost Setup: VOUT > VIN VIN = 4.75V to 45V PWMI PWMO LBO Reference Designator DBO Part NumberManufacturer CIN , CBO TDIM,TSW RCS RFB ROVH D1 - 10 ROVL CCOMP RCOMP CIVCC RFREQ, RST IC2 IC1 Osram LUW H9GP Vishay Coilcraft MSS1278T-104ML EEEFK1H101GPPanasonic Value White 100 uH 100 uF, 50V EPCOS Type LED Diode Capacitor Capacitor Capacitor IC IC Inductor Resistor Resistor Resistor Resistor Resistor Resistor Transistor EPCOS1uF , 6.3V MLCC CCNPZC 105KBW X7R Infineon ILD1150-- Infineon XC866-- Infineon IPG20N06S4L-26Dual N-ch enh. (60V, 20A) 820 mΩ, 1% Panasonic ERJ14BQFR82U 20 kΩ, 1% Panasonic ERJ3EKF2002V 33.2 kΩ, 1% Panasonic ERJ3EKF3322V 1 kΩ, 1% Panasonic ERJ3EKF1001V 50 mΩ, 1% Panasonic ERJB1CFR05U SS3H10Schottky, 3 A, 100 VR 10 nF X7R Panasonic10 kΩ, 1% ERJ3EKF1002V Quantity TransistorInfineon IPG20N10S4L-22alternativ: 100V N-ch, 35A 2 TransistorInfineon BSP318Salternativ : 60V N-ch, 2.6A 2
Datasheet 31 Rev. 1.1, 2012-04-11
10.1 Further Application Information
- For further information you may contact http://www.infineon.com/
- Application Note: ILD1150 / ILD115 1 DC-DC Multitopology Controller IC for Industrial Applications “Dimensioning and Stability Guideline - Theory and Practice”
Datasheet 32 Rev. 1.1, 2012-04-11 ILD1150
Revision History
1.0 2011-11-16 Initial Datasheet 1.1 2012-04-11 Page 3: RoHS Logo update Page 3: Topology update Application Information chapter update
Datasheet 33 Rev. 1.1, 2012-04-11 Figure 27 PG-SSOP-14 Green Product (RoHS compliant) To meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. Green products are RoHS-Compliant (i.e Pb-free finish on leads and suitable for Pb-free soldering according to IPC/JEDEC J-STD-020). PG-SSOP-14-1,-2,-3-PO V02 1 7 14 8 14x0.25±0.05 2) M0.15 DC A-B 0.65 C Stand Off 0 ... 0.1 (1.45) 1.7 MAX. 0.08 C A B 4.9±0.11) A-BC0.1 2x 1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Does not include dambar protrusion Bottom View ±0.23 ±0.22.65 0.2 ±0.2 D 6 M D 8x 0.64±0.25 3.9±0.11) 0.35 x 45˚ 0.1 CD +0.06 0.19 8˚ MAX. Index Marking Exposed Diepad PG-SSOP-14 For further package information, please visit our website: http://www.infineon.com/packages. Dimensions in mm
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