IL9270

IL9270 INTEGRAL | Alldatasheet

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High-Performance Silicon-Gate CMOS IL9270

ORDERING INFORMATION

TA = -10° to 70° C The IL9270N/D is a com plete DTMF receiver integrating both the bandsplit filter and d igital d ecoder fu nctions. Th e filter sectio n u ses switched capacitor techniques for high- and low-group filters and dial- tone rejection. Digital counting techniques are employed in the decoder to detect and decode al l 16 DTMF tone-pairs into a 4-bit code. External component count i s m inimized by on-chi p provi sion of a differential input amplifier, clock-oscillator and latched 3-state bus interface.

• Complete receiver in an 18-pin package.
• Excellent performance.
• CMOS, single 5 volt operation. D SUFFIX SOIC
• Minimum board area.
• Central office quality.
• Low power consumption. LOGIC DIAGRAM PIN 9 = GND PIN 18 = VCC PINS 5,6 = NO CONNECTION PIN ASSIGNMENT * Connect to GND

ESt 16 Early st eering out put. Present s a l ogic high immediately when the digital algorithm detects a recognizable tone-p air (signal condition). Any m omentary loss of signal condition will cause ESt to return to a logic low. GS 3 Gain Select. Gives access to output of front-end differential am plifier for connection of feedback resistor. IC 5,6 Internal Connection. Must be tied to GND. IN+ 1 Non-Inverting Input Connections to the front-end IN- 2 Inverting Input differential amplifier. C1 7 Clock Input 3.579545 MHz crystal connected between C2 8 Clock Output these pins completes internal oscillator. Q1-Q4 11-14 3-state data outputs. When enabled by OE, provide the code corresponding to the last valid tone-pair received. StD 15 Delayed steering output. Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt. St/GT 17 Steering i nput/guard t ime out put (bi -directional). A vol tage great er t han VTSt, detected at St causes the device to register the detected tone-pair and updat e the output latch. A voltage less than VTSt frees the device to accept a new tone-pair. The GT output acts to reset the external steerin g tim e-constant; its state is a function of ESt and the voltage on St. OE 10 3-state out put enabl e (i nput). Logi c hi gh enabl es t he out puts Q1-Q4. Internal pull-up. VCC 18 Positive power supply, +5 V. VREF 4 Reference vol tage out put, nom inally V CC /2. May be used t o bi as t he i nputs at mid-rail. GND 9 Negative power supply, normally connected to 0 V. FUNCTIONAL DESCRIPTION The IL9270 monolithic DTMF receivers offer small size, low power consumption and hi gh perform ance. The architecture consists of a b andsplit filter sectio n, which separates the high and low tones of a receiver pair, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. Filter Section Separation of t he l ow-group and hi gh-group t ones i s achieved byapplying the dual-tone signal to the inputs of two filters - a sixth order fo r the high group and an eight order for t he l ow group. The band-wi dths of which correspond t o t he bands encl osing the low-group and high-group tones (see Figure 1). The filter section also incorporates not ches at 350 Hz and 440 Hz for exceptional d ial-tone rej ection. Each filter output is followed by a second order swi tched-capacitor section which smooths the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hy steresis t o prevent det ection of unwanted low- level si gnals and noi se; t he outputs of the comparators provide ful l-rail l ogic swi ngs at t he frequenci es of the incoming tones.

The decoder uses di gital count ing techniques to determine th e freq uencies o f th e lim ited to nes an d to verify that t hey correspond t o st andard DTM F frequencies. A complex averagi ng al gorithm prot ects against tone si mulation by ext raneous si gnals, such as voice, whi le provi ding t olerance t o sm all frequency deviations and vari ations. This averaging algorithm has been devel oped t o ensure an opt imum com bination of immunity to “talk-off” and tolerance to the presence of interfering signals (“third tones”) and noi se. W hen t he detector recogni zes t he si multaneous presence of two valid tones (referred t o as “si gnal condi tion” i n som e industry specifications), it raises the “early steering” flag (ESt). An y su bsequent lo ss o f sig nal-condition will cause Est to fall. Steering Circuit Before registration of a dec oded tone-pair, the receiver checks for a val id si gnal duration (referred to as “character-recognition-condition”). This check is performed by an external RC time-constant dri ven by ESt. A logic high on ESt causes VC (see Figure 2) to rise as the capacitor discharges. Provided signal-condition is maintained (ESt rem ains high) for the validation period (tGTP), V C reaches the threshold (V TSt) of the steering logic to register the tone-pair, latching its corresponding 4-bit code (see Fi gure 3) i nto t he out put l atch. At t his point, the GT out put is activated and dri ves VC to VCC. GT continues to drive high as long as ESt remains high. Finally after a sh ort d elay to allo w th e o utput latch to settle, the “delayed-steering” output flag, StD, goes high, signaling that a received tone -pair has been registered. The cont ents of t he out put l atch are made available on the 4-bit output bus by raising the 3-st ate cont rol input (OE) to a logic high. The st eering ci rcuit works i n reverse to validate the interdigit pause between signals. Thus, as wel l as reject ing si gnals t oo short t o be considered valid, the recei ver will tolerate signal interruptions (“drop-out”) too short t o be consi dered a valid pause. The facility, to gether with the capability of selecting th e steerin g tim e-constants ex ternally, allows the designer to tailor performance to meet a wide variety of system requirements. Guard Time Adjustment In many situations not requiring independent selection of receive and pause, the simple steering circuit of Figure 2 is applicable. Component values are chosen according to the following formula: tREC = tDP + tGTP tID = tDA + tGTA The value of t DP is a param eter of the device and tREC is the m inimum si gnal durat ion t o be recognized by the receiver. A value for C of 0.1 µF i s recom mended for most appl ications, l eaving R to be selected by the designer. For example, a suitable value of R for a t REC of 40 ms would be 300 k. Different st eering arrangem ents m ay be esed to select independently the guard-times for tone-present (tGTP) and tone-absent (t GTA). This m ay be necessary to m eet system specifications which place both accept and reject limits on both tone duration and inter-digital pause. Guard-time adjustment also allows the designer to tailor system parameters such as t alk-off and noi se immunity. Increasing t REC im proves talk-off perform ance, since it reduces the probability that tones sim ulated by speech will m aintain signal condition for long enough to be registered. On the other hand, a relatively short tREC with a l ong t DO would be appropri ate for ext remely noi sy environments where fast acquisition time and i mmunity to drop-outs would be requirements. Design information for guard-time adjustment is show in Figure 4. Input Configuration The i nput arrangem ent of t he IN9270 provi des a differential-input operational amplifier as wel l as a bias source (VREF) which is used to bias the inputs at mid-rail. Provision is made for connect ion of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a si ngle-ended confi guration, t he i nput pi ns are connected as shown i n Fi gure 5 wi th t he op-am p connected for uni ty gai n and V REF bi asing t he input at 1/2VCC. Figure 6 shows t he di fferential confi guration, which permits the adjustment of gain with the feedback resistor R5.

MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.3 to +6.0 V VIN DC Input Voltage (Referenced to GND) -0.3 to VCC +0.3 V IIN DC InputCurrent, per Pin 10 mA PD Power Dissipation in Still Air, Plastic DIP** 500 mW Tstg Storage Temperature -65 to +150 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. ** Derating: -10 mW/°C from 65°C to 70°C. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 4.75 5.25 V VIN DC Input Voltage (Referenced to GND) 1.5 3.5 V TA Operating Temperature -10 +70 °C PO Power Consumption ( f = 3.579 MHz, VCC = 5 V) - 45 mW tr, tf Input Rise and Fall Time 0 110 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions m ust be taken to avoid applications of any voltage highe r than maximum rated voltages to this high-impedance ci rcuit. For proper operat ion, V IN and V OUT should be const rained t o t he range GND ≤(VIN or VOUT)≤VCC. Unused inputs must always be t ied to an appropri ate logic voltage level (e.g., ei ther GND or VCC). Unused outputs must be left open.

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND, VCC = 5 V ± 5%, TA = -10 to +70°C) Guaranteed Limits Symbol Parameter Test Conditions Min Typ Max Unit VIH Minimum High-Level Input Voltage VOUT =5 V 3.6 V VIL Maximum Low-Level Input Voltage VOUT =5 V 1.4 V VOH Minimum High-Level Output Voltage No Load 4.97 V VOL Maximum Low-Level Output Voltage No Load 0.05 V IIN Maximum Input Leakage Current VIN=VCC or GND ±0.1 µA ISO Maximum Pull Up (Source) Current OE = 0 V 24 µA IOL Minimum Output-Low (Sink) Current VOUT =0.4 V 0.8 mA IOH Minimum Output-High (Source) Current VOUT =4.6 V 0.35 mA ICC Maximum Quiescent Supply Current (per Package) VIN =VCC 11 mA VTSt Steering Threshold Voltage 2.2 2.5 V RIN Input Impedance (Signal Inputs 1,2) @ 1 KHz 8 MΩ VREF Output Voltage No Load 2.4 2.8 V ROR Output Resistance 10 kΩ IOZ Maximum Three-State Leakage current Output in High- Impedance State VIN =VIL VOUT=VCC or GND ±0.1 µA

Symbol Parameter Test Conditions Typ Unit IN Input Leakage Current GND< VIN < VCC ±100 nA RIN Input Resistance 10 MΩ VOS Input Offset Voltage ±25 mV PSRR Power Supply Rejection 1 KHz 60 dB CMRR Common Mode Rejection -3.0 V < VIN < 3.0 V 60 dB AVOL DC Open Loop Voltage Gain 65 dB fC Open Loop Unity Gain Bandwidth 1.5 MHz VO Output Voltage Swing RL ≥100 KΩ to GND 4.5 VPP CL Tolerable Resistive Load (GS) 100 pF RL: Tolerable Resistive Load (GS) 50 KΩ VCM Common Mode Range No Load 3.0 VPP AC ELECTRICAL CHARACTERISTICS (All Voltages referenced to GND. VCC = 5.0 V, GND = 0 V, TA = -10 to +70°C, FCLK = 3.579545 Mhz, using test circuit of Figure 5) Parameter Guaranteed Limits Min Typ Max Unit Notes SIGNAL CONDITION Valid Input Signal MIN -29 dBm 1,2,3,5,6,9 Level (each tone of 27.5 m VRMS 1,2,3,5,6,9 composite signal) MAX +1 dBm 1,2,3,5,6,9 883 m VRMS NON-ACCEPT LEVEL Freq. Deviation Accept Limit ±1.5% ±2 Hz Nom. 2,3,5,9 Freq. Deviation Reject Limit ±3.5% Nom. 2,3,5 Third Tone Tolerance -2.5 dB 2,3,4,5,7,9,10 Dial Tone Tolerance +18 dB 2,3,4,5,8,9,10

Notes: 1. dBm = decibels above or below a reference power of 1 mW into a 600 Ω load.

1. Digit sequence consists of all 16 DTMF tones.
2. Tone duration = 40 ms, Tone pause = 40 ms.
3. Nominal DTMF frequencies are used.
4. Both tones in the composite signal have an equal amlitude.
5. Tone pair is deviated by ±1.5% ±2 Hz.
6. Bandwidth limited (3 KHz) Gaussian Noise.
7. The precise dial tone frequencies are (350 Hz and 440 Hz) ±2%.
8. For an error rate of less than 1 in 10,000.
9. Referenced to the lowest level frequency component in DTMF signal.

Figure 1. Typical Filter Characteristic

Figure 6. Differential Input Configuration A. Short tone bursts: detected. Tone duration is invalid. B. Tone #n is detected. Tone duration is valid. Decoded to outputs. C. End of tone #n is detected and validated. D. 3 State outputs disabled (high impedance). E. Tone #n+1 detected. Tone duration is valid. Decoded to outputs. F. Tristate outputs are enabled. Acceptable drop out of tone #n+1 does not register at outputs. G. End of tone #n+1 is detected and validated.

(MS - 001AC) Symbol MIN MAX A 22.35 23.37 B 6.1 7.11 C 5.33 D 0.36 0.56 F 1.14 1.78 G H J 0° 10° K 2.92 3.81 NOTES: L 7.62 8.26 1. Dimensions “A”, “B” do not include mold flash or protrusions. M 0.2 0.36 Maximum mold flash or protrusions 0.25 mm (0.010) per side. N 0.38 D SUFFIX SOIC (MS - 013AD) Symbol MIN MAX A 10.1 10.5 B 7.4 7.6 C 2.35 2.65 D 0.33 0.51 F 0.4 1.27 G H NOTES: J 0° 8° 1. Dimensions A and B do not include mold flash or protrusion. K 0.1 0.3 for A; for B ‑ 0.25 mm (0.010) per side. P 10 10.65 R 0.25 0.75 2.54 7.62 1.27 Dimension, mm Dimension, mmA BH C K C M J F M G D R x 45 SEATING PLANE 0.25 (0.010) M T -T- L H M J A B F G D SEATING PLANE N K 0.25 (0.010) M T -T- C