IL6083 IKSEMICON | Alldatasheet

Document overview

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Technical content

Features

  • Protection Against Short-circuit, Load Dump Overvoltage and Reverse VS
  • Duty Cycle 18 to 100% Continuously
  • Internally Reduced Pulse Slope of Lamp's Voltage
  • Interference and Damage Protection
  • Charge-pump Noise Suppression
  • Ground-wire Breakage Protection IL6083N DIP-8 TA = –40 ~ +110°С Pin Configuration Figure 1. Pin Symbol Pin Description

01 Vs Supply voltage

02 GND IC ground

03 Vi Control input (duty cycle)

04 Osc Oscillator

05 Delay Short-circuit protection delay

06 Sense Current sensing

08 Output Output

Rev. 00

Block diagram with External Circuit Figure 2. Maximum and Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. T his is a stress rating only and functional operation of the device at these or any other conditions bey ond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Ratings Absolute Maximum Ratings Parameter, Symbol, Unit min max min Max Supply voltage Vbatt, V 9.0 25 32.5 Storage temperature Tstg, oС -55 +125 Ambient operation temperature range TA , oC -40 +110 -55 +125 Junction maximum temperature TJ(max), oC +150 Temperature resistance junction – ambient Rth j-a, =120oC/W Rev. 00

Pin 1, Supply Voltage, VS or VBatt Overvoltage Detection Stage 1 If overvoltages of VBatt > 20 V (typically) occur, the external transistor is switched off, and switched on again at VBatt < 18.5 V (hysteresis). Stage 2 If VBatt > 28.5 V (typically), the voltage limit ation of the IC is reduced from V S = 26 V to 20 V. The gate of the external transistor remains at the potential of t he IC ground, thus producing voltage sharing between FET and lamps in the event of overvoltage pulses (e.g. , l oad dump). The short - circuit protection is not in operation. At VBatt approximately < 23 V, the overvoltage detection stage 2 is switched off. Thus, during overvoltage detection stage 2, the lamp voltage Vlamp is calculated as follows: VLamp = VBatt - VS - VGS VS = supply voltage of the IC at overvoltage detection stage 2 VGS = gate - source voltage of the FET Undervoltage Detection In the event of voltages of approximately VBatt < 5.0 V, the external FET is switched off and the latch for short-circuit detection is reset. A hysteresis ensures that the FET is switched on again at approximately VBatt ≥ 5.4 V. Pin 2, GND Ground-wire Breakage To protect the FET in the case of ground-wire breakage, a 1 M Ω resistor between gate and source is recommended to provide proper switch-off conditions. Pin 3, Control Input The pulse width is controlled by means of an external potentiometer (47 k Ω). The characteristic (angle of rotation/duty cycle) is linear. The duty cycle can be vari ed from 18 to 100%. It is possible to further restrict the duty cycle with the resistors R1 and R2 (see Figure 4). In order to reduce the power dissipation of the FET and to increase the lifetime of the lamps, the IC automatically reduces the maximum duty cycl e at pin 8 if the supply voltage exceeds V2 = 13 V. Pin 3 is protected against short-circuit to VBatt and ground (VBatt ≤ 16.5 V). Pin 4, Oscillator The oscillator determines the frequency of the output vo ltage. This is defined by an external capacitor, C2. It is charged with a constant current, I, until the upper switching threshold is reached. A second current source is then activated which taps a double current, 2 x I, from the charging current. The capacitor, C 2, is thus discharged at the current, I, until the lower switching threshold is reached. The second source is then switched off again and the procedure starts once more. Rev. 00

VT100 = High switching threshold (100% duty cycle) VT100 = VS x α 1 = (VBatt - IS x R3) x α 1 VT<100 = High switching threshold (< 100% duty cycle) VT<100 = VS x α2 = (VBatt - IS x R3) x α 2 VTL = Low switching threshold VTL = VS x α 3 = (VBatt - IS x R3) x α 3 where α 1, α 2 and α 3 are fixed values Calculation Example The above mentioned threshold voltages are calculated for the following values given in the data sheet. VBatt = 12 V, IS = 4 mA, R3 = 150 Ω, α 1 = 0.7, α 2 = 0.67 and α 3 = 0.28 VT100 = (12 V - 4 mA x 150 Ω) x 0.7 ≈ 8 V VT<100 = 11.4 V x 0.67 = 7.6 V VTL = 11.4 V x 0.28 = 3.2 V Oscillator Frequency 3 cases have to be distinguished 1. f1 for duty cycle = 100%, no slope reduction with capacitor C4 (see Figure 4) 2. f2 for duty cycle < 100%, no slope reduction with capacitor C4 . For a duty cycle of less than 100%, the oscillator frequency, f, is as follows: 3. f3 with duty cycle < 100% with slope reduction capacitor C4 (see “Output Slope Control”) Electrical parameters are given for temperature range from minus 40 to + 110° С and Vbatt. From 9 to 16,5V. Operation is guaranteed for Vbatt from 6 to 9V. All electr ical parameters are specified relatively to “common” output (02). By selecting different values of C2 and C4, it is possible to have a range of oscillator frequencies from 10 to 2000 Hz as shown in the data sheet. Rev. 00

To damp oscillation tendencies, a resistance of 100Ω in series with capacitance C4 is recommended.

  • “On-board” radio reception according to VDE 0879 part 3/4.81
  • Test conditions refering to Figure 3
  • Application circuit according to Figure 1 or Figure 4
  • Load: nine 4 W lamps in parallel
  • Duty cycle = 18%
  • VBatt = 12 V
  • fOsc = 100 Hz

Figure 3. Voltage Spectrum of On-board Radio Reception

Pins 5 and Pin 6, Short-circuit Protection and Current Sensing Short-circuit Detection and Time Delay, td The lamp current is monitored by means of an external shunt resistor. If the lamp current exceeds the threshold for the short-circuit detection circuit (VT2 ≈ 90 mV), the duty cycle is switched over to 100% and the capacitor C5 is charged by a current source of Ich - Idis. The external FET again is switched off after the cut- off threshold (V T5) is reached. Switching on the FET again is possible after a power-on reset only. The current source, Idis, ensures that the capacitor C5 is not charged by parasitic currents. The time delay, td, is calculated as follows: Current Limitation The lamp current is limited by a control amplifier to protect the external power transistor. The voltage drop across the external shunt resistor ac ts as the measured variable. Current limitation takes place for a voltage drop of VT1 ≈ 100 mV. Owing to the difference VT1 - VT2 ≈ 10 mV, it ensures that current limitation occurs only when the short-circuit detection circuit has responded. After a power-on reset, the output is inactive for half an oscillator cycle. During this time, the supply voltage capacitor can be charged so that current limitation is guaranteed in the event of a short-circuit when the IC is switched on for the first time. Pins 7 and 8, Charge Pump and Output Pin 8 (output) is suitable for controlling a power MOSF ET. During the active integration phase, the supply current of the operational amplifier is mainly supplied by the capacitor C 3 (bootstrapping). In addition, a trickle charge is generated by an integrated oscillator (f7 ≈ 400 kHz) and a voltage doubler circuit. This permits a gate voltage supply at a duty cycle of 100%. Rev. 00

Table of Electrical Parameters Tamb = -40°C to +110°C, VBatt = 9 to 16.5 V, (basic function is guaranteed between 6.0 V to 9.0 V) reference point ground, unless otherwise specified (see Figure 2). All other values refer to pin GND (pin 2). Rate Parameter Symbol Test Conditions min Typ. max Unit Pin 1 Current Consumption Is 7.9 mA Supply voltage Vbatt Overvoltage Detection, stage 1 25 V Stabilized voltage VS Is=10mA 24.5 27.0 V Switching on 4.4 5.0 5.6 Level of the lowered battery voltage Vbatt Switching off 4.8 5.4 6.0 V Battery Overvoltage Detection Switching on 18.3 20.0 21.7Stage 1 Vbatt Switching off 16.7 18.5 20.3 V Stage 2 Switching on 25.5 28.5 32.5 Detection stage 2 Vbatt Switching off 19.5 23.0 26.5 V Stabilized voltage VS Is=30mA 18.5 20.0 21.5 V Short- Circuit Protection, Pin 6 short-circuit current limitation VT1 VT1 = VS-V6 85 100 120 mV VT2 VT2 = VS-V6 75 90 105 Short circuit voltage VT1 -VT2 VT2 = VS-V6 3 10 30 mV Delay Timer Short-circuit Detection, Vbatt = 12.0V, Pin 5 Switch off threshold VT5 VT5 = VS-V5 10.2 10.4 10.6 V Charge current Ich 13 uA Dicharge current Idis 3 uA Capacitance current I5 I5 = Ich-Idis 5 10 15 mA Voltage doubler, Pin 7 Voltage V7 Duty cycle 100% 2VS V Oscillator frequency f7 280 400 520 kHz 26.0 27.5 30.0Internal voltage limitation V7 I7=5mA (whichever is lower) VS+14 VS+15 VS+16 V dV8/dt =α4 dV4/dt 53 63 72 Edge rate α4 dV8/dtmax 130 V/ms Rev. 00

Rate Parameter Symbol Test Conditions min Type max Unit Gate Output , Pin 8 Low level 0.35 0.70 0.95 Vbatt = 16.5V Tamb = 110° C, R3=150Ω 1.5*Voltage V8 High level, duty cycle 100% V7 V V8 = low level 1.0 Current, I8 V8 = high level, I7 >|I8| -1.0 mA Min: С2=68nF 15 18 21 Max: Vbatt ≤12.4V, 100 Duty cycle tpмин /T Vbatt = 16.5V, С 2=68nF 65 73 81 Oscillator, Pin 4 Frequency f 10 2000 Hz 0.68 0.7 0.72 0.65 0.67 0.69 Threshold cycle Upper Lower α3 0.26 0.28 0.3 Oscillator current ± IOSC Vbatt=12.0 V 34 45 54 uA Frequency f С4 is open, С2=68nF, duty cycle=50% 56 75 90 Hz * Reference point is battery ground Rev. 00

Figure 4. Application Circuit

(MS – 001BA) Symbol MIN MAX A 8.51 10.16 B 6.1 7.11 C 5.33 D 0.36 0.56 F 1.14 1.78 G H J 0° 10° K 2.92 3.81 NOTES: L 7.62 8.26 1. Dimensions “A”, “B” do not include mold flash or protrusions. M 0.2 0.36 Maximum mold flash or protrusions 0.25 mm (0.010) per side. N 0.38 Dimension, mm 2.54 7.62 L H M J A B F G D SEATING PLANE N K 0.25 (0.010) M T -T- C Rev. 00