IL5851 INTEGRAL | Alldatasheet

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Technical content

The IL5851 is a m onolithic CMOS inte grated circuit which uses an inexpensive RC o scillator fo r its freq uency referen ce and provides all the features required for implementing a pulse dialer with 32 digit redial.

ORDERING INFORMATION

TA = -20° to 70° C

  • Wide operating voltage range (2.0~6.0V)
  • Low power dissipation
  • Use either a standard 2 of 7 matrix keyboard with negative true common or the inexpensive form A-type keyboard
  • Make/Break ratio can be selected
  • Redial with * or #
  • Continuous MUTE
  • Power up clear circuitry on chip
  • 10 pps/20 pps can be selected PIN ASSIGNMENT LOGIC DIAGRAM PIN 1 = VCC PIN 6 = GND

VCC 1 Positive supply pin. The vol tage on t his pi n i s m easured rel ative t o Pi n 6 and i s suppl ied from a 150µA current source. Thi s vol tage shoul d be regul ated t o l ess t han 6.0 volts using on external form or regulation. VREF 2 The VREF out put provi des reference voltage that track s in ternal parameters of t he IL5851N. VREF provides a negative voltage reference to the VCC supply. Its magnitude will be approximately 0.6 volt higher than the minimum operat ing vol tage of each particular IL5851N. The t ypical appl ication woul d be t o connect the V REF pin to the GND pin (Pin 6). The suppl y t o the VCC pi n (Pin 1) shoul d t hen be regul ated to 150µA (IOP max). with this amount of supply current , operat ion of the IL5851N is guaranteed. The in ternal circu it o f the VREF function is shown in Figure 1 with its associated I-V characteristic Row1-Row4, Col1-Col4 3,4,5,13, 14,15,16 Keyboard inputs. The IL5851N incorporates an innovative keyboard scheme that allows either the standard 2-of-7 keyboard with negative common or the inexpensive single contact (form A) keyboard to be used. A valid key entry is defined by either a single row being connected to a single column or GND being simultaneously presented to both a single row and column. When in the on-hook mode, the row and column inputs are held high and no keyboard inputs are accepted. When off-hook, the keyboard is completely static until the initial valid key input is sensed. The oscillator is then enabled and the rows and columns are scanned alternately (pulled high, then low) to verify the varied input. The input must remain valid for 10msec of debounce time to be accepted. Form A type keyboard 2 of 7 keyboard (negative common) 2 of 7 keyboard Electronic input GND 6 Negative supply

pin is connected to the common part in general applications. RC1-RC3 7,8,9 Oscillator The IL5851N contains on-chip inverters to provide oscillator which will operate with a minimum external components. Following figure shows the on-chip configuration with the necessary external components. Optimum stability occurs with the ration K=RS/R equal to 10 The oscillator period is given by: T=RC(1.386+(3.5KCS)/C-(2K/(K+1)) in (K/(1.5K + 0.5)) Where CS is the stray capacitance on Pin 7. Accuracy and stability will be enhanced with this capacitance minimized. PPS 10 10/20pps Select Connecting this pin to GND (pin 6) will select an output pulse rate of 10pps. Connecting the pin VCC (pin 1) will select an output pulse rate of 20pps. M/B 11 Make/break Select The M ake/Break pi n cont rols t he M ake/Break rat io of t he pul se out put. The make/Break ratio is controlled by connection VCC or GND to this pin as shown in the following table. Input Make Break VCC (Pin1) 33.4% 66.6% GND(PIn 6) 40% 60% ____ Mute

12 Mute Output

The mute output is an open-drain N-Channel transistor designed to drive external bipolar transistor. This circuitry is usually used to mute the receiver during outpulsing. As shown in Fig. 2 the IL5851N m ute out put t urns on (pul ls t o t he V GND-supply) at t he beginning of the predigital pause and turns off (goes to an open circuit) following the last break. The delay from the end of the last b reak until the mute output turns off is m ute overlap and is specified as tMO. OH 17 ON-HOOK/TEST This pin detects the state of t he hook swi tch contact “OFF HOOK” corresponds to VSS condition. ÖN HOOK”corresponds to VDD condition. When outpulsing in this mode, which can be up to 300m sec, is completed, the circuit is deactivated and will require current only necessary to sustain the memory and power-up-clear detect circuitry (refer to the electrical specifications). Upon retuning off-hook, a negative transis tion on the mute output will insure the speech network is connected to the line. If the first key entry is either a * or #, the

number sequence stored on-chip will b e outpulsed. Any other valid key entries will clear the memory and outpulse the new number sequence. PULSE

18 Pulse Output

The Pulse output is an open drain N-channel transistor designed to drive external bipolar transistor. These transistor would normally be used to pulse the telephone line by disconnecting and connect ing the network. The IL5851N pul se output is an open circuit during make and pulls to the GND supply during break. MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.3 to +6.2 V VIN DC Input Voltage (Referenced to GND) -0.3 to VCC +0.3 V PD Power Dissipation in Still Air ** 500 mW Tstg Storage Temperature -40 to +125 °C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. ** Derating: -10 mW/°C from 65°C to 70°C. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V VIN DC Input Voltage (Referenced to GND) 0 VCC V TA Operating Temperature -20 +70 °C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions m ust be taken to avoid applications of any voltage highe r than maximum rated voltages to this high-impedance ci rcuit. For proper operat ion, V IN and V OUT should be const rained t o t he range GND ≤(VIN or VOUT)≤VCC. Unused inputs must always be t ied to an appropri ate logic voltage level (e.g., ei ther GND or VCC). Unused outputs must be left open.

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND, VCC = 2.0 V to 6.0V, TA = -20 to +70°C, FOSC=2.4KHz) Guaranteed Limits Symbol Parameter Test Conditions Min Typ Max Unit VIH Input High Voltage 0.8VCC VCC V VIL Input Low Voltage 0 0.2VCC V VDR Minimum Memory Retention Voltage 1.0 V IOL Output Leakage Current VCC=6.0V , MUTE,PULSE=6.0V 1 µA IOL1 Minimum Output current (MUTE,PULSE) VO=0.8V,VCC=2.5V 0.5 mA IOL2 Minimum Output current (MUTE,PULSE) VO=0.8V,VCC=3.5V 1.7 mA IOD Operating Current All output under no load, VCC=2.0V 150 µA ISD Maximum Standby Current VCC=2.5V VIH=2.5V 1 µA IREF Minimum Reference Current VCC=6.0V 1 µA AC ELECTRICAL CHARACTERISTICS (FOSC= 2.4 KHz, VCC=2.0 to 6.0 V, TA=-20 to +70°C ) Symbol Parameter Test Conditions Guaranteed Limit Unit Min. Typ. Max TKD Minimum Valid Key Entry Time 20 mS TOH On Hook Time Required to Clear Memory (Figure 2) 300 mS TIDR Inter Digital Pause (Figure 2) 800 mS ∆f Frequency Sability ±10 % TMO Recovery Time, MUTE to PULSE (Figure 2) 800 mS TPDP Maximum Pre- digital Pause (Figure 2) 30 mS TDP Maximum Delay Time, Key Input to PULSE (Figure 2) 50 mS M/B Make/Break 1/2 M/B=VCC Ratio 2/3 M/B=GND

(MS - 001AC) Symbol MIN MAX A 22.35 23.37 B 6.1 7.11 C 5.33 D 0.36 0.56 F 1.14 1.78 G H J 0° 10° K 2.92 3.81 NOTES: L 7.62 8.26 1. Dimensions “A”, “B” do not include mold flash or protrusions. M 0.2 0.36 Maximum mold flash or protrusions 0.25 mm (0.010) per side. N 0.38 2.54 7.62 Dimension, mm L H M J A B F G D SEATING PLANE N K 0.25 (0.010) M T -T- C