IL44608

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2011, February, Rev. 01 External Components Reliable and Flexible SMPS Controller

DESCRIPTION

The IL44608N is a high performance voltage mode controller designed for off–line converters. This high voltage circuit that inte- grates the start–up current source and the oscillator capacitor, re- quires few external components while offering a high flexibility and reliability. The device also features a very high efficiency stand–by man- agement consisting of an effective Pulsed Mode operation. This technique enables the reduction of the stand–by power consumption to approximately 1.0 W while delivering 300 mW in a 150 W SMPS.

• Integrated Start–Up Current Source
• Lossless Off–Line Start–Up
• Direct Off–Line Operation
• Fast Start–Up General Features
• Flexibility
• Duty Cycle Control
• Under-voltage Lockout with Hysteresis
• On Chip Oscillator Switching Frequency 40, 75, or 100 kHz
• Secondary Control with Few External Components Protections
• Maximum Duty Cycle Limitation
• Cycle by Cycle Current Limitation
• Demagnetization (Zero Current Detection) Protection
• “Over VCC Protection” Against Open Loop
• Programmable Low Inertia Over Voltage Protection against Open Loop
• Internal Thermal Protection SMPS Controller
• Pulsed Mode Techniques for a Very High Efficiency Low Power Mode
• Lossless Startup
• Low dV/dT for Low EMI Radiations

Ordering Information

Device Switching Frequency Package IL44608N40 40 kHz Plastic DIP–8 IL44608N75 75 kHz Plastic DIP–8 IL44608N100 100 kHz Plastic DIP–8 PACKAGE PDIP-8 IL44608 Pin Connection

1 Demag

configuration status and the 120 μA level to detect an Over Voltage status called Quick OVP.

2 Isense

current detection can be performed during the SMPS stand–by mode.

3 Control

duty cycle during the Stand–by mode. 4 Ground This pin is the ground of the primary side of the SMPS. 5 Driver The current and slew rate capability of this pin are suited to drive Power MOSFETs.

6 VСС

tage level of 10 V creates a disabling condition called Latched Off phase. 7 This pin is to provide isolation between the Vi pin 8 and the VCC pin 6. rapid charge of the VCC capacitor. As soon as the IC starts–up, this current source is disabled. Figure 1. Representative Block Diagram

2011, February, Rev. 01 MAXIMUM RATINGS Rating Symbol Value Unit Total Power Supply Current ICC 30 mA Output Supply Voltage with Respect to Ground VCC 16 V All Inputs except Vi Vinputs –1.0 to +16 V Line Voltage Absolute Rating Vi 500 V Recommended Line Voltage Operating Condition Vi 400 V Power Dissipation and Thermal Characteristics Maximum Power Dissipation at TA = 85°C Thermal Resistance, Junction–to–Air PD RQJA 600 100 mV ºC/W Operating Junction Temperature TJ 150 ºC Operating Ambient Temperature TA –25 to +85 ºC * Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condi tions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS(VCC = 12 V, for typical values TA = 25°C, for min/max values TA = –25°C to +85°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OUTPUT SECTION Output Resistor Sink Resistance Source Resistance ROL ROH 5.0 8.5 Ω Output Voltage Rise Time (from 3.0 V up to 9.0 V) (Note 1.) tr - 50 - ns Output Voltage Falling Edge Slew–Rate (from 9.0 V down to 3.0 V) (Note 1.) tf - 50 - ns CONTROL INPUT SECTION Duty Cycle @ Ipin3 = 2.5 mA d2mA - - 2.0 % Duty Cycle @ Ipin3 = 1.0 mA d1mA 36 - 48 % Control Input Clamp Voltage (Switching Phase) @ Ipin3 = –1.0 mA 4.75 - 5.25 V Latched Phase Control Input Voltage (Stand–by) @ Ipin3 = +500 _A VLP–stby 3.4 - 4.3 V Latched Phase Control Input Voltage (Stand–by) @ Ipin3 = +1.0 mA VLP–stby 3.4 - 3.7 V CURRENT SENSE SECTION Maximum Current Sense Input Threshold VCS–th 0.95 - 1.05 V Input Bias Current IB–cs -1.8 - 1.8 μA Stand–By Current Sense Input Current ICS–stby 180 - 220 μA Start–up Phase Current Sense Input Current ICS–stup 180 - 220 μA Propagation Delay (Current Sense Input to Output @ VTH T MOS = 3.0 V) Leading Edge Blanking Duration IL44608N 40 TPLH(In/Out) TLEB 220 480 ns ns Leading Edge Blanking Duration IL44608N75 TLEB - 250 - ns Leading Edge Blanking Duration IL44608N100 TLEB - 200 - ns Leading Edge Blanking + Propagation Delay IL44608N40 TDLY 500 - 900 ns Leading Edge Blanking + Propagation Delay IL44608N75 TDLY 370 - 570 ns Leading Edge Blanking + Propagation Delay IL44608N100 TDLY 300 - 500 ns OSCILLATOR SECTION Normal Operation Frequency IL44608N40 fosc 36 - 44 kHz Normal Operation Frequency IL44608N 75 fosc 68 - 82 kHz Normal Operation Frequency IL44608N 100 fosc 90 - 110 kHz Maximum Duty Cycle @ f = fosc dmax 78 - 86 % OVERVOLTAGE SECTION Quick OVP Input Filtering (Rdemag = 100 k Ω) Tfilt - 250 - ns Propagation Delay (Idemag > Iovp to output low) TPHL(In/Out) - 2.0 - μs Quick OVP Current Threshold IOVP 105 - 140 μA Protection Threshold Level on VCC VCC–OVP 14.8 - 15.8 V Minimum Gap Between VCC–OVP and Vstup–th VCC–OVP – Vstup 1.0 - - V NOTE 1: This parameter is measured using 1.0 nF connected between the output and the ground.

2011, February, Rev. 01 ELECTRICAL CHARACTERISTICS (VCC = 12 V, for typical values TA = 25°C, for min/max values TA = –25°C to +85°C unless other- wise noted) (Note2 ) Characteristic Symbol Min Typ Max Unit DEMAGNETIZATION DETECTION SECTION (Note 3.) Demag Comparator Threshold (Vpin1 increasing) Vdmg–th 30 - 69 mV Demag Comparator Hysteresis (Note 4.) Hdmg - 30 - mV Propagation Delay (Input to Output, Low to High) tPHL(In/Out) - 300 - ns Input Bias Current (Vdemag = 50 mV) Idem–lb -0.6 - - μA Negative Clamp Level (Idemag = –1.0 mA) Vcl–neg–dem -0.9 - -0.4 V Positive Clamp Level @ Idemag = 125 μA Vcl–pos– dem–H 2.05 - 2.8 V Positive Clamp Level @ Idemag = 25 μA Vcl–pos– dem–L 1.4 - 1.9 V OVERTEMPERATURE SECTION Trip Level Over Temperature Thigh - 160 - ºC Hysteresis Thyst - 30 - ºC STAND–BY MAXIMUM CURRENT REDUCTION SECTION Normal Mode Recovery Demag Pin Current Threshold Idem–NM 20 - 30 μA K FACTORS SECTION FOR PULSED MODE OPERATION ICCS / Istup IL44608N40 10 x K1 2.4 - 3.8 - ICCS / Istup IL44608N75 10 x K1 2.8 - 4.2 - ICCS / Istup IL44608N100 10 x K1 3.1 - 4.5 - ICCL / Istup 103 x K2 46 - 63 - (Vstup – UVLO2) / (Vstup – UVLO1) 102 x Ksstup 1.8 - 2.6 - (UVLO1 – UVLO2) / (Vstup – UVLO1) 102 x Ksl 90 - 150 - ICS / Vcsth 106 x Ycstby 175 - 225 - Demag ratio Iovp / Idem NM Dmgr 3.0 - 5.5 - (V3 1.0 mA – V3 0.5 mA) / (1.0 mA – 0.5 mA) R3 - 1800 - Ω Vcontrol Latch–off V3 - 4.8 - V SUPPLY SECTION Minimum Start–up Voltage Vilow - - 50 V VCC Start–up Voltage Vstup–th 12.5 - 13.8 V Output Disabling VCC Voltage After Turn On Vuvlo1 9.5 - 10.5 V Hysteresis (Vstup–th – Vuvlo1) Hstup–uvlo1 - 3.1 - V VCC Undervoltage Lockout Voltage Vuvlo2 6.2 - 7.0 V Hysteresis (Vuvlo1 – Vuvlo2) Huvlo1–uvlo2 - 3.4 - V Absolute Normal Condition VCC Start Current @ (Vi = 100 V) and (VCC = 9.0 V) –(ICC) 7.0 - 12.8 mA Switching Phase Supply Current (no load) IL44608N40 IL44608N 75 IL44608N100 ICCS 2.0 2.4 2.6 3.6 4.0 4.5 mA Latched Off Phase Supply Current ICC–latch 0.3 - 0.68 mA Hiccup Mode Duty Cycle (no load) _Hiccup - 10 - % NOTE 2 : Adjust VCC above the start–up threshold before setting to 12 V. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. NOTE 3 : This function can be inhibited by connecting pin 1 to GND. NOTE 4 : Guaranteed by design (non tested).

2011, February, Rev. 01 OPERATING DESCRIPTION The pin 3 senses the feedback current provided by the opto coupler. During the switc hing phase the switch S2 is closed and the shunt regulator is acces sible by the pin 3. The shunt regulator voltage is typically 5 .0 V. The d ynam- ic resistance of the shunt regulator represented by the zener diode is 20 Ω. The gain of the Control input is given on Figure 11/, which shows the duty cycle as a func tion of the current injected into the pin 3. A 4.0 kHz filter network is inserted between the shunt regulator and the PWM comparator to cancel the high fr e- quency residual noise. The switch S3 is closed in Stand –by mode during the Latched Off Phase while the switch S2 remains open. (See section PULSED MODE DUTY CYCLE CONTROL). The resistor Rdpulsed (Rduty cycle burst) has no effect on the regulation process. This r esistor is used to determine the burst duty cycle described in the chapter “Pulsed Duty Cycle Control” PWM Latch The IL44608 works in voltage mode. The on –time is controlled by the PWM comparator that compares the o s- cillator sawtooth with the regulation block output (refer to the block diagram on page 2). The PWM latch is initialized by the oscillator and is r e- set by the PWM comparator or by the current sense co m- parator in case of an over current. This configuration en- sures that only a single pulse appears at the circuit output during an oscillator cycle. Current Sense The inductor current is co nverted to a positive voltage by inserting a ground reference sense resistor R Sense in se- ries with the power switch. The maximum current sense threshold is fixed at 1.0 V. The peak current is given by the following equation: )A(R 1Ipk )( SENSE max Ω In stand–by mode, this current can be lowered as due ac- tivation of a 200 μA current source: The current sense input consists of a filter (6.0 k Ω, 4.0 pF) and of a leading edge blanking. Thanks to that, this pin is not sensitive to the power switch turn on noise and spikes and practically in most applications, no filtering network is required to sense the current. Finally, this pin is used: – as a protection against over currents (Isense > I) – as a reduction of the peak current during a Pulsed Mode switching phase. The overcurrent propagation delay is reduced by producing a sharp output turn off (high slew rate). This results in an abrupt output turn off in the event of an over current and in the majority of the pulsed mode switching sequence. (A))(R 0,2))(k(R-1Ipk SENSE csstbymax Ω ×Ω=−

2011, February, Rev. 01 Demagnetization Section The IL44608N demagnetization detection consists of a comparator designed to compare the V CC winding voltage to a reference that is typically equal to 50 mV. This reference is chosen low to increase effectiveness of the demagnetization detection even during start–up. A latch is incorporated to turn the demagnetization block output into a low level as soon a s a voltage less than 50 mV is detected, and to keep it in this state until a new pulse is generated on the output. This avoids any ringing on the input signal which may alter the demagnetization detection. For a higher safety, the demagnetization block output is also directly connected to the output, which is disabled during the demagnetization phase. The demagnetization pin is also used for the quick, pr o- grammable OVP. In fact, the demagnetization input current is sensed so that the ci rcuit output is latc hed off when this current is detected as higher than 120 μA This function can be inhibited by grounding it but in this case, the quick and programmable OVP is also dis- abled. Oscillator The IL44608 contains a fixed frequency oscillator. It is built around a fixed value capacitor CT successive- ly charged and discharged by two distinct current sources ICH and IDCH. The window comparator senses the CT voltage value and activates the sources when the voltage is reaching the 2.4 V/4.0 V levels. The complete demagnetization status DMG is used to inhibit the recharge of the CT capacitor. Thus in case of incomplete transformer demagnetization the next switching cycle is postpone until the DMG signal appears. The osci l- lator remains at 2.4 V corresponding to the sawtooth valley voltage. In this way the SMPS is working in the so called SOPS mode (Self Oscillating Power Supply). In that case the effective switching frequency is variable and no longer depends on the oscillator timing but on the external wor k- ing conditions (Refer to DMG signal in the Figure 6) The OSC and Clock signals are provided according to the Figure 6. The Clock signals correspond to the CT c a- pacitor discharge. The bottom curve represents the cu rrent flowing in the sense resi stor Rcs. It starts from zero and stops when the sawtooth value is equal to the control vo l- tage Vcont. In this way the SMPS is regulated with a vo l- tage mode control.

2011, February, Rev. 01 Overvoltage Protection The IL44608 offers two OVP functions: – a fixed function that detects when V CC is higher than 15.4 V – a programmable function that uses the demag pin. The current flowing into the demag pin is mirrored and compared to the reference current Iovp (120 μA). Thus this OVP is quicker as it is not impacted by the V CC inertia and is called QOVP. In both cases, once an OVP condition is detected, the output is latched off until a new circuit START–UP. Start–up Management The V i pin 8 is di rectly connected to the HV DC rail Vin. This high voltage current source is internally co n- nected to the V CC pin and thus is used to charge the V CC capacitor. The V CC capacitor charge p eriod corresponds to the Start–up phase. When the V CC voltage reaches 13 V, the high voltage 9.0 mA current source is disabled and the device starts working. The d evice enters into the switching phase. It is to be noticed that the maximum rating of the Vi pin 8 is 500 V. ESD prote ction circuitry is not currently added to this pin due to size limitations and technology co n- straints. Protection is limited by the drain –substrate junc- tion in avalanche breakdown. To help increase the applica- tion safety against high voltage spike on that pin it is po ss- ible to insert a small wattage 1. 0 k Ω series resistor b e- tween the V in rail and pin 8. The Figure 7 shows the V CC voltage evolution in case of no external current source providing current into the V CC pin during the switching phase. This case can be e n- countered in SMPS when the self supply t hrough an aux- iliary winding is not present (strong overload on the SMPS output for example). The Figure 17 also depicts this wor k- ing configu ration. In case of the hiccup mode, the duty cycle of the switching phase is in the range of 10%. Mode Transition The LW latch Figure 8 is the memory of the working status at the end of every switching sequence. Two different cases must be considered for the logic at the termination of the SWITCHING PHASE: 1. No Over Current was observed 2. An Over Current was observed These 2 cases are corresponding to the signal labeled NOC in case of “No Over Current” and “OC” in case of Over Current. So the effective working status at the end of the ON time memorized in LW corresponds to Q=1 for no over current and Q=0 for over current. This sequence is repeated during the Switching phase. Several events can occur: 1. SMPS switch OFF 2. SMPS output overload 3. Transition from Normal to Pulsed Mode 4. Transition from Pulsed Mode to Normal Mode 1. SMPS Switch off When the mains is switched OFF, so long as the bulk electrolithic bulk capacitor provides energy to the SMPS, the co ntroller remains in the switching phase. Then the peak current reaches its maximum peak value, the switch- ing frequency decreases and all the secondary voltages are reduced. The V CC voltage is also reduced. When V CC is equal to 10 V, the SMPS stops working.

2011, February, Rev. 01 2. Overload In the hiccup mode the 3 distinct phases are described as follows (refer to Figure 7): The SWITCHING PHASE: The SMP S output is low and the regulation block reacts by increasing the ON time (dmax = 80%). The OC is reached at the end of every switching cycle. The LW latch (Figure 8) is reset before the VPWM signal appears. The SMPS output voltage is low. The V CC voltage cannot be maintained at a normal level as the auxiliary winding provides a voltage which is also reduced in a ratio similar to the one on the output (i.e. Vout nominal / Vout short –circuit). Consequently the V CC voltage is reduced at an operating rate given by the comb i- nation VCC capacitor value together with the I CC working consumption (3.2 mA) according to the equation 2. When VCC crosses 10V the WORKING PHASE gets terminated. The LW latch remains in the reset status. The LATCHED–OFF PHASE: The V CC capacitor vol- tage continues to drop. When it reaches 6.5 V this phase is terminated. Its duration is governed by equation 3. The START –UP PHASE is reinitiated. The high vo l- tage start–up current source ( –ICC1 = 9.0 mA) is activated and the MODE latch is reset. Th e V CC voltage ramps up according to the equation 1. When it reaches 13 V, the IC enters into the SWITCHING PHASE. The NEXT SWITCHING PHASE: The high voltage current source is inhibited, the MODE latch (Q=0) act i- vates the NORMAL mode of operation. Figure 3 shows that no current is injected out pin 2. The over current sense level corresponds to 1.0 V. As long as the overload is present, this sequence r epeats. The SWITCHING PHASE duty cycle is in the range of 10%. 3. Transition from Normal to Pulsed Mode In this sequence the secondary side is reconfigured (r e- fer to the typical application schematic on page 13). The high voltage output value becomes lower than the NO R- MAL mode regulated value. The TL431 shunt regulator is fully OFF. In the SMPS stand –by mode all the SMPS ou t- puts are lowered except for the low voltage output that supply the wake –up circuit located at the isolated side of the power supply. In that mode the secondary regulation is performed by the zener diode co nnected in parallel to the TL431. The secondary reconfiguration status can be detected on the SMPS primary side by measuring the voltage level present on the auxiliary winding Laux. (Refer to the D e- magnetization Section). In the reconfigured status, the Laux voltage is also reduced. The V CC self–powering is no longer possible thus the SMPS enters in a hiccup mode similar to the one described under the Overload condition. In the SMPS stand–by mode the 3 distinct phases are: The SWITCHING PHASE: Similar to the Overload mode. The current sense clamping level is reduced accor d- ing to the equation of the current sense section, page 5. The C.S. clamping level depends on the power to be delivered to the load during the SMPS stand –by mode. Every switching sequence ON/OFF is terminated by an OC as long as the secondary Zener diode vol tage has not been reached. When the Zener voltage is reached the ON cycle is terminated by a true PWM action. The proper SWITC H- ING PHASE termination must correspond to a NOC co n- dition. The LW latch stores this NOC status. The LATCHED OFF PHASE: The MODE latch is set. The START– UP PHASE is similar to the Overload Mode. The MODE latch remains in its set status (Q=1). The SWITCHING PHASE: The Stand –by signal is v a- lidated and the 200 μA is sourced out of the Current Sense pin 2. 4. Transition from Stand–by to Normal The secondary reconfiguration is removed. The regul a- tion on the low voltage secondary rail can no longer be achieved, thus at the end of the SWITCHING PHASE, no PWM condition can be encountered. The LW latch is reset. At the next WORKING PHASE a NORMAL mode sta- tus takes place. In order to become independent of the recovery time co n- stant on the secondary side of the SMPS an additional reset input R2 is provided on the MODE latch. The cond ition Idemag<24 μA corresponds to the activation of the se c- ondary reconfiguration status. The R2 reset insures a direct return into the Normal Mode Pulsed Mode Duty Cycle Control During the sleep mode of the SMPS the switch S3 is closed and the control input pin 3 is connected to a 4.6 V voltage source thru a 500 Ω resistor. The discharge rate of the V CC capacitor is given by I CC–latch (device consumption during the LATCHED OFF phase) in addition to the cu r- rent drawn out of the pin 3. Connecting a resistor b etween the Pin 3 and GND (R DPULSED) a programmable cu rrent is drawn from the V CC through pin 3. The duration of the LATCHED OFF phase is i mpacted by the presence of the resistor RDPULSED. The equation 3 shows the relation to the pin 3 current. Pulsed Mode Phases Equations 1 through 8 define and predict the effective behavior during the PULSED MODE operation. The equa- tions 6, 7, and 8 contain K, Y, and D factors. These factors are combinations of measured parameters. They appear in the parameter section “Kfactors for pulsed mode oper a- tion” page 4. In equations 3 through 8 the pin 3 current is the current defined in the above sec tion “Pulsed Mode Du- ty Cycle Control”

2011, February, Rev. 01 EQUATION 1 Start–up Phase Duration: STUP STUPVcc UPSTART I UOLO2)(VCt −×=− where: Istup is the start–up current flowing through VCC pin CVcc is the VCC capacitor value EQUATION 2 Switching Phase Duration: GccS STUPVcc switch II UOLO1)(VCt + −×= where: IccS is the no load circuit consumption in switching phase IG is the current consumed by the Power Switch EQUATION 3 Latched–off Phase Duration: pin3ccL Vcc offlatched II UOLO2)(UVLOP1Ct + −×=− where: IccL is the latched off phase consumption Ipin3 is the current drawn from pin3 adding a resistor EQUATION 4 Burst Mode Duty Cycle: off-latchedswitchup-start SWITCH BM ttt td ++= EQUATION 5 Ipin3ccL Vcc GccS STUPVcc STUP STUPVcc GccS STUPVcc BM II UVLO2)(UVLO1C II UVLO1)(VC I UVLO2)(VC II UVLO1)(VC d −×++ −×+−× EQUATION 6 +×+  +×+ pin3ccL GccS S/L stup GccS S/Stup BM II IIkI IIk1 where: kS/Stup = (Vstup – UVLO2)/(Vstup – UVLO1) kS/L = (UVLO1 – UVLO2)/(Vstup – UVLO1) EQUATION 7 +×+×++ pin3ccL stup S/LS/Stup stup GccS BM II IkkI II1

2011, February, Rev. 01 EQUATION 8 ×+× stup pin3 S/LS/Stup stup G BM I Ik2 1kkI Ik11 where: k1 = Iccs/Istup k2 = IccL/Istup kS/Stup = (Vstup–UVLO2)/(Vstup–UVLO1) kS/L = (UVLO1–UVLO2)/(Vstup–UVLO1) PULSED MODE CURRENT SENSE CLAMPING LEVEL Equations 9, 10, 11 and 12 allow the calculation of the Rcs value for the desired m aximum current peak value during the SMPS stand–by mode.] EQUATION 9 S cscsthcs stby R )I(RVIpk ×−= − where: Vcs–th is the CS comparator threshold Ics is the CS internal current source RS is the sensing resistor Rcs is the resistor connected between pin 2 and RS EQUATION 10 S thc cs cs thcsstby R V IR1 VIpk  ×− s EQUATION 11 ( ) S stbycscs thcsstby R YR1VIpk ×−×= where: Ycs–stby = Ics/Vcs–th Taking into account the circuit propagation delay (δtcs) and the Power Switch reaction time (δtps): EQUATION 12 ( ) P pscsin S stbycscs thcsstby L )δt t(δV R YR1VIpk +×+  ×−×=

2011, February, Rev. 01 The Figure 11 represents a complete power supply using the secondary reconfiguration. The specification is as follows: Input source: 85 Vac to 265 Vac 3 Outputs 112 V/0.45 A 16 V/1.5 A 8.0 V/1.0 A Output power 80 W Stand–by mode @ Pout = 300 mW, 1.3 W

2011, February, Rev. 01 PACKAGE DIMENSIONS