IL4108 SIEMENS | Alldatasheet

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Technical content

5–141

DESCRIPTION

The IL4108 consists of a GaAs IRLED optically coupled to a photosensi- tive zero crossing TRIAC network. The TRIAC consists of two inverse parallel connected monolithic SCRs. These three semiconductors are assembled in a six pin 0.3 inch dual in-line package, using high insula- tion double molded, over/under leadframe construction. High input sensitivity is achieved by using an emitter follower pho- totransistor and a cascaded SCR predriver resulting in an LED trigger current of less than 2 mA (DC). The IL4108 uses two discrete SCRs resulting in a commutating dV/dt greater than 10KV/ m s. The use of a proprietary dv/dt clamp results in a static dV/dt of greater than 10KV/ m s. This clamp circuit has a MOSFET that is enhanced when high dV/dt spikes occur between MT1 and MT2 of the TRIAC. When conducting, the FET clamps the base of the pho- totransistor, disabling the first stage SCR predriver. The zero cross line voltage detection circuit consists of two enhance- ment MOSFETS and a photodiode. The inhibit voltage of the network is determined by the enhancement voltage of the N-channel FET. The P- channel FET is enabled by a photocurrent source that permits the FET to conduct the main voltage to gate on the N-channel FET. Once the main voltage can enable the N-channel, it clamps the base of the pho- totransistor, disabling the first stage SCR predriver. The 800V blocking voltage permits control of off-line voltages up to 240VAC, with a safety factor of more than two, and is sufficient for as much as 380VAC. The IL4108 isolates low-voltage logic from 120, 240, and 380 VAC lines to control resistive, inductive, or capacitive loads including motors, sole- noids, high current thyristors or TRIAC and relays. Applications include solid-state relays, industrial controls, office equip- ment, and consumer appliances. Package Dimensions in inches (mm) ZCC* *Zero Crossing Circuit Triac MT1 Triac MT2 Substrate do not connect LED Anode LED Cathode NC .010 (.25) .014 (.35) .110 (2.79) .150 (3.81) .130 (3.30) .150 (3.81) .020 (.051) min. .300 (7.62) typ. .031 (0.80) .035 (0.90) .100 (2.54) typ. .039 (1.00) min. .018 (0.45) .022 (0.55) .248 (6.30) .256 (6.50) .335 (8.50) .343 (8.70) Pin One ID. 654 123 18° typ. .300 (7.62) .347 (8.82) typ.

FEATURES

  • On-State Current, 300 mA
  • Zero Voltage Crossing
  • Blocking Voltage, 800 V
  • Isolation Test Voltage 5300 VACRMS
  • High Input Sensitivity IFT=2 mA, PF=1.0 IFT=5 mA, PF 1.0
  • High Static dv/dt 10,000 V/ m s
  • Inverse Parallel SCRs Provide Commutating dv/dt >10K V/ m s
  • Very Low Leakage <10 m A
  • Small 6-Pin DIP Package
  • Underwriters Lab File #E52744
  • VDE App roval #0884 (Optional with Option 1, Add -X001 Suffix) Maximum Ratings Emitter C/W Derate from 25 C Detector C/W Derate from 25 C Package Isolation Test Voltage (between emitter and detector, climate per DIN 40046, RMS 7 mm 7 mm Comparative Tracking Index per DIN IEC 112/VDE 0303 part 1, Group IIIa per 175 Isolation Resistance V IO =500 V, T A =25 W V IO =500 V, T A =100 W C to +125 C C to +100 C Soldering Temperature (max. 10 sec. dip soldering 0.5 mm from C IL4108 ZERO VOLTAGE CROSSING

800 V TRIAC DRIVER OPTOCOUPLER

5–142 IL4108

Electrical Characteristics

Parameter Symbol Min. Typ. Max. Unit Condition Emitter Forward Voltage V F 1.16 1.35 V I F =10 mA Breakdown Voltage V BR 63 0 V I R =10 m A Reverse Current I R 0.1 10 m AV R =6 V Capacitance C 25 pF V F =0 V, f=1 MHz Thermal Resistance, Junction to Lead R THJL 750 C/W Output Detector Repetitive Peak Off-state Voltage V DRM

800 V I

=100 m A Off-state Voltage V D(RMS)

565 V I

D(RMS) =70 m A Off-state Current I D(RMS)1 10 100 m AV D =800 V, T A 100 C, I F mA Off-state Current I D(RMS)2 200 m AV D =800 V, I F =Rated I FT On-state Voltage V TM 1.7 3 V I T =300 mA On-state Current I TM 300 mA PF=1.0, V T(RMS) =1.7 V Surge (Non-repetitive On-state Current) I TSM

3 A f=50 Hz

2.0 mA V D =5 V Trigger Current 2 I FT2 6.0 mA V op =220 V, f=50 Hz, T j =100 C, t pF >10 ms Trigger Current Termperature Gradient D I FT1 D T j D I FT2 D T j m A/K m A/K Inhibit Voltage Temperature Gradient D V DINH D T j –20 mV/K Off-state Current in Inhibit State I DINH 50 200 m AI F FT1 , V DRM Capacitance between Input and Output Circuit C IO 2.0 pF V D =0, f=1 kHz Holding Current I H 65 500 m A Latching Current I L 5m A V T =2.2 V Zero Cross Inhibit Voltage V IH 15 25 V I F =Rated I FT Turn-on Time t ON m sV RM DM =565 VAC Turn-off Time t OFF m s PF=1.0, I T =300 mA Critical Rate of Rise of Off-State Voltage dv/dt cr dv/dt cr 10000 5000 m s m s V D =0.67 V DRM , Tj=25°C Tj=80°C Critical Rate of Rise of Voltage at Current Commutation dv/dtcrq dv/dtcrq 10000 5000 V/ms V/ms V D =0.67 VDRM , di/dtcrq<15 A/ms Tj=25°C Tj=80°C Critical Rate of Rise of On-state Current di/dt/ cr 8A / ms Thermal Resistance, Junction to Lead R THJL 150 °C/W Package Critical Rate of Rise of Coupled Input/Output Voltage dv (IO)/dt 1000 V/msI T=0 A, VRM =VDM =565 VAC Common Mode Coupling Capacitor C CM 0.01 pF Package Capacitance C IO 0.8 pF f=1 MHz, V IO=0 V