IL33153 IKSEMICON | Alldatasheet

Document overview

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Technical content

Features

  • High Current Output Stage: 1.0 A Source/2.0 A Sink
  • Protection Circuits for Both Conventional and Sen se IGBTs
  • Programmable Fault Blanking Time
  • Protection against Overcurrent and Short Circuit
  • Undervoltage Lockout Optimized for IGBT's
  • Negative Gate Drive Capability
  • Cost Effectively Drives Power MOSFETs and Bipolar Transistors Block Diagram IL33153 SOP-8 DIP-8

Rev. 02 Absolute Maximum Ratings Rating Symbol Value Unit Power Supply Voltage VCC to VEE Kelvin Ground to VEE (Note 1 ) VCC -VEE KGnd - VEE V Logic Input Vin V EE -0.3 to V CC V Current Sense Input VS -0.3 to Vcc V Blanking/Desaturation Input VBD -0.3 to Vcc V Gate Drive Output Source Current Sink Current Diode Clamp Current I O 1.0 2.0 1.0 A Fault Output Source Current Sink Curent I FO mA Power Dissipation and Thermal Characteristics D Suffix SO-8 Package, Case 751 Maximum Power Dissipation @ T A = 5O °C Thermal Resistance, Junc- tion-to-Air P Suffix DIP-8 Package, Case 626 Maximum Power Dissipation @ T A = 5O °C Thermal Resistance, Junc- tion-to-Air P D Rθ JA P D Rθ JA 0.56 180 1.0 100 W °C/W W °C/W Operating Junction Temperature T J +150 °C Operating Ambient Temperature T A -40 to +105 °C Storage Temperature Range Tstg -65 to +150 °C

Rev. 02

ELECTRICAL CHARACTERISTICS

(Vcc=15V, V EE =0V, Kelvin Gnd connected to V EE . For typical values TA=25 °C, for min/max values T A is the operating ambient temperature range that applies (Note 2), unless otherwise noted.) Characteristic Symbol Min Typ Max Unit LOGIC INPUT Input Threshold Voltage ] High State (Logic 1 ) Low State (Logic 0) VIH V IL 1.2 2.70 2.30 3.2 V Input Current High State (VIH = 3.0 V) Low State (V ii . = 1.2 V) IIH I IL 130 500 100 µ A DRIVE OUTPUT Output Voltage Low State (Isink = 1.0 A) High State (Isource = 500 mA) VOL VOH 2.0 13.9 2.5 V Output Pull-Down Resistor RPD - 100 200 kΩ FAULT OUTPUT Output voltage Low Slate (Isink = 5.0 mA) High State (Isource = 20 mA) VFL V FH 0.2 13.3 1.0 V SWITCHING CHARACTERISTICS Propagation Delay (50% Input to 50% Output C L = 1.0 nF) Logic Input to Drive Output Rise Logic Input to Drive Output Fall t PLH (in/out) t PHL (in/out) 120 300 300 ns Drive Output Rise Time (10% to 90%) C L = 1.0 nF tr - 17 55 ns Drive Output Fall Time (90% to 10%) C L= 1.0 nF tf - 17 55 ns Propagation Delay Current Sense Input to Drive Output Fault Blanking/Desaturation Input to Drive Output tp (OC) tp (FLT) 0.3 0.3 1.0 1.0 µ s UVLO Startup Voltage VSS S tart 11.3 12 12.6 V Disable Voltage VSS dis 10.4 11 11.7 V COMPARATORS Overcurrent Threshold Voltage (V pin8 > 7,0 V) V SOC 50 65 80 mV Short Circuit Threshold Voltage (V pine8> 7,0 V) V SSC 100 130 160 mV Fault Blanking/Desaturation Threshold (Vpin1 > 100 mV) V th(FLT ) 6.0 6.5 7.0 V Current Sense Input Current (Vsi = 0 V) I SI - -1.4 -10 uA FAULT BLANKING/DESATURATION INPUT Current Source (Vpjn8 = 0 V, Vpin4 = 0 V) Ichg -200 -270 -300 uA Discharge Current (Vpin8 = 15 V, Vpin4 = 5.0 V) Idsc hg 1.0 2.5 - mA TOTAL DEVICE Power Supply Current Standby (Vpin 4 = VCC , O utput Open) Operating (C L= 1.0 nF, f= 20 kHz) ICC 7.2 7.9 mA NOTES : 1. Kelvin Ground must always be between VEE and VCC . 2.Low duty cycle pulse techniques are used during test to maintain the junction temperature as close to ambient as possi- ble. Tlow = -40°C for IL33153 Thigh = +105 °C for IL33153

Rev. 02 sitic wiring inductance. The fault signal from the De- saturation Comparator must be blanked sufficiently to allow the diode to be cleared and the ringing to se ttle out. The blanking function uses an NPN transistor t o clamp the comparator input when the gate input is l ow. When the input is switched high, the clamp transist or will turn “off”, allowing the internal current sour ce to charge the blanking capacitor. The time required fo r the blanking capacitor to charge up from the on−voltage of the internal NPN transistor to the trip voltage of the comparator is the blanking time. If a short circuit occurs after the IGBT is turned on and saturated, the delay time will be the time requ ired for the current source to charge up the blanking ca paci- tor from the V CE(sat) level of the IGBT to the trip volt- age of the comparator. Fault blanking can be disabled by leaving Pin 8 unconnected. Sense IGBT Protection Another approach to protecting the IGBTs is to sense the emitter current using a current shunt or Sense IGBTs. This method has the advantage of being able to use high gain IGBTs which do not have any inherent short circuit capability. Current sense IGBTs work as well as current sense MOSFETs in most circumstances . However, the basic problem of working with very low sense voltages still exists. Sense IGBTs sense curr ent through the channel and are therefore linear with re- spect to the collector current. Because IGBTs have a very low incremental on−resistance, sense IGBTs be- have much like low−on resistance current sense MOS- FETs. The output voltage of a properly terminated s ense IGBT is very low, normally less than 100 mV. The sense IGBT approach requires fault blanking to prevent false tripping during turn−on. The sense IG BT also requires that the sense signal is ignored whil e the gate is low. This is because the mirror output norm ally produces large transient voltages during both turn− on and turn−off due to the collector to mirror capacit ance. With non−sensing types of IGBTs, a low resistance c ur- rent shunt (5.0 to 50 m Ω) can be used to sense the emit- ter current. When the output is an actual short cir cuit, the inductance will be very low. Since the blanking cir- cuit provides a fixed minimum on−time, the peak cur - rent under a short circuit can be very high. A shor t cir- cuit discern function is implemented by the second comparator which has a higher trip voltage. The sho rt circuit signal is latched and appears at the Fault Output. When a short circuit is detected, the IGBT should b e turned−off for several milliseconds allowing it to cool down before it is turned back on. The sense circuit is very similar to the desaturation circuit. It is pos sible to build a combination circuit that provides protectio n for both Short Circuit capable IGBTs and Sense IGBTs.

Rev. 02 Package Dimension N SUFFIX PLASTIC DIP (MS – 001BA) Symbol MIN MAX A 8.51 10.16 B 6.1 7.11 C 5.33 D 0.36 0.56 F 1.14 1.78 G H J 0° 10° K 2.92 3.81 NOTE S: L 7.62 8.26 Dimensions “A”, “B” do not include mold flash or pr otrusions. M 0.2 0.36 Maximum mold flash or protrusions 0.25 mm (0.010) per side. N 0.38 Dimension, mm 2.54 7.62 L H M J A B F G D SEATING PLANE N K 0.25 (0.010) M T -T- C

Rev. 02 D SUFFIX SOIC (MS - 012AA) Symbol MIN MAX A 4.8 5 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 G H J 0° 8° NOTE S: K 0.1 0.25 Dimensions A and B do not include mold flash or pro trusion. M 0.19 0.25 1.27 5.72 Dimension, mm A BH C K C M J F M P G D R x 45 SEATING PLANE 0.25 (0.010) M T -T-