IL317L ESTEK | Alldatasheet

Document overview

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Technical content

Features

  • Output Current in Excess of 100 mA
  • Output Adjustable Between 1.2 V and 37 V Pin 1.Vin
  • Internal Thermal Overload Protection 2.Vout
  • Internal Short Circuit Current Limiting 3.Adjust
  • Output Transistor Safe-Area Compensation
  • Floating Operation for High Voltage Applications
  • Standard 3-Lead Transistor Package
  • Eliminates Stocking Many Fixed Voltages *Cin is required if regulator is located an appreciable distance from power supply filter. **Co is not needed for stability, however, it does improve transient response. Vout = 1.25 V (1+R2/R1) + I Adj Since I Adj is controlled to less than 100µA, the error associated with this term is negligible in most applications. MAXIMUM RATINGS Rating Symbol Value Unit Input-Output Differential V I o

40 Vdc

T A =25°C Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case Case SOIC-8 (Note 1) T A =25°C Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case P D R θJA R θJC R θJA R θJC Internally Limited 160 180 W °C/W °C/W °C/W °C/W Operating Junction Temperature Range Tj -10 to +125 °C Storage Temperature Range Tstg -65 to +150 °C IL317L technical data

Positive Voltage Regulator

ELECTRICAL CHARACTERISTICS

I O = 5.0 V ; I O = 40 mA;T A = 25°C, unless otherwise noted, Imax and Pmax (NOTE1)) Pad Location Coordinates NOTES : Physica l Characteristics: 1.Imax = 100 mA ,Pmax=625 mV ♦ Wafer Diameter 100 ± 0.5 mm 2. Load and line regulation are specified at constant junction temperature. ♦ Wafer thickness (*) 280 ± 20 µm Changes in V O due to heating effects must be taken into account separately. ♦ Die size 1.53 x 0.93 mm Pulse testing with low duty cycle is used. ♦ Scribe width 100 µm ♦ Passivation PSG *The wafer thickness shall be specified in a PO or Contract Bonding Diagram (TO-92) Fig.1 Test Circuit for Vo>1.25V Fig.2 Test Circuit for Vo=1.25V Сi=0,1µF, Сo=1,0 µF. Сi=0,1µF, Сo=1,0 µF. Vo=1,25(1+R2/R1)I ADJ Reference Voltage (T A =-10° to +125°C)

3.0 V ≤ V

I - V O ≤ 40 V, 10mA ≤ I O ≤ Imax,P D ≤ Pmax Vo 1.20 1.30 V Line Regulation (NOTE2)

3.0 V ≤V

I - V O ≤ 40 V, Io=5mA ∆Vov - 20 mV Line Regulation (T A =-10° to +125°C) (NOTE2) I - V O ≤ 40 V, Io=5mA ∆Vov - 35 mV Load Regulation (NOTE2) 10 mA ≤ I O ≤ Imax,Vi=6.25V ∆Voi - 6.25 mV Load Regulation (T A =-10° to +125°C) (NOTE2) 10 mA ≤ I O ≤ Imax,Vi=6.25V ∆Voi - 18.75 mV Adjustment Pin Current I Adj 10 100 µA Adjustment Pin Current Change , P D ≤ Pmax I - V O ≤ 40 V, 10 mA ≤ I O ≤ Imax ∆ I Adj - 5 µA Maximum Output Current ,P D ≤ Pmax I O MAX 0.1 - A Minimum Load Current to Maintain Regulation (V I - V O =40V) I Lmin - 5 mA Ripple Rejection V O = 1.2 V, f = 120 Hz RR 60 - dB N X (µm) Y (µm) Pad names 01 375 92 Output 02 545 110 Input 03 1262 735 Adjustable 04 570 690 Output IL317L(Chip) X TR Y technical data