IGI60F1414A1L

IGI60F2020A1L INFINEON | Alldatasheet

Document overview

• Manufacturer or author: Infineon Technologies AG
• PDF pages: 35

Technical content

Features

• Two 200 m GaN switches in half-bridge configuration with dedicated high- and low-side isolated gate drivers ­ Source / sink driving current up to 1 / 2 A ­ Application-configurable turn-on and turn-off speed
• Fast input-to-output propagation (typ. 47 ns) with extremely small channel-to- channel mismatch
• PWM input signal (switching frequency up to 3 MHz)
• Standard logic input levels compatible with digital controllers
• Wide supply range
• Single gate driver supply voltage possible (typ. 8 V) with fast UVLO recovery
• Low-side open source for current sensing with external shunt resistor
• Galvanic input-to-output isolation based on robust coreless transformer technology
• Gate driver with very high common mode transient immunity (CMTI) > 300 V/ns
• Thermally enhanced 8 x 8 mm QFN-28 package
• Product is fully qualified acc. to JEDEC for Industrial Applications

Description

IGI60F2020A1L combines a half -bridge power stage consisting of two 200 m (typ. Rdson) / 600 V enhancement- mode CoolGaNTM HEMTs with dedicated gate drivers in a small 8 x 8 mm QFN -28 package. In the low-to-medium power area (example application in Figure 1) it is thus ideally suited to support the design of high-density AC/DC chargers and adapters utilizing the superior switching behavior of CoolGaNTM HEMTs. Infineon’s CoolGaNTM and related power switches provide a very robust gate structure. When driven by a continuous gate current of a few mA in the “on” state, a minimum on-resistance Rdson is always guaranteed. Figure 1 Typical application circuit (active clamp flyback converter) CoolGaNTM INH ENABLE GNDI VDDI TX UVLO Control Logic RX UVLO Logic SW RX UVLO Logic TX INL SLDON SLDO SL VDDL OUTL GL OUTH GH VDDH DH CT CCRtr Rss CC Rtr Rss CVDDL Cboot VDDL Rsense Dboot Cout Vin Controller RVDDI GND GPIOx PWML PWMH CoolGaNTM IPS Vout Cclmp Is CVDDI VDDL

Final Datasheet 2 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage Due to the GaN -specific low threshold voltage and the fast switching transients, a negative gate drive voltage is required in certain applications to both enable fast turn-off and avoid cross-conduction effects. This can be achieved by the well -known RC interface between driver and switch. A few external SMD resistors and c aps enable easy adaptation to different power topologies. The driver utilizes on -chip coreless transformer technology (CT) to achieve signal level -shifting to the high -side. Further, CT guarantees robustness even for extremely fast switching transients abo ve 300 V/ns.

Applications

• Charger and adaptors
• Server, telecom & networking SMPS
• Low power motor drive
• LED lighting Power Topologies
• Active clamp flyback or hybrid flyback converters
• LLC or LCC resonant converters
• Single or interleaved synchronous buck or boost converter
• Single phase or multiphase two-level inverters Product Versions Table 1 CoolGaNTM integrated power stage half bridge products overview Part Number / Ordering code high- / low-side Marking IGI60F1414A1L IGI60F1414A1L AUMA1 PG-TIQFN-28-1 8 x 8 mm 140 mΩ / 140 mΩ 60F1414A IGI60F2020A1L IGI60F2020A1L AUMA1 PG-TIQFN-28-1 8 x 8 mm 200 mΩ / 200 mΩ 60F2020A IGI60F2727A1L IGI60F2727A1L AUMA1 PG-TIQFN-28-1 8 x 8 mm 270 mΩ / 270 mΩ 60F2727A IGI60F5050A1L IGI60F5050A1L AUMA1 PG-TIQFN-28-1 8 x 8 mm 500 mΩ / 500 mΩ 60F5050A

Final Datasheet 3 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage Table of contents

Final Datasheet 4 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage

1 Pin configuration and description

Figure 2 Pin configuration and exposed pads for QFN-28 8 x 8 mm package, top view (not to scale) Table 2 Pin description Pin No. Symbol Description

1 NC Not connected

2 OUTH Driver output high-side

3 VDDH Supply voltage for high-side driver (typ. 8 V referred to SW)

4 GH Gate connection high-side switch

5 – 8, 28 SW Half-bridge output (switching node) 9 - 11 DH Drain connection high-side switch 12 - 16 SL Source connection low-side switch

17 GL Gate connection low-side switch

18 VDDL Supply voltage for low-side driver (typ. 8 V referred to SL)

19 OUTL Driver output low-side

20, 25 GNDI Ground connection of driver input stage

Final Datasheet 5 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage

21 INL Input signal (default state “Low”); controls low-side switch

22 INH Input signal (default state “Low”); controls high-side switch

23 SLDON

Connected to VDDI (or not connected): VDDI directly supplies driver input circuitry Connected to GNDI: Internal shunt regulator activated to generate VDDI (3.3 V) 24 VDDI Supply voltage driver input stage (+3.3 V); can be either applied directly or generated by internal SLDO (e.g by connecting VDDI via resistor RVDDI to VDDL)

26 ENABLE Input signal (default state “Low” - both outputs set to low state); logic “High”

required to activate outputs

27 NC Not connected

Final Datasheet 6 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage

2 Functional description

2.1 Block Diagram

A simplified functional block diagram of the CoolGaNTM Power Stage is given in Figure 3. For the level -shifting function of the input signal to the high -side switch an on -chip coreless transformer (CT) is utilized. F or symmetry reasons a CT is also included in the low-side path, resulting in both a galvanic input -to-output and high-to-low-side isolation. In addition, this CT separates the low-side gate driver reference (SL) fro m GNDI allowing to use a shunt resistor for current sensing as shown in Figure 1. INH ENABLE GNDI VDDI TX UVLO Control Logic RX UVLO Logic SW RX UVLO Logic TX INL SLDON SLDO DH SH DL SL SLVDDL OUTL GL OUTH GHVDDH DH CT functional isolation Figure 3 Block Diagram IGI60F2020A1L

Final Datasheet 7 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage

2.2 Power supply

Basically, the Power Stage requires 3 supply voltages: a ground-related 3.3 V (VDDI) for the driver input circuitry, another ground-related 8 V (VDDL) for the low-side driver and a floating 8 V (VDDH) for the high-side driver. However, in most application s a single 8 V supply is sufficient, as V DDI and V DDH can be simply generated from V DDL. Independent Undervoltage Lockout (UVLO) functions for all supply voltages ensure a defined start -up and robust functionality under all operating conditions. All driver supply currents stay in the few mA range, as described in Table 9, resp. However, in particular applications a further power reduction in stand -by mode might be benef icial. Then a complete elimination of the supply currents can be achieved by implementing a simple circuit with a bipolar transistor as a supply switch controlled by the Enable signal.

2.2.1 Driver input supply voltage

The driver input die is supplied via VDDI with a nominal voltage of 3.3 V. The Undervoltage Lockout threshold, defining the minimum VDDI, is set to typically 2.85 V. Power consumption to some extent depends on switching frequency, as the input signal is converted into a train of repetitive current pulses to drive the CT. Due to the chosen robust encoding scheme the average repetition rate of these pulses and thus the average supply current depends on the switching frequency fsw. However, for fsw < 500 kHz this effect is very small. If no separate 3.3 V supply is available, the input side can also be operated with VDDL (typically 8 V). Then the shunt LDO voltage regulator (SLDO) has to be enabled by connecting pin SLDON (pin#23) to GNDI. The SLDO regulates the current through an external resistor R VDDI connected between VDDL and pin VDDI as depicted in Figure 1 to generate the required voltage drop. For proper operation it has to be ensured that the current through R VDDI always exceeds the maximum supply current IVDDI of the input chip; but not too small to casue a high power dissipation and significant impact on the total system efficiency. RVDDI thus has to fulfil: 𝑅𝑉𝐷𝐷𝐼 < 𝑉𝐷𝐷𝐿,𝑚𝑖𝑛 − 3.3 𝑉 𝐼𝑉𝐷𝐷𝐼,𝑚𝑎𝑥 (1) A typical choice for V DDL = 8 V would be R VDDI = 1 k, resulting in sufficient margin between resistor current and maximum operating current. Dynamic current peaks are provided by a blockin g cap (10 to 22 nF) between VDDI and GNDI. Table 3 shows proper RVDDI values for different supply voltages VDDL.. Table 3 Proper RVDDI values for different VDDL VDDL RVDDI SLDO

3.3 V no resistor (connect VDDL to VDDI pin) Disabled

5.0 V 360  Enabled

8.0 V 1.0 k Enabled 12.0 V 1.8 k Enabled

2.2.2 Driver output supply voltages

Both output dice have to be supplied by a voltage of typically 8 V related to the source of the respective GaN switch. In many applications the floating high-side supply VDDH can be generated from the ground-related VDDL by means of bootstrapping (components D boot, C boot and R boot in Figure 1). A ceramic bypass capacitance CVDDL of typically 100 nF has to be placed close to pin VDDL.

Final Datasheet 8 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage For both driver output stages the minimum operating supply voltage is set by independent undervoltage lockout functions (UVLOout).

2.3 Input configurations

The inputs INL and INH are two independent logic (PWM) channels. The input signal is transferred non-inverted to the corresponding gate driver outputs OUTL and OUTH. All inputs are compatible with LV-TTL threshold levels with a hysteresis of typ. 0.8 V. The hysteresis is independent of the supply voltage VDDI. The PWM inputs are internally pulled down to a logic low voltage level (GNDI ). In case the PWM -controller signals have an undefined state during the power -up sequence, the gate driver outputs are forced to the "off" -state (low). If the Enable input is low, both channel outputs are driven to “low”, regardless of the state of INL or INH. Table 4 shows the logic table in normal operation. Table 4 Logic table ( UVLO input inactive, both output side UVLO inactive; normal operation) Inputs Gate Drive Ouput Enable INL INH OUTL OUTH L x x L L H L L L L H L H L H H H L H L H H H H H

2.4 Driver outputs

The rail-to-rail gate driver output stage realized with complementary MOS transistors is able to provide a typical 1 A sourcing and 2 A sinking current. This is by far sufficient when driving the GaN HEMTs due to their low gate charge. In addition, the relatively low driver output resistance is beneficial, too. With an Ron of 3.1  for the sourcing pMOS and 1.2  for the sinking nMOS transistor the driver can be considered as nearly ideal. The gate drive parameters can thus be determined easily and accurately by the external components as described in chapter 4. The p-channel sourcing transistor allows real rail-to-rail behavior without suffering from a source follower's voltage drop.

2.5 Undervoltage Lockout (UVLO)

The Undervoltage Lockout function ensures that the gate drive outputs can be switched to their high level only, if both input and output supply voltages exceed the corresp onding UVLO threshold voltages. Thus it can be guaranteed, that the GaN switches are in “off” state, if the driving voltage is too low for complete and fast switching on, thereby avoiding excessive power dissipation and keeping the switch transistors within their safe operating area (SOA). The UVLO levels for the output supplies VDDL and VDDH are set to a typical “on”-value of 4.2 V (with 0.3 V hysteresis), whereas UVLOin for VDDI is set to 2.85 V with 0.15 V hysteresis. Table 5 shows the logic table in the condition that input or outputs are in UVLO active or inactive condition.

Final Datasheet 9 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage Table 5 Logic table ( dependence on UVLO status) Inputs Gate Drive Ouput Enable INL INH UVLO input UVLO output L UVLO output H OUTL OUTH x x x Active x x L L H x L Inactive Active Inactive L L H x H Inactive Active Inactive L H H L x Inactive Inactive Active L L H H x Inactive Inactive Active H L

2.6 Start-up and active clamping

Special attention has been paid to cover all possible operating conditions, like start -up or arbitrary supply voltage situations: - if VDDI drops below UVLOin, a “switch-to-low” command is sent to both outputs OUTL and OUTH - for VDDL and/or VDDH lower than the respective UVLO levels, a new fast active clamping circuit provides a low-impedance path from the gate driver outputs OUTL and OUTH to their r espective grounds SL and SW. As soon as the output voltage exceeds a low threshold level (typically below 1 V), the clamp is activated within approximately 20 ns. As the result, safe operation of the GaN Power Stage can be guaranteed under any circumstances.

2.7 CT Communication and Data Transmission

A Coreless Transformer (CT) based communication module is used for PWM signal transfer between input and outputs. A proven high -resolution pulse repetition scheme in the transmitter co mbined with a watchdog time -out at the receiver side enables recovery from communication fails and ensures safe system shut -down in failure cases.

2.8 CoolGaNTM output stage

The output stage consists of t wo CoolGaNTM 600V switches in half -bridge configuration . The switches are characterized by a typical Rdson of 200 m @ 25 °C. And thanks to the current driving concept, this value increases by a comparably moderate 85 % @ 150 °C. As typical for GaN, gate and output c harges are very small (3 and 16 nC, resp.) an d there is no reverse recovery charge due to the lack of a physical body diode (for more information please refer to [1]).

Final Datasheet 10 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage

3 Characteristics

3.1 Absolute maximum ratings

The absolute maximum ratings are listed in Table 6. Stresses beyond these values may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 6 Absolute maximum ratings Parameter Symbol Values Unit Note or Test Conditions Min. Max. Voltage between output pins DH, SW and SL VDHSW VSWSL 600 600 V V VGHSH = 0 V, VGLSL = 0 V Drain-to-source voltage pulsed VDS,pulse - 7501 650 V V TJ = 25°C, VGS ≤ 0 V, cumulated stress time ≤ 1h TJ = 125°C, VGS ≤ 0 V, cumulated stress time ≤ 1h Continuous drain current ID - 5.0 3.7 A A TCase = 25°C TCase = 125°C Pulsed drain current2 ID,pulse - 14.1 7.73 A A TCase = 25°C (see Figure 13) TCase = 125°C (see Figure 13) Supply voltage input chip VDDI -0.3 3.7 V Note4 Supply voltage output chips VDDL/H -0.3 22 V with respect to SW/SL Voltage at pins INL, INH and ENABLE VIN -0.3 17 V Voltage at pin SLDO VSLDO -0.3 VDDI + 0.3 V Voltage at pins OUTL, OUTH VOUTL/H -0.3 VDDL/H + 0.3 V Junction temperature TJ - 40 150 °C Storage temperature TS - 55 150 °C Soldering temperature Tsold - 260 °C reflow/wave soldering5

1 Acc to JEDEC-JEP180

2 Limits derived from product characterization, parameter not measured during production

3 Parameter is influenced by reliability requirements. Please contact the local Infineon Sales Office to get an assessment of your application 4 If the SLDO is activated (SLDON pin tied to GNDI), the input-side supply voltage (VDDL) does not correspond to VDDI and can be higher 5 Acc. to JESD22A111

Final Datasheet 11 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage Parameter Symbol Values Unit Note or Test Conditions Min. Max. ESD capability VESD_HBM - 2 kV Human Body Model1 VESD_CDM - 1.0 kV Charged Device Model2

3.2 Thermal characteristics

Table 7 Thermal characteristics Parameter Symbol Values Unit Note or Test Conditions Min. Typ. Max. Thermal resistance junction-case RthJC - - 3.0 °C/W Thermal resistance junction- ambient RthJA - 35 - °C/W Device mounted on four-layer PCB with 600 mm2 total cooling area

3.3 Recommended operating range

Table 8 Recommended operating range 1 Acc. to EIA/JESD22-A114-B (discharging 100 pF capacitor through 1.5 kΩ resistor) 2 Acc. to JESD22-002 3 Parameter is influenced by rel-requirements. Contact the local Infineon Sales Office to get an assessment of your application. 4 We recommend to use RC interface gate drive to optimize the device performance. Please see gate drive application note for details.

5 Continuous operation above 125°C may reduce lifetime

Parameter Symbol Values Unit Note or Test Conditions Min. Typ. Max. Input supply voltage VDDI 3 3.3 3.5 V if operated directly without SLDO Driver output supply voltages VDDL/H 5.5 8 12 V min. defined by UVLOout VDDI blocking capacitance CVDDI 10 - 22 nF SLDO active Logic input voltage at pins INL, INH and ENABLE VIN 0 - 6.5 V Voltage at pin SLDO VSLDO 0 - 3.5 V Gate current, continuous3 4 IG, avg - - 6.9 mA Junction temperature TJ -40 - 125 5 °C

Final Datasheet 12 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage

3.4 Electrical characteristics

Unless otherwise noted, min/max values of characteristics are the lower and upper limits, resp. They are valid within the full operating range. All values are given at TJ = 25 °C with VDDI = 3.3 V and VDDL/H = 8 V. Table 9 Power supply Parameter Symbol Values Unit Note or Test Conditions Min. Typ. Max. VDDI quiescent current1 IVDDIqu - 1.4 - mA no switching VDDL quiescent current1 IVDDLqu - 0.7 - mA no switching VDDH quiescent current1 IVDDHqu - 0.7 - mA no switching Undervoltage Lockout input (UVLOVDDI) turn-on threshold UVLOVDDI 2.75 2.85 2.95 V UVLOVDDI turn-off threshold UVLOVDDI- - 2.7 - V UVLOVDDI threshold hysteresis UVLOVDDI 0.1 0.15 0.2 V Undervoltage Lockout outputs (UVLOVDDL/H) turn-on threshold UVLOoutLH 4.0 4.2 4.4 V UVLOVDDL/H turn-off threshold UVLOVDDL/H - - 3.9 - V UVLOVDDL/H threshold hysteresis UVLOVDDL/H 0.2 0.3 0.4 V Table 10 Logic inputs INL, INH and ENABLE Parameter Symbol Values Unit Note or Test Conditions Min. Typ. Max. Input voltage threshold for transition LH VIN+ 1.7 2.0 2.3 V independent of VDDI Input voltage threshold for transition HL VIN- - 1.2 - V independent of VDDI Input voltage threshold hysteresis VIN_hys 0.4 0.8 1.2 V Input pull down resistor RIN - 150 - k 1 Can be completely eliminated in stand-by mode by utilizing external supply switch (see chapter 2.2)

Final Datasheet 13 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage Table 11 Static gate driver output characteristics Parameter Symbol Values Unit Note or Test Conditions Min. Typ. Max. High-level (sourcing) output resistance Ron 1.4 3.1 5.8 Peak sourcing output current1 Isrc,pk - 1 - A actively limited to 1.3 A Low-level (sinking) output resistance Roff 0.6 1.2 2.5  Peak sinking output current1 Isnk,pk - -2 - A actively limited to -2.6 A Active clamp threshold voltage Vclmp - 1 - V Table 12 Output characteristics GaN switches Parameter Symbol Values Unit Note or Test Conditions Min. Typ. Max. Rdson high-side Rdshs - 200 260 m IG = 6.9 mA, ID = 2.1 A, TJ = 25°C TJ = 150°C Rdson low-side Rdsls - 200 260 m IG = 6.9 mA, ID = 2.1 A, TJ = 25°C TJ = 150°C Drain-source leakage current IDSShs, IDSSls - 0.26 - µA VDS = 600 V, VGS = 0 V, TJ = 25°C - 5.3 - µA VDS = 600 V, VGS = 0 V, TJ = 25°C Total gate charge (per switch) 1 QG - 1.5 - nC IG = 0 to 2.6 mA, VDH = 400 V, ID = 2.1 A 1Verified by design / characterization, not tested in production

Final Datasheet 14 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage Table 13 Static characteristics GaN switches Parameter Symbol Value s Unit Note or Test Condition Min. Typ. Max. Gate threshold voltage VGS(th) 0.9 0.7 1.2 1.0 1.6 1.4 V V IDS = 0.69 mA, VDS = 10 V, Tj =25 °C IDS = 0.69 mA, VDS = 10 V, Tj=125°C Gate-source reverse clamping voltage VGS, clamp - - -8 V IGSS1 = -1 mA, Tj =25 °C Gate resistance RG,int - 0.80 - Ω LCR impedance measurement Table 14 Dynamic characteristics GaN switches Parameter Symbol Values Unit Note or Test Condition Min. Typ. Max. Input capacitance Ciss - 100 - pF VGS = 0 V, VDS = 400 V; f = 1MHz Output capacitance Coss - 19.0 - pF VGS = 0 V, VDS = 400 V; f = 1MHz Reverse transfer capacitance Crss - 0.1 - pF VGS = 0 V, VDS = 400 V; f = 1MHz Effective output capacitance, energy related2 Co(er) - 21.1 - pF VGS = 0 V, VDS = 0 to 400 V Effective output capacitance, time related3 Co(tr) - 27.1 - pF VGS = 0 V, VDS = 0 to 400 V Output charge Qoss - 10.8 - nC VDS = 0 to 400 V

1 Gate-Source leakage current

2 Co(er) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 to 400 V 3 Co(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 400 V

Final Datasheet 15 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage Table 15 Reverse conduction characteristics Parameter Symbol Values Unit Note/Test Condition Min. Typ. Max. Source-Drain reverse voltage VSD - 2.2 2.5 V VGS = 0V, ISD = 2.1 A Pulsed current, reverse IS,pulse - - 15.8 A IG = 6.9 mA Reverse recovery charge Qrr1 - 0 - nC ISD = 2.1 A, VDS = 400V Reverse recovery time trr - 0 - ns Peak reverse recovery current Irrm - 0 - A Table 16 Dynamic Characteristics2 (see Figure 4, Figure 5) Parameter Symbol Values Unit Note or Test Conditions Min. Typ. Max. INL to SW propagation delay “on” tPDonL - 47 - ns Rtr = 50  INL to SW propagation delay “off” tPDoffL - 47 - ns Iload = 2 A Propagation delay matching high/low-side tPDonLH tPDoffLH ns ns ENABLE to SW propagation delay tPD_DIS_ON, tPD_DIS_OFF - 70 - ns ns Rise time SW trise - 6 - ns 10 % to 90 % Fall time SW tfall - 5 - ns 90 % to 10 % Minimum input pulse width that changes output state tPW - 18 - ns - Input-side start-up time2 tSTART,VDDI - 7 - µs see Figure 6 Input-side deactivation time2 tSTOP,VDDI - 255 - ns see Figure 6 Input-side deactivation time2 tSTART,VDDL/H - 5 - ns see Figure 6 Output-side deactivation time2 tSTOP,VDDL/H - 110 - ns see Figure 6

1 Excluding Qoss

2 Verified by design / characterization, not tested in production

Final Datasheet 16 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage Table 17 Isolation specifications Parameter Symbol Value Unit Note or Test Conditions Functional isolation Max. Input-to-DH voltage VInDH >1200 VDC production test > 10 ms Max. Input-to-SW voltage VInSW >600 VDC Max. Input-to-SL voltage VInSL >100 VDC Package characteristics Nominal package clearance CLR 1.9 mm shortest distance over air, from any input pin to any high-side output pin Nominal package creepage CRP 1.9 mm shortest distance over surface, from any input pin to any high- side output pin Comparative Tracking Index of package mold CTI >400 V according to DIN EN 60112 (VDE 0303-11) Material group - II - according to IEC 60112 Common Mode Transient Immunity (CMTI) Static Common Mode Transient Immunity12 |CMStatic,H| 300 V/ns VCM = 1500 V; INL, INH tied to VDDI (logic high inputs) |CMStatic,L| 300 V/ns VCM = 1500 V; INL, INH tied to GNDI (logic high inputs) Dynamic Common Mode Transient Immunity1 3 |CMDynamic| 300 V/ns VCM = 1500 V; dynamic INL, INH (10 MHz square wave) 1 minimum slew rate of a common mode voltage at which the output signal is disturbed 2 parameters verified by characterization according to VDE0884-11 standard definitions and test-methods 3 verified by characterization with ground reference for the common mode pulse generator connected to the coupler intput-side ground to reflect real applications requirements

Final Datasheet 17 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage

3.5 Timing diagrams and test circuit

Figure 4 depicts rise, fall and delay times measured at the GaN half -bridge output SW . Figure 5 shows the associated test circuit. The power stage is operated in a boost configuration at a constant current I load. In this so - called double-pulse arrangement I load is determined by the high -voltage supply (400 V), the output inductance and the length of the first “on”-phase of the INL-signal. The specified delay and transient times are related to an Iload value of 2 A (particularly the “off” transient strongly depends on this cu rrent). INH need not be switched for this measurement. VINH VINL INL SW tPDoff 90% tPDon 10% 90% trise tfall 10% Figure 4 Propagation delay, rise and fall time INH ENABLE GNDI VDDI SW INL SLDON SL VDDL OUTL GL OUTH GH VDDH DH 1.5n33 1.5n33 100n 100n +8 V +400 V VDDL 22n +8 V 2 A Figure 5 Test circuit

Final Datasheet 18 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage OUTL/H VDDI UVLOVDDI,on tSTA R T,VDDI tSTOP,VDDI INL/INH VDDL/H High logic level High level ( > UVLOVDDL/H,on ) UVLOVDDI,off ENABLE High logic level OUTL/H VDDL/H UVLOVDDL/H,on tSTA R T,VDDL/H tSTOP,VDDL/H INL/INH VDDI High logic level High level ( > UVLOVDDI,on ) UVLOVDDL/H,off ENABLE High logic level Figure 6 UVLO behavior, start-up and deactivation time (unloaded output)

Final Datasheet 19 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage

4 Driving CoolGaNTM HEMTs

Although Gallium Nitride High Electron Mobility Transistors (GaN HEMTs) with ohmic connection to a pGaN gate are robust enhancement-mode (“normally-off”) devices, they differ significantly from MOSFETs. The gate module is not isolated from the channel, but behaves like a diode with a forward voltage VF of 3 to 4 V. Equivalent circuit and typical gate input characteristic are given in Figure 7. In the steady “on” state a continuous gate current is required to achieve stable operating conditions. The switch is “normally -off”, but the threshold voltage V th is rather low (~ +1 V). This is why in many applic ations a negative gate voltage -VN, typically in the range of several Volts, is required to safely keep the switch “off” (Figure 7b). Figure 7 Equivalent circuit (a) and gate input characteristics (b) of typical normally-off GaN HEMT Obviously the transistor in Figure 7 cannot be driven like a conventional MOSFET due to the need for a steady-state “on” current Iss and a negative “off” voltage –VN. While an Iss of a few mA is sufficient, fast switching transients require gate charging currents Ion and Ioff in the 1 A range. To avoid a dedicated driver with 2 separate “on” paths and bipolar supply voltage, the solution depicted in Figure 8 is usually chosen, combining a standard gate driver with a passive RC circuit to achieve the intended behavior. The high -current paths containing the small gate resistors R on and Roff, respectively, are connected to the gate via a coupling capacitance C C. CC is chosen to have no significant effect on the dynamic gate currents Ion and Ioff. In parallel to the high-current charging path the much larger resistor R ss forms a direct gate connection to continuously deliver the small steady-state gate current Iss. In addition, CC can be used to generate a negative gate voltage. Obviously, in the “on” -state CC is charged to the difference of driver supply V DD and diode voltage V F. When switching off , this charge is redistributed between C C and CGS and causes an initial negative VGS of value: 𝑉𝑁 = 𝐶𝐶 ∙ (𝑉𝐷𝐷 − 𝑉𝐹) − 𝑄𝐺 𝐶𝐶 + 𝐶𝐺𝑆 (2) with QG denoting the total gate charge . VN can thus be controlled by proper choice o f VDD and CC. During the „off“ state the negative V GS decreases, as C C is discharged via R SS. The associated time constant cannot be chosen independently, but is related to the steady-state current and is typically in the 1 s range. The negative gate voltage at the end of the “off” phase (VNf in Figure 8b) thus depends on the “off” duration. It lowers the effective driver voltage for the following switching -on event, resulting in a slight dependence of switching dynamics on frequency and duty cycle. However, in most applications the impact of this effect is negligible. Another situation requires attention, too. If there is by any reason a longer period with both switches of a half -bridge in “off”-state (e.g. duri ng system start -up, burst mode operation etc.), both capacitors C C will be discharged. That

Final Datasheet 20 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage means, for the first switching pulse after such an extended non-switching period no negative voltage is available. To avoid instabilities due to spurious turn-on effects in such a situation, CC should not be chosen lower than 1 nF. CGD CGS CDS D G S Ioff Roff Rtr GaN switch Driver Ion Rss Iss VDD OUT CC offon t 3.5V VDD VGS VF -VN -VNf Figure 8 Equivalent circuit of GaN switch with RC gate drive (a) and gate-to-source voltage VGS (b) In the topology of Figure 8 often a single resistor R tr can be used for setting the maximum transient charging and discharging current. If this is not acceptable by any reason, an additional resistor Roff with series diode in parallel with Rtr can be used to realize independent gate impedances for the “on” and “off” transient, respectively. All relev ant driving parameters are easily programmable by choosing V DD, Rss, R tr, Roff and C C according to the relations 𝑉𝑁 = 𝐶𝐶 ∙ (𝑉𝐷𝐷 − 𝑉𝐹) − 𝑄𝐺 𝐶𝐶 + 𝐶𝐺𝑆 (3) 𝐼𝑠𝑠 = 𝑉𝐷𝐷 − 𝑉𝐹 𝑅𝑠𝑠 , 𝐼𝑜𝑛,𝑚𝑎𝑥~ 𝑉𝐷𝐷 − 𝑉𝑁𝑓 𝑅𝑡𝑟 , 𝐼𝑜𝑓𝑓,𝑚𝑎𝑥~ (𝑉𝑡ℎ + 𝑉𝑁) ∙ (𝑅𝑜𝑓𝑓 + 𝑅𝑡𝑟) 𝑅𝑜𝑓𝑓 ∙ 𝑅𝑡𝑟 The main guidelines for dimensioning gate drive parameters are as follows: - VN must always be positive; a target value of 2 V in soft-switching and 4 V to 5 V in hard-switching systems is recommended - The target value of Iss is around 3 mA, Rss has to be chosen accordingly - Rtr sets the transient speed for a hard switching “on” event. Due to the low gate charge, values above 50  typically do not result in significant benefits. For soft switching systems R tr is anyway uncritical. - If a separate Roff is used, it should guarantee sufficient damping of oscillations in the gate loop. For a given driving voltage the values for the gate drive components can now be derived from equations ( 3). VDD = 8 V, for example, yields - CC = 1.2 nF - Rss = 2 k - Rtr = 27 … 68  - Roff = 10  (if used) For more information regarding how to drive GaN HEMT refer to [2] [3].

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5 Typical characteristics

5.1 GaN switch characteristics

The following graphs refer to a single GaN switch. ID=f(VDS,IGS); Tj=25°C ID=f(VDS,IGS); Tj=125°C Figure 9 Typical output characteristics RDS(on)=f(ID,IG); Tj=125°C RDS(on)=f(Tj); ID=2.11 A Figure 10 Typical drain-source on-resistance 0 2 4 6 8 10 ID [A] VDS [V] 26 µA 69 µA 260 µA 690 µA 2.6 mA 6.9 mA 0 2 4 6 8 10 ID [A] VDS [V] 26 µA 69 µA 260 µA 690 µA 2.6 mA 6.9 mA 130 180 230 280 330 380 -50 0 50 100 150 RDS(on) [mΩ] Tj [oC] IG = 6.9 mA VGS = 3 V 300 350 400 450 500 550 600 0 5 10 15 20 RDS(on) (mΩ) ID [A] 26 µA 69 µA 260 µA 690 µA 2.6 mA 6.9 mA

Final Datasheet 24 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage Figure 15 Typical output energy (single switch)

5.2 Gate driver characteristics

Typical VDDI quiescent current vs. temperature Typical VDDI current vs. temperature and frequency Figure 16 Supply current VDDI 0 200 400 600 EOSS [μJ] VDS [V]

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6 Application circuit

In Figure 21 a typical application example is given with IGI60F2020A1L operated in an actively clamped flyback topology. In this application the recommended values for the gate drive circuit are as follows: VDD = 8 V CC = 1.2 nF Rss = 2 k Rtr = 27 … 68  CoolGaNTM INH ENABLE GNDI VDDI TX UVLO Control Logic RX UVLO Logic SW RX UVLO Logic TX INL SLDON SLDO SL VDDL OUTL GL OUTH GH VDDH DH CT CCRtr Rss CC Rtr Rss CVDDL Cboot VDDL Rsense Dboot Cout Vin Controller RVDDI GND GPIOx PWML PWMH CoolGaNTM IPS Vout Cclmp Is CVDDI VDDL Figure 21 Application Circuit (active clamp flyback converter)

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7 Package information

Figure 22 TIQFN-28-1 8x8 package outline and footprint

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8 Layout guidelines

Figure 23 shows the suggested arrangement of the power stage and the external components on the PCB based on the schematic shown in the Figure 24. Figure 25 and Figure 26 show the top and bottom layer of the PCB. The following layout recommendations should be considered: 1. On the exposed pads’ landing area place vias with 0.3mm hole size with <0.7mm space (center to center) 2. Use solder mask expansion of 0.05~0.075mm for the chipset footprint pins and pads 3. Place and align the GND trace (PGND node for power return) beneath the DC bus trace on the top layer to minimize the inductance loop in the power path. 4. For the low voltage controller reference (DGND) on the PGND trace select a location free of any switching current to avoid switching-induced noise in DGND ( do not connect the DGND trace to any trace which connects the bypass cap to CoolGaNTM). Figure 23 CoolGaNTM IPS external component placement on the PCB

Final Datasheet 31 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage Figure 26 Bottom layer of the PCB - top view (Trace on the left and silk mask on the right)

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9 Appendix

I. PCB footpriont and Altium file for the reference PCB design can be found in the CoolGaNTM Half-bridge IPS webpage (product registration is needed to access the design files) II. Related Links IFX CoolGaNTM webpage: www.infineon.com/why-coolgan IFX CoolGaNTM reliability white paper: www.infineon.com/gan-reliability IFX CoolGaNTM applications information: www.infineon.com/gan-in-server-telecom www.infineon.com/gan-in-wirelesscharging www.infineon.com/gan-in-adapter-charger

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10 References

[1] CoolGaN™ application note [2] Driving CoolGaN™ 600 V high electron mobility transistors [3] Quick-reference guide to driving CoolGaN™ GIT HEMTs 600V

Final Datasheet 34 of 35 V1.1 2023-05-05 IGI60F2020A1L CoolGaNTM Integrated Power Stage

Revision history

Document version Date of release Description of changes V1.0 2023-02-14 1st version of final datasheet V1.1 2023-05-05 Products overview update with marking information

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