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A bsolute M axim um Ratings M in M ax U nit N otes Input voltage (+In to –In) O perating 3 6 60 V dc N on-operating 75 V dc <1 00 m S Input voltage slew rate 5 V / μs EN to –IN -0.5 2 0 V dc O utput voltage (+O ut to –O ut) -0.5 1 3 .8 V dc O utput current 48 A Pout ≤ 5 00 W Dielectric w ithstand (input to output) 1 ,5 00 V dc 1 m in. Tem perature O perating junction -40 1 2 5 °C H ottest Sem iconductor Storage -5 5 1 2 5 °C [A ] F or low er pow er applications see 3 00 W m odel IB048E096T40N 1 -00 A pplications
- Enterprise netw orks
- O ptical access netw orks
- Storage netw orks
- A utom ated test equipm ent Size: 2 .3 0 x 0.9 x 0.3 8 in 5 8,4 x 2 2 ,9 x 9,5 m m
IBC M O D U LE Rev 1.5 vicorpow er.com Page 2 of 13 1 0/2 01 2 80 0 73 5 .620 0 IB0 48E0 96T48N 1-0 0 A ttribute Sym bol Conditions / N otes M in Typ M ax U nit IN PU T (O perating from DC input source) O perating input voltage 3 8 48 5 5 V dc N on-operating input surge w ithstand <1 00 m S 75 V dc O perating input dV /dt 0.003 5 V /us U ndervoltage protection Turn-on 3 1 3 6 V dc Turn-off 2 9 3 4 V dc Turn-o n/Turn-off hysteresis 2 V dc Tim e constant 7 µs U ndervoltage blanking tim e U V blanking tim e is enabled after start up 5 0 1 00 2 00 µs O vervoltage protection Turn-off 60 64 V dc Turn-on 5 5 64 V dc Tim e constant 4 µs Turn O N delay Start up inhibit V IN reaching turn-on voltage 2 0 2 5 3 0 m s to enable function operational, see F igure 6 Turn-on delay Enable to 9 0% V O U T ; pre-applied V IN , see F igure 7, 5 0 µs 0 load capacitance F rom 1 0% to 90% Vout, 1 0% load, O utput voltage rise tim e 0 load capacitance. 5 0 µs Restart turn-on delay See page 1 0 for resart after EN pin disable 2 5 0 m s N o Load pow er dissipation Enabled 1 .9 2 .5 W Disabled 0.1 8 0.2 1 W Input current Low line, full load 9.8 A Inrush current overshoot U sing test circuit in F igure 2 1 1 3 .5 A Input reflected ripple current A t m ax pow er; 5 00 m A rm s U sing test circuit in F igure 2 2 Peak short circuit input current 40 A Repetitive short circuit peak current 2 5 A Internal input capacitance 8.8 μF Internal input inductance 5 nH Recom m ended external 2 00 nH m axim um source inductance 47 470 μFinput capacitance O U TPU T DC O utput voltage band N o load, over V in range 7.6 9.6 1 1 .0 V O utput pow e r[a] 3 8-5 5 V IN 0 3 60 W 48-5 5 V IN 0 45 0 W 5 4-5 5 V IN 0 5 00 W O utput current P ≤ 5 00 W 48 A O utput start up load of Iout m ax, m axim um output capacitance 1 5 % Effective output resistance 4.7 m Ω Line regulation (K factor) V O U T = K • V IN @ no load 0.1 98 0.2 00 0.2 02 0 A ll specifications valid at 4 8 V IN , 10 0 % rated load and 25 °C am bient, unless otherw ise indicated. SPECIFICATIO N S
Electrical Characteristics
[a] Does not exceed IPC-95 92 derating guidelines. A t 70 °C am bient, full pow er operation m ay exceed IPC-95 92 guidelines, but does not exceed com ponent ratings, does not activate O TP and does not com prom ise reliability.
IBC M O D U LE Rev 1.5 vicorpow er.com Page 3 of 13 1 0/2 01 2 80 0 73 5 .620 0 IB0 48E0 96T48N 1-0 0 A ttribute Sym bol Conditions / N otes M in Typ M ax U nit O U TPU T (Continued) Current share accuracy F ull pow er operation; See Parallel O peration 1 0 % on page 1 1 ; up to 3 units Efficiency 5 0% load See F igure 1 ,2 and 3 97.5 98.0 % F ull load See F igure 1 ,2 and 3 96.9 97.1 % Internal output inductance 1 .6 nH Internal output capacitance 5 5 μF Load capacitance N om inal load 0 45 00 μF O utput O V P set point M odule w ill shutdow n 1 2 .0 1 2 .8 V dc O utput voltage ripple 2 0 M H z bandw idth, using test circuit in 60 1 5 0 m V p-p F igure 2 3 O f Iout m ax., w ill not shutdow n w hen started O utput O verload protection threshold into m ax Cout and 1 5 % load 1 05 1 5 0 % A uto restart w ith duty cycle <1 0% O ver current protection tim e constant 5 m s Short circuit current response tim e 1 .5 µs Sw itching frequency 1 .0 M H z Transient Response Voltage overshoot 2 5 % load step; See F igures 1 1 - 1 4 1 00 m V using test set up in F igure 2 4 Response tim e See F igures 1 1 - 1 4 using test set up in F igure 2 4 1 µs V IN step 5 V step in 1 µs w ithin V in operating range 1 .2 5 V Pre-bias voltage U nit w ill start up 0 1 2 V dc into pre-bias voltage on output Electrical Characteristics (Continued) SPECIFICATIO N S (CO N T.) A ttribute Sym bol Conditions / N otes M in Typ M ax U nit M TBF Calculated per Telcordia SR-3 3 2 , 40 °C 1 .0 M hrs Service life Calculated at 3 0 °C 7 Years O ver tem perature shut dow n TJ ; Converter w ill reset w hen over 1 2 5 1 3 0 1 3 5 °C tem perature condition is rem oved Dielectric w ithstand Input to output 1 ,5 00 V dc Insulation resistance Input to output 3 0 MΩ M echanical W eight 0.71 / 2 0.3 oz/g Length 2 .3 0/5 8.4 in / m m W idth 0. 9/ 2 2 .9 in / m m H eight above custom er board 0.3 8/9.5 in / m m Clearance to custom er board F rom low est com ponent on IBC 0.1 2 /3 .0 in / m m A gency approvals U L/ cU L 6095 0-1 , EN 6095 0-1 , IEC 6095 0-1 cTU Vus Low voltage directive (CE M ark) CE A ltitude, operating Derate operating tem p 1 °C -5 00 1 0,000 F eet per 1 ,000 feet above sea level Relative hum idity, O perating N on condensing 1 0 90 % RoH S com pliance Com patible w ith RoH S directive 2 00 2 / 95 / EC G eneral Characteristics A ll specifications valid at 4 8 V IN, 10 0 % rated load and 25 °C am bient, unless otherw ise indicated. Conditions: 25°C case, 75% rated load and specified input voltage range unless otherw ise specified.
IBC M O D U LE Rev 1.5 vicorpow er.com Page 4 of 13 1 0/2 01 2 80 0 73 5 .620 0 IB0 48E0 96T48N 1-0 0 Test D escription Test D etail Q uantity Tested Low Tem p 3 H igh Tem p 3 Rapid Therm al Cycling 3 5 .2 .3 H A LT (H ighly A ccelerated Life testing) 6 DO F Random V ibration Test 3 Input Voltage Test 3 O utput Load Test 3 Com bined Stresses Test 3 5 .2 .4 TH B (Tem p. H um idity Bias) (72 hr presoak required) 1 000 hrs – Continuous Bias 3 0 Pow er cycle - O n 42 m inutes 5 .2 .5 H TO B (H igh Tem p. O perating Bias) O ff 1 m inute, O n 1 m inute, O ff 1 m inute, O n 1 m inute, O ff 1 m inute, 3 0 O n 1 m inute, O ff 1 m inute, O n 1 m inute, O ff 1 0 m inutes. A lternating betw een m axim um and m inim um operating Voltage every hour. 5 .2 .6 TC (Tem p. Cycling) 700 cycles , 3 0 m inute dw ell at each extrem e – 2 0C m inim um ram p rate. 3 0 5 .2 .7 Pow er Cycling Reference IPC-95 92 A 3 Random V ibration – O perating IEC 60068-2 -64 (norm al operation vibration) 3 Random V ibration N on-operating (transportation) IEC 60068-2 -64 3 5 .2 .8 – 5 .2 .1 3 Shock and V ibration Shock O perating - norm al operation shock IEC 60068-2 -2 7 3 F ree fall - IEC 60068-2 -3 2 3 Drop Test 1 full shipping container (box) 1 2 5 .2 .1 4.1 Corrosion Resistance – N ot required N /A 5 .2 .1 4 O ther Environm ental Tests 5 .2 .1 4.2 Dust Resistance – U npotted class II G R-1 2 74-CO RE 3 5 .2 .1 4.3 SM T A ttachm ent Reliability IPC-9701 - J-STD-002 3 5 .2 .1 4.4 Through H ole solderability – J-STD-002 5 ESD Classification Testing Sam ple size assum es CDM testing 1 2 Total Q uantity 161 Environm ental Q ualification SPECIFICATIO N S (CO N T.) IPC-9592A , Based on Class II Category 2 the follow ing detail is applicable. – Pre-conditioning required A ttribute Sym bol Conditions / N otes M in Typ M ax U nit Enable (negative logic)* Referenced to –IN M odule enable threshold 0.8 V dc M odule enable current V EN = 0.8 V 1 3 0 2 00 µA M odule disable threshold 2 .4 V dc M odule disable current V EN = 2 .4 V 1 0 µA Disable hysteresis 5 00 m V Enable pin open circuit voltage 2 .5 3 .0 V dc EN to –IN resistance O pen circuit, 1 0 V applied betw een EN and -IN 3 5 kΩ Enable (positive logic)* Referenced to –IN M odule enable threshold 2 .0 2 .5 3 .0 V dc M odule disable threshold 1 .45 V dc EN source current (operating) V EN = 5 V 2 m A EN voltage (operating) 4.7 5 5 .3 V dc Control & Interface Specifications *See part num bering on page 1 1
IBC M O D U LE Rev 1.5 vicorpow er.com Page 5 of 13 1 0/2 01 2 80 0 73 5 .620 0 IB0 48E0 96T48N 1-0 0 Efficiency TAMB 25 °C Efficiency (%) Iout (A)
38 V 48 V 55 V V :IN
Efficiency TAMB 55 °C Efficiency (%) Iout (A) Efficiency TAMB 70 °C Efficiency (%) Iout (A) Figure 1 — Efficiency vs. output current, 25°C am bient Figure 2 — Efficiency vs. output current, 55°C am bient Figure 3 — Efficiency vs. output current, 70 °C am bient Figure 4 — Inrush current at high line 15% load Figure 5 — Input reflected ripple current at nom inal line, full load Figure 6 — Turn on delay tim e; VIN turn on delay at nom inal line, 15% load; start up inhibit tim e SPECIFICATIO N S (CO N T.) W AVEFO RM S
IBC M O D U LE Rev 1.5 vicorpow er.com Page 8 of 13 1 0/2 01 2 80 0 73 5 .620 0 IB0 48E0 96T48N 1-0 0 SPECIFICATIO N S (CO N T.) Output Current (A) Output Current Derating Ambient Air Temperature (°C)
200 LFM 400 LFM 600 LFM
Figure 19 — M axim um output pow er derating vs am bient air tem perature. Transverse airflow , Board and junction tem peratures <125 °C tested w ith IBC evaluation board IB0 4 8E0 96T4 8N 1-CB Output Current (A) Output Current Derating Ambient Air Temperature (°C) Figure 20 — M axim um output pow er derating vs am bient air tem perature. Longitudinal airflow , Board and junction tem peratures <125 °C tested w ith IBC evaluation board IB0 4 8E0 96T4 8N 1-CB Vsource Current Probe 47 µF IBC +IN EN –IN +OUT –OUT Load *Maximum load capacitance Figure 21 — Inrush current overshoot Vsource Current Probe 470 µF IBC +IN EN –IN +OUT –OUT Load 10 µH Figure 22 — Input reflected ripple current SPECIFICATIO N S +IN –IN +OUT –OUT IBC E – Load Cy = 4700 pF
20 MHz BW
10 µF 0.1 µF Cy b Cy d Cy cCy a a-d Figure 23 — Test circuit; output voltage ripple Vsource CIN IBC +IN EN –IN +OUT –OUT Load COUT RL CIN = 500 µF COUT = 0.4 x [ POUT MAX (w) ] µF VOUT 0.25 x IOUT MAX RL Ω= Figure 24 — Load transient response
IBC M O D U LE Rev 1.5 vicorpow er.com Page 10 of 13 1 0/2 01 2 80 0 73 5 .620 0 IB0 48E0 96T48N 1-0 0 + In / -In – D C Voltage Input Pins The IBC input voltage range should not be exceeded. A n internal undervoltag e/ overvoltage lockout function prevents operation outside of the norm al operating input range. The IBC turns on w ithin an input voltage w indow bounded by the “Input under-voltage turn-on” and “Input over-voltage turn-off” levels, as specified. The IBC m ay be protected against accidental application of a reverse input voltage by the addition of a rectifier in series w ith the positive input, or a reverse rectifier in shunt w ith the positive input located on the load side of the input fuse. The connection of the IBC to its pow er source should be im plem ented w ith m inim al distribution inductance. If the interconnect inductance exceeds 1 00 nH , the input should be bypassed w ith a RC dam per to retain low source im pedance and stable operation. W ith an interconnect inductance of 2 00 nH , the RC dam per m ay be 47 μF in series w ith 0.3 Ω. A single electrolytic or equivalent low -Q capacitor m ay be used in place of the series RC bypass. EN - Enable/D isable N egative Logic O ption If the EN port is left floating, the IBC output is disabled. O nce this port is - pulled low er than 0.8 V dc w ith respect to –In, the output is enabled. The EN port can be driven by a relay, opto-coupler, or open collector transistor. Refer to F igures 6 and 7 for the typical enable / disable characteristics. This port should not be toggled at a rate higher than 1 H z. The EN port should also not be driven by or pulled up to an external voltage source. Positive Logic O ption If the EN port is left floating, the IBC output is enabled. O nce this port is pulled low er than 1 .4 V dc w ith respect to –In, the output is disabled. This action can be realized by em ploying a relay, opto-coupler, or open collector transistor. This port should not be toggled at a rate higher than 1 H z. The EN port should also not be driven by or pulled up to an external volt - age source. The EN port can source up to 2 m A at 5 V dc. The EN port should never be used to sink current. If the IBC is disabled using the EN pin, the m odule w ill attem pt to restart approxim ately every 2 5 0m s. O nce the m odule has been disabled for at least 2 5 0m s, the turn on delay after the EN pin is enabled w ill be as show n in F igure 7. + O ut / -O ut – D C Voltage O utput Pins Total load capacitance at the output of the IBC should not exceed the specified m axim um . O w ing to the w ide bandw idth and low output im pedance of the IBC, low frequency bypass capacitance and significant energy storage m ay be m ore densely and efficiently provided by adding capacitance at the input of the IBC. PIN / CO N TRO L FU N CTIO N S Top View Pin Function
1 V in+
2 Enable
3 V in-
4 Vout-
5 Vout+
Figure 31 — IBC Pin D esignations
IBC M O D U LE Rev 1.5 vicorpow er.com Page 11 of 13 1 0/2 01 2 80 0 73 5 .620 0 IB0 48E0 96T48N 1-0 0 Parallel O peration The IBC w ill inherently current share w hen operated in an array. A rrays m ay be used for higher pow er or redundancy in an application. Current sharing accuracy is m axim ized w hen the source and load im pedance presented to each IBC w ithin an array are equal. The recom m ended m ethod to achieve m atched im pedances is to dedicate com m on copper planes w ithin the PCB to deliver and return the current to the array, rather than rely upon traces of varying lengths. In typical applications the current being delivered to the load is larger than that sourced from the input, allow ing narrow er traces to be utilized on the input side if necessary. The use of dedicated pow er planes is, how ever, preferable. O ne or m ore IBCs in an array m ay be disabled w ithout adversely affecting operation or reliability as long as the load does not exceed the rated pow er of the enabled IBCs. The IBC pow er train and control architecture allow bi-directional pow er transfer, including reverse pow er processing from the IBC output to its input. The IBC’s ability to process pow er in reverse im proves the IBC tran - sient response to an output load dum p. Therm al Considerations The tem perature distribution of the V I Brick can vary significantly w ith its inpu t/output operating conditions, therm al m anagem ent and environm ental conditions. A lthough the PCB is U L rated to 1 3 0 °C, it is recom m ended that PCB tem peratures be m aintained at or below 1 2 5 °C. F or m axim um long term reliability, low er PCB tem peratures are recom m ended for continuous operation, how ever, short periods of operation at 1 2 5 °C w ill not negatively im pact perform ance or reliability. W A RN IN G : Therm al and voltage hazards. The IBC can operate w ith surface tem peratures and operating voltages that m ay be hazardous to personnel. Ensure that adequate protection is in place to avoid inadvertent contact. Input Im pedance Recom m endations To take full advantage of the IBC capabilities, the im pedance presented to its input term inals m ust be low from DC to approxim ately 5 M H z. The source should exhibit low inductance and should have a critically dam ped response. If the interconnect inductance is excessive, the IBC input pins should be bypassed w ith an RC dam per (e.g., 47 μF in series w ith 0.3 Ω) to retain low source im pedance and proper operation. G iven the w ide bandw idth of the IBC, the source response is generally the lim iting factor in the overall system response. A nom alies in the response of the source w ill appear at the output of the IBC m ultiplied by its K factor. The DC resistance of the source should be kept as low as possible to m inim ize voltage deviations. This is especially im portant if the IBC is operated near low or high line as the overvoltag e/ undervoltage detection circuitry could be activated. Input Fuse Recom m endations The IBC is not internally fused in order to provide flexibility in configuring pow er system s. H ow ever, input line fusing of V I Bricks m ust alw ays be incorporated w ithin the pow er system . A fast acting fuse should be placed in series w ith the +In port. See safety agency approvals. A pplication N otes F or IBC and V I Brick application notes on soldering, therm al m anagem ent, board layout, and system design visit vicorpow er.com . A PPLICATIO N S N O TE IB 048 = 3 8-5 5 V dc E 096 T 48 N = N egative 1 = 0.1 45 -00 = O pen fram e P = Positive 2 = 0.2 1 0 3 = 0.1 80 PA RT N U M BERIN G Product Fam ily Input Voltage Package N om inal O utput Voltage Tem perature G rade O utput Current Enable Logic Pin Length O ptions
IBC M O D U LE Rev 1.5 vicorpow er.com Page 13 of 13 1 0/2 01 2 80 0 73 5 .620 0 IB0 48E0 96T48N 1-0 0 Vicor’s com prehensive line of pow er solutions includes high density A C-D C and D C-D C m odules and ac - cessory com ponents, fully configurable A C-D C and D C-D C pow er supplies, and com plete custom pow er system s. Inform ation furnished by V icor is believed to be accurate and reliable. H ow ever, no responsibility is assum ed by V icor for its use. V icor m akes no representations or w arranties w ith respect to the accuracy or com pleteness of the contents of this publication. V icor reserves the right to m ake changes to any products, specifications, and product descriptions at any tim e w ithout notice. Inform ation published by V icor has been checked and is believed to be accurate at the tim e it w as printed; how ever, V icor assum es no responsibility for inaccuracies. Testing and other quality controls are used to the extent V icor deem s necessary to support V icor’s product w arranty. Except w here m andated by governm ent requirem ents, testing of all param eters of each product is not necessarily perform ed. Specifications are subject to change w ithout notice. Vicor’s Standard Term s and Conditions A ll sales are subject to V icor’s Standard Term s and Conditions of Sale, w hich are available on V icor’s w ebpage or upon request. Product W arranty In V icor’s standard term s and conditions of sale, V icor w arrants that its products are free from non-conform ity to its Standard Specifications (the “Ex - press Lim ited W arranty”). This w arranty is extended only to the original Buyer for the period expiring tw o (2 ) years after the date of shipm ent and is not transferable. U N LESS O TH ERW ISE EXPRESSLY STA TED IN A W RITTEN SA LES A G REEM EN T SIG N ED BY A DU LY A U TH O RIZED V ICO R SIG N A TO RY, V ICO R DISCLA IM S A LL REPRESEN TA TIO N S, LIA BILITIES, A N D W A RRA N TIES O F A N Y KIN D (W H ETH ER A RISIN G BY IM PLICA TIO N O R BY O PERA TIO N O F LA W ) W ITH RE - SPECT TO TH E PRO DU CTS, IN CLU DIN G , W ITH O U T LIM ITA TIO N , A N Y W A RRA N TIES O R REPRESEN TA TIO N S A S TO M ERCH A N TA BILITY, F ITN ESS F O R PA RTICU LA R PU RPO SE, IN F RIN G EM EN T O F A N Y PA TEN T, CO PYRIG H T, O R O TH ER IN TELLECTU A L PRO PERTY RIG H T, O R A N Y O TH ER M A TTER. This w arranty does not extend to products subjected to m isuse, accident, or im proper application, m aintenance, or storage. V icor shall not be liable for collateral or consequential dam age. V icor disclaim s any and all liability arising out of the application or use of any product or circuit and assum es no liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using V icor products and com ponents. Prior to using or distributing any products that include V icor com ponents, buyers should provide adequate design, testing and operat - ing safeguards. V icor w ill repair or replace defective products in accordance w ith its ow n best judgm ent. F or service under this w arranty, the buyer m ust contact V icor to obtain a Return M aterial A uthorization (RM A ) num ber and shipping instructions. Products returned w ithout prior authorization w ill be re - turned to the buyer. The buyer w ill pay all charges incurred in returning the product to the factory. V icor w ill pay all reshipm ent charges if the prod - uct w as defective w ithin the term s of this w arranty. Life Support Policy V ICO R’S PRO DU CTS A RE N O T A U TH O RIZED F O R U SE A S CRITICA L CO M PO N EN TS IN LIF E SU PPO RT DEV ICES O R SYSTEM S W ITH O U T TH E EXPRESS PRIO R W RITTEN A PPRO VA L O F TH E CH IEF EXECU TIV E O F F ICER A N D G EN ERA L CO U N SEL O F V ICO R CO RPO RA TIO N . A s used herein, life support de - vices or system s are devices w hich (a) are intended for surgical im plant into the body, or (b) support or sustain life and w hose failure to perform w hen properly used in accordance w ith instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical com ponent is any com ponent in a life support device or system w hose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Per V icor Term s and Conditions of Sale, the user of V icor products and com ponents in life support applications assum es all risks of such use and indem nifies V icor against all liability and dam ages. Intellectual Property N otice V icor and its subsidiaries ow n Intellectual Property (including issued U .S. and F oreign Patents and pending patent applications) relating to the prod - ucts described in this data sheet. N o license, w hether express, im plied, or arising by estoppel or otherw ise, to any intellectual property rights is granted by this docum ent. Interested parties should contact V icor's Intellectual Property Departm ent. The products described on this data sheet are protected by the follow ing U .S. Patents N um bers: 5 ,945 ,1 3 0; 6,403 ,009; 6,71 0,2 5 7; 6,91 1 ,848; 6,93 0,893 ; 6,93 4,1 66; 6,940,01 3 ; 6,969,909; 7,03 8,91 7; 7,1 66,898; 7,1 87,2 63 ; 7,3 61 ,844; D496,906; D5 05 ,1 1 4; D5 06,43 8; D5 09,472 ; and for use under 6,975 ,098 and 6,984,965 . Vicor Corporation 2 5 F rontage Road A ndover, M A , U SA 01 81 0 Tel: 800-73 5 -62 00 F ax: 978-475 -671 5 em ail Custom er Service: custserv@vicorpow er.com Technical Support: apps@vicorpow er.com