IA88C00 INNOVASIC | Alldatasheet
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Copyright 2005 IA88C00 Microcontroller Data Sheet
Microcontroller As of Production Version -01 Copyright 2005 ENG 21 0 050519-00 www.Innovasic Innovasic.com Innovasic Semiconductor Page 3 of 80 1.888.824.4184
Microcontroller As of Production Version -01 Copyright 2005 ENG 21 0 050519-00 www.Innovasic Innovasic.com Innovasic Semiconductor Page 4 of 80 1.888.824.4184 Please Note Included under Ordering Information on page 68 are enhanced RoHS-compliant versions of the IA88C00. However, standard packaged or non RoHS-compliant versions of the IA88C00 microcontroller are still available.
Features
- Fully Form, Fit and Function Compatible with the Super8 (Z88C00)
- Available in 48-, and 68-pin packages
- Fully Compatible with the Super8 Instruction Set
- Rich Program Register Set
- 128 Kbytes external program address space
- Built-in Direct Memory Access (DMA)
- Two Programmable 16-bit counter/timers with 8-bit prescalers
- Up to 32 General Purpose I/O Lines including special handshake funtionality
- Robust Interrupt structure
- Watch-Dog Timer General Description The IA88COO is a form, fit and function replacement for the original Zilog Z88C00 microcontroller. Innovasic Semiconductor produces replacement ICs using its MILES TM , or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILES TM captures the design of a clone so it can be produced even as silicon technology advances. MILES TM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This Data Sheet documents all necessary engineering information about the IA88COO including functional and I/O descriptions, electrical characteristics, and applicable timing. The function block diagram of the IA88C00 is shown in Figure 1. The device is available in a 48-pin DIP (Figure 2) and a 68-pin PLCC package (Figure 3). The pin functions of the IA88COO are outlined in
Figure 6. Pin Functions .
Figure 1. Functional Block Diagram
Figure 2. 48-Lead DIP Package
Figure 3. 48-Lead DIP Pin Assignments
11 Vcc Power Supply Input
12 XTAL2 Crystal Oscillator Output
13 XTAL1 Crystal Oscillator Output
18 P22 Port 2, pin 2 Input/Output
31 R/W READ/WRITE Output
34 GND Ground Input
Figure 4. 68-Lead PLCC Package
Figure 5. 68-Lead PLCC-Pin Assignments
1 NC Note Connected
12 De-Mux De-multiplex Pin Input
17 Vcc Power Supply Input
18 GND Ground Input
19 Vcc Power Supply Input
20 XTAL2 Crystal Oscillator In/Output
21 XTAL1 Crystal Oscillator In/Output
28 P22 Port 2, pin 2 In/Output
29 NC Not Connected
35 P31 Port 3, pin 1 In/Output
36 NC Not Connected
37 P30 Port 3, pin 0 In/Output
45 R//W READ/WRITE Output
58 Vcc Power Supply Input
66 GND Ground Input
Microcontroller As of Production Version -01 Copyright 2005 ENG 21 0 050519-00 www.Innovasic Innovasic.com Innovasic Semiconductor Page 10 of 80 1.888.824.4184
67 NC Not Connected Input/Output
68 GND Ground Input
Microcontroller As of Production Version -01 Copyright 2005 ENG 21 0 050519-00 www.Innovasic Innovasic.com Innovasic Semiconductor Page 11 of 80 1.888.824.4184 P07 P14 P15 P16 P17 P14 /RESET +5V 11 XTAL1 13 GND 34 XTAL2 12 P47 P46 P45 14 P44 P37 P36 P35 P34 P32 24 P31 P30 P27 26 P26 10 P25 9 P24 P23 P22 P20 R//W /DS 37 /AS 38 P00 48 P01 P02 P03 45 P04 44 P05 43 P06 P21 22 P10 1 P11 2 P12 3 P33 19 P13 P15 35 P16 P17 32 Timing and Control Port 0 Port 1 Port 4 (1/2) Power Clock Port 2 Port 3 Port 4 (1/2) IA88C00
Figure 6. Pin Functions
Microcontroller As of Production Version -01 Copyright 2005 ENG 21 0 050519-00 www.Innovasic Innovasic.com Innovasic Semiconductor Page 13 of 80 1.888.824.4184 Architecture IA88C00 maintains program model compatibility with the Super8 architecture, including 268 general purpose registers and 57 registers for control and mode functions. The instruction set, is also fully binary compatible supporting all instructions, including multiply and divide instructions and provisions for BCD operations. The peripheral set maintains register/ program model compatibility. Robust serial communications are provided by an on-board UART. Counter/timers are provided for time-sensitive/control loop applications. A watchdog timer is provided for processor sanity. Pin Descriptions /AS Address Strobe (output, active Low ) The rising edge of this output indicates that address, R/W, and DM (when appropriate) are valid. /DS Data Strobe (output, active Low The leading edge of this signal indicates that data is valid during a write cycle. The trailing edge of this signal is used to latch data into the IA88C00 during a read cycle. P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, Port I/O Lines (input/output ) Input/Output Ports configured under program control. Specific functions include: Port 1 serves as the multiplexed address/data port. It serves as the data bus de-multiplexed mode, and Port 0 pins can be used as additional address lines or general purpose I/O. Ports 2 and 3 provide support for interrupts, the UART and the timers. Alternatively, they can be programmed as general purpose I/O. Port 4 is used for general I/O or as the lower address byte in de-mux mode. /RESET ( input, active Low ) Reset input. Reset vector is address 0020H. R/W Read/Write (output ) When high, the current bus operation is a read. When low, the current bus operation is a write.
Microcontroller As of Production Version -01 Copyright 2005 ENG 21 0 050519-00 www.Innovasic Innovasic.com Innovasic Semiconductor Page 14 of 80 1.888.824.4184 XTAL1, XTAL2 (Crystal oscillator input ) Crystal inputs for the internal oscillator. All port pins are configured as inputs (high impedance) during RESET, except for Port 1 and Port 0. Port 1 is configured as a multiplexed address/ data bus. Port 0 pins P00-P04 are configured as address out. And pins P05-P07 are configured as inputs. Registers The IA88C00 supports a 256-byte register address space. Addresses 00H-BFH contain two sets of registers. Set one contains control registers that are only accessible by register direct commands. Set two contains data registers that are only available via register indirect, indexed, stack and DMA commands, Note that address space E0H to FFH in Set one is further divided into two banks. The state of bank select bit in the Flag register determines which bank is accessed. The register space is shown in Figure 7.
192 Bytes
256 Bytes
Figure 7. IA88C00Registers Working registers are those registers found within a moveable 8-register section of the register space.
- High order bit of the 4-bit address selects one of the two register pointers (0 selects RP0; 1 selects RP1).
- Live high order bits in the register pointer select an 8-register (contiguous) slice of the register space.
- Three low order bits of the 4-bit address select one of the eight registers in the slice.
the same eight registers, as long as the address in the register pointer remains unchanged. is specified. This is shown in section b. of Figure 8. Figure 8. Working Register Window to R192 and RP1 points to R200.
Figure 9. IA88C00Registers
208 D0 P0 Port 0 I/O bits
209 D1 P1 Port 1 (I/O only)
210 D2 P2 Port 2
211 D3 P3 Port 3
212 D4 P4 Port 4
213 D5 FLAGS System Flags Register
214 D6 RP0 Register Pointer 0
215 D7 RP1 Register Pointer 1
216 D8 SPH Stack Pointer Low Byte
217 D9 SPL Stack Pointer High Byte
218 DA IPH Instruction Pointer High Byte
219 DB IPL Instruction Pointer Low Byte
220 DC IRQ Interrupt Request
221 DD IMR Interrupt Mask Register
222 DE SYM
223 DF HMR Hall Mode Register
224 E0 Bank 0 COCT CTR 0 Control
225 E1 Bank 0 C1CT CTR 1 Control
226 E2 Bank 0 COCH CTR 0 Capture Register, bits 8- 15
227 E3 Bank 0 COCL CTR 0 Capture Register, bits 0- 7
228 E4 Bank 0 C1CH CTR 1 Capture Register, bits 8- 15
229 E5 Bank 0 C1CL CTR 1 Capture Register, bits 0- 7
230 E6 Bank 0 CTPRS Counter Prescaler
230 E6 Bank 1 WDTSMR Watch-Dog/Stop Mode Register
235 EB Bank 0 UTC UART Transmit Control
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236 EC Bank 0 URC UART Receive Control
237 ED Bank 0 UIE UART Interrupt Enable
238 EE Bank 0 UTI Transmit Interrupt Register
239 EF Bank 0 UIO UART Data
240 F0 Bank 0 POM Port 0 Mode
Bank 1 DCH DMA Count, bits 8-15
241 F1 Bank 0 PM Port Mode Register
Bank 0 DCL DMA Count, bits 0-7
244 F4 Bank 0 H0C Handshake Channel 0 Control
245 F5 Bank 0 H1C Handshake Channel 1 Control
246 F6 Bank 0 P4D Port 4 Direction
247 F7 Bank 0 P4OD Port 4 Open Drain
248 F8 Bank 0 P2AM Port 2/3 A Mode
Bank 1 UBGH UART Baud Rate Generator, bits 8-15
249 F9 Bank 0 P2BM Port 2/3 B Mode
Bank 1 UBGL UART Baud Rate Generator, bits 0-7
250 FA Bank 0 P2CM Port 2/3 C Mode
251 FB Bank 0 P2DM Port 2/3 D Mode
252 FC Bank 0 P2AIP Port 2/3 A Interrupt Pending
253 FD Bank 0 P2BIP Port 2/3 B Interrupt Pending
254 FE Bank 0 EMT External Memory Timing
Bank 1 WUMCH Wake-up Match Register
255 FF Bank 0 IPR Interrupt Priority Register
Bank 0 WUMSK Wake-up Mask Register
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Figure 10. R213 (D5) Flags System Flags Register contained in the flag register are the Bank Address bit and the Fast Interrupt Status bit.
- For operations that test bits in a register, the 0 bit is set to 1 if the result is 0. For rotate and shift
operations, this bit is set to 1 if the result is 0. the MSB of the result. A 0 indicates a positive number and a 1 indicates a negative number. than 127 or less than -128. It is also cleared to 0 during logical operations. accessible to programmers and cannot be used as a test condition. Decimal Adjust flag are not usually accessed by users. to be executed when the IRET instruction is fetched. addresses 224 and 255. It is cleared by the SB0 instruction and set by the SB1 instruction.
a PUSH and incremented after a POP. on the stack for recovery by IRET when the interrupt is finished. occurs as the result of incrementing or decrementing the stack address during normal stack operations. Figure 14. R217 (D9) SPL Stack Pointer register (R254B0) selects between the two. a PUSH and incrementd after a POP. on the stack for recovery by IRET when the interrupt is finished. occurs as the result of incrementing or decrementing the stack address during normal stack operations.
Microcontroller As of Production Version -01 Copyright 2005 ENG 21 0 050519-00 www.Innovasic Innovasic.com Innovasic Semiconductor Page 23 of 80 1.888.824.4184 A user-defined stack can be implemented in both the register file and program or data memory. These can be made to increment or decrement on a push by the choice of opcodes. For example, to implement a stack that goes from Low addresses to High addresses in the register file, use PUSHUI and POPUD. For a stack that goes from High address to Low addresses in data memory, use LDEI for POP and LDEPD for PUSH.
Figure 20. Counter 0 Control Register (C0CT), R224 Bank 0 periods. A hardware reset forces this bit to 0. implies a maximum counter frequency of 5 MHz. bit resets it, while writing a 0 has no effect. request when it counts to 0. A hardware reset forces this bit to 0. register. This bit is automatically cleared following the capture. automatically cleared following the load. the Mode register. 1 indicates up; 0 indicates down. 0000, while the one for up counting is FFFF. When this bit is cleared to 0, no reloading occurs.
Figure 21. Counter 0 Mode, R224 periods. A hardware reset forces this bit to 0. implies a maximum counter frequency of 5 MHz. bit resets it, while writing a 0 has no effect. request when it counts to 0. A hardware reset forces this bit to 0. register. This bit is automatically cleared following the capture. automatically cleared following the load. the Mode register. 1 indicates up; 0 indicates down. 0000, while the one for up counting is FFFF. When this bit is cleared to 0, no reloading occurs.
Figure 22. Counter 0 Mode, R225 periods. A hardware reset forces this bit to 0. implies a maximum counter frequency of 5 MHz. bit resets it, while writing a 0 has no effect. request when it counts to 0. A hardware reset forces this bit to 0. register. This bit is automatically cleared following the capture. automatically cleared following the load. the Mode register. 1 indicates up; 0 indicates down. 0000, while the one for up counting is FFFF. When this bit is cleared to 0, no reloading occurs.
Figure 26. Counter 1 Capture Register (Low Byte) (C1CL), R229 Bank 0 register and the counter is alternately loaded from each.
000 XTAL/2
101 XTAL/64
110 XTAL/128
111 XTAL/256
Only the prescaler of CT1 is activated when the counters are cascaded.
Microcontroller As of Production Version -01 Copyright 2005 ENG 21 0 050519-00 www.Innovasic Innovasic.com Innovasic Semiconductor Page 31 of 80 1.888.824.4184 Figure 28b. Watch Dog Timer and Stop Mode Recovery Register (WDT/SMR) R230 Bank0 Bit 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 WDT time-out WDT Enable WDT in Stop WDT Source SMR On SMR Source Initial Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W This register controls the Watchdog Timer time-out and Stop recovery mode. D1, D0 Stop Mode Recovery source select. Bit D0 and D1 determine the Stop Mode Recovery source. D1 D0 0 0 Recovery from RESET only 0 1 Recovery from P22 and RESET 1 0 Recovery from P32 and RESET 1 1 Recovery from any input for Port 4 and RESET A hardware reset forces D0 and D1 to zero. D2 Stop Recovery Edge A 1 in this position indicates that a rising edge on any one of the recovery sources wakes the IA88C00 from Stop mode. A 0 indicates falling edge recovery. The reset value is 0. D3 XTAL1/RC Select for WDT When a zero is written to D3, the clock of the WDT is driven by the on-board RC oscillator. If D3 is set to 1, the WDT is driven by XTAL1. D3 has a zero reset value. D4 WDT Enable During STOP or HALT When this bit is set, WDT is enabled during STOP or HALT. In this case, recovery from STOP or HALT should be performed before the selected time-out. A 0 in this bit location disables the WDT while the IA88C00 is stopped or halted. A hardware reset forces this bit to a zero.
until a hardware reset occurs. Two sets of four different time-out values can be selected, depending on the logical state of these bits. stabilizes, generating a good oscillator output level. Figure 29. UART Transmit Control (UTC), R235 Bank 0 This register cont ains the status and command bits needed to control the transmit sections of the UART. memory or the register file to the UART transmit section. A hardware reset forces this bit to 0. is cleared to 0 when a data byte is written in the transmit buffer. A hardware reset forces this bit to 1. only after the desired transmission of data in the buffer is completed. A hardware reset forces this bit to 0.
and the receiver. The transmitter adds a bit beyond those specified by the bits/character and the parity. UMA register. The resulting action depends on the configuration of the Wake-up feature. continues to send the contents of the Transmit Data Register. A hardware reset forces this bit to 0. output. If this bit is set to 1, the serial data coming out of the transmit section is reflected on the P31 pin. Figure 30. UART Receive Control (URC), R236 Bank 0 write to this possition has not effect. A hardware reset forces this bit to 0. hardware reset clears this bit to 0. that once an error occurs, it remains set until it is cleared to 0 by writing a 1 to this bit position. error. Once set, this bit remains set until cleared to 0 by writing a 1 to this bit position.
cleared to 0 by writing a 1 to this bit position. sequence in the receive data stream. It stays set to 1 until cleared to 0 by writing a 1 to this bit position. the Receive Data Register (UIOR) and Break Detect is set again, along with another interrupt request. Figure 31. UART Interrupt Enable (UIE), R237 Bank 0 DMA counter is also set. If it is not set, a Receive Character Available status causes no interrupt. the register file or the external memory. Transmit Buffer Empty signal causes no interrupt. status in the UTC register will cause an interrupt request.
Microcontroller As of Production Version -01 Copyright 2005 ENG 21 0 050519-00 www.Innovasic Innovasic.com Innovasic Semiconductor Page 36 of 80 1.888.824.4184 Writing to this register automatically writes the data in the Transmit Data register (UIOT). A read from this register gets the data from the UART Receive Data register (UIOR).
Microcontroller As of Production Version -01 Copyright 2005 ENG 21 0 050519-00 www.Innovasic Innovasic.com Innovasic Semiconductor Page 39 of 80 1.888.824.4184 The Port 4 Direction register defines the I/O direction of Port 4 on a bit basis. If a bit of this register is a 1, the corresponding bit of Port 4 is configured as and input line. If the bit is a 0, the corresponding bit of Port 4 is configured as and output line. D0-D7 - P40-P47 Mode, 0 = Output, 1 = Input.
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This section provides a summary of the IA88C00 instructions. Assignment of a value is indicated by the symbol “←”. The notation “addr (n) ” is used to refer to bit (n) of a given operand location. refers to bit 7 of the destination operand. Figure 49. Instruction Summary
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 46 of 80 1.888.824.4184 Flags Affected Instruction and Operation Address Mode dst scr Opcode Byte (Hex) C Z S V D H BITS dst dst←0 dst←1 Flags Affected Instruction and Operation Address Mode dst scr Opcode Byte (Hex) C Z S V D H BOR dst, src dst←0 OR src r0 rB 07 - * 0 U - - BTJRF dst←0 if src=0, PC=PC+dst BTJRT IF SRC=0, PC=PC+dst BXOR dst, src dst←dst XOR src r0 Rb 27 - * 0 U - - CALL dst SP←SP - 2 @SP←PC, PC←dst DA IRR IA - - - - - - CCF C←NOT C EF * - - - - - CLR dst dst←0 R IR - - - - - - COM dst dst←NOT dst R IR - * * 0 - - CP dst, src Dst - src CPIJE if dst - src=0, then PC←PC+RA Ir←Ir + 1 CPIJNE if dst - src=0, then PC←PC+RA Ir←Ir + 1 DA dst dst←DA dst R IR * * * U - - DEC dst dst←dst - 1 R IR - * * * - -
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 47 of 80 1.888.824.4184 DECW dst dst←dst - 1 RR IR - * * * - - DI SMR(0)←0 8F - - - - - - DIV dst, src dst÷src RR R 94 * * * * - - dst (Upper)← RR IR 95 Quotient dst (Lower)← RR IM 96 Remainder Flags Affected Instruction and Operation Address Mode dst scr Opcode Byte (Hex) C Z S V D H DJNZ r, dst RA r rA - - - - - - r←r - 1 (r=0 IoF) If r = 0 PC←PC + dst El SMR(0) 9F - - - - - - ENTER SP←SP - 2 @ SP←IP IP←PC PC←@ IP IP←IP + 2 1F - - - - - - EXIT IP←@SP SP←SP + 2 PC←@ IP IP←IP + 2 2F - - - - - - INC dst r rE - * * * - - dst←dst + 1 r=0-F R 20 IR 21 INCW dst RR A0 - * * * - - dst←dst + 1 IR A1 IRET (Fast) BF Restored to PC↔IP FLAG←FLAG FIS←0 before interrupt
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 48 of 80 1.888.824.4184 IRET (Normal) BF Restored to FLAGS←@SP; before interrupt SP←SP + 1; PC←@ SP SP←SP + 2; SMR(0) ←1 JP cc, dst DA ccD - - - - - - if cc is true C = 0 to F PC←dst IRR 30 JR cc, dst RA ccB - - - - - - if cc is true, cc = 0 to F PC←PC + d LD dst, src r IM rC - - - - - - dst←src r R r8 R r9 r = 0 to F Flags Affected Instruction and Operation Address Mode dst scr Opcode Byte (Hex) C Z S V D H r IR C7 IR r D7 R R E4 R IR E5 R IM E6 IR IM D6 IR R F6 r x 87 - x r 97 LDB dst, src r0 Rb 47 - - - - - dst←src Rb r0 47 - LDC/LDE r lrr C3 - - - - - - dst←src lrr r D3 r xs E7 xs r F7 r x1 A7 x1 r B7 r DA A7 DA R B7 LDCD/LDED dst, src r lrr E2 - - - - - - dst←src rr←rr-1 LDEI/LDCI dst, src r lrr E3 - - - - - - dst←src rr←rr+1 LDCPD/LDCI dst, src r lrr E3 - - - - - -
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 49 of 80 1.888.824.4184 dst←src rr←rr+1 LDCPI/LDEPI dst, src r lrr E3 - - - - - - dst←src rr←rr+1 LDW dst, src RR RR C4 - - - - - - RR IR C5 RR IMM C6 MULT dst, src RR R 84 * 0 * * - - RR IR 85 RR IM 86 NEXT 0F - - - - - - PC←@ IP IP←IP + 2 NOP FF - - - - - - OR dst, src † 4[ ] - * * 0 - - dst←dst OR src POP dst R 50 - - - - - - dst←@SP; IR 51 SP←SP + 1 POPUD dst, src R IR 92 - - - - - - dst←src IR←IR - 1 POPUI dst, src R IR 93 - - - - - - dst←src IR←IR + 1 - Flags Affected Instruction and Operation Address Mode dst scr Opcode Byte (Hex) C Z S V D H PUSH scr R 70 - - - - - - SP←SP - 1; @SP←src IR 71 PUSHUD dst, src IR R 82 - - - - - - IR←IR - 1 dst←src PUSHUI dst, src IR R 83 - - - - - - IR←IR + 1 dst←src RCF CF 0 - - - - - C←0 RET PC←@SP;SP←SP+2 AF - - - - - - RL dst R 90 * * * * - - C←dst(7) IR 91 dst(0)←dst(7)
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 50 of 80 1.888.824.4184 dst(N+1)←dst(N) N=0 to 6 RLC dst R 10 * * * * - - dst(0)←C IR 11 C←dst(7) dst(N)←dst(N+1) N=0 to 6 RR dst R C0 * * * * - - C←dst(0) IR C1 dst(7)←C dst(N)←dst(N+1) N=0 to 6 SB0 4F - - - - - - BANK←0 SB1 5F BANK←1 SBC dst, src † 3[ ] * * * * 1 * dst←dst - src - C SCF DF 1 - - - - - C←1 SRA dst R D0 * * * 0 - - dst(7)←dst(7) C←dst(0) dst(N)←dst(N+1) N=0 to 6 SRP src IM 31 - - - - - - RP0←IM RP1←IM+8 RP0←IM RP1←IM STOP 6F - - - - - - SUB dst, src † 2[ ] * * * * 1 * dst←dst - src SWAP dst R F0 - * * U - - Dst(0-3)↔dst(4-7) IR F1 TCM dst, src † 6[ ] - * * 0 - - (NOT dst) AND src TM dst, src † 7[ ] - * * 0 - - dst AMD src TSW dst, src R R 7F U * * 0 U U WFI 3F - - - - - - XOR dst, src † B[ ] - * * 0 - -
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 51 of 80 1.888.824.4184 dst←dst XOR src † These instructions have an identical set of addressing modes, which are encoded for brevity. The first opcode nibble is found in the instruction set table above. The second nibble is expressed symbolically by a ‘[ ]’ in this table. Its value is found in the following table to the left of the applicable addressing mode pair. For example, the opcode of an ADC instruction using the addressing modes r (destination) and ir (source) is 13. Address dst Mode src Lower Opcode Nibble r r [2] r Ir [3] R R [4] R IR [5] R IM [6] Notes: 0 = Cleared to Zero 1 = Set to One – = Unaffected * = Set or reset, depending on result of operation. U = Undefined
Figure 50. Opcode Map
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 54 of 80 1.888.824.4184 INCW dst Increment word MULT dst, src Multiply SBC dst, src Subtract with carry SUB dst, src Subtract
Figure 58. Interrupt Levels and Vectors
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 58 of 80 1.888.824.4184 Interrupt Programming Model The IA88C00 maintains program compatibility with the Super8. Enabling or disabling of interrupts are controlled via the following registers: Interrupt enable/disable . See the System Mode register (R222). Level enable. See the interrupt Mask register (R221). Level priority. See the Interrupt Priority register (R255, Bank 0). Source enable/disable. Interrupt sources are enabled or disabled in the individual source’s Mode and Control register. Functional Overview For an interrupt to be serviced, it’s source must be enabled. The corresponding interrupt and level must likewise be enabled. Each interrupt input is conditioned with edge-triggered devices to convert all interrupt inputs to “levels”. The eliminates the requirement for external hardware to maintain the interrupt input prior to servicing. When an interrupt source is received the processor is “vectored” to the vector address associated with the interrupt. In the fact of multiple interrupts, the enabled interrupt whose level has the highest priority is serviced first. For interrupts within the same level, the priority of the individual interrupt takes precedence. Upon servicing the interrupt, the processor clears the Interrupt Enable bit in the System Mode register to prevent a high priority interrupt from disrupting the service routine. The program counter and status flags are pushed onto the stack and the program counter is loaded with the appropriate interrupt vector and the interrupt service routine (ISR) begins to the execute. Upon completion, the ISR executes an RET instruction. The flags and program counter are popped off the stack and the Interrupt Enable bit in the System Mode register is set. The IA88C00 supports a special mode of “fast” interrupt processing. Utilization of this mode requires program intervention. The vector address of the ISR must be loaded into the instruction pointer and the Fast Interrupt enable bit in the System Mode Register must be set. Upon receipt of the interrupt source, the ISR vector is loaded into the program counter while the old value of the program counter is saved in the Instruction Pointer. Status flags are saved in the FLAGs register and the Fast interrupt Status Bit in FLAGS is set. Upon completion of the ISR, the process is reversed. Stack Operation The IA88C00 maintains program model compatibility on all Stack operations. The stack may be maintained in either the register file or in data memory space. For programming model details see registers R216/R217 (the stack pointer) and register R254 (Memory Timing register)
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 59 of 80 1.888.824.4184 The IA88C00 also supports user-defined stacks. These stacks are accessed via the PUSHUI, POPUD, LDEI and LDEPD instructions. Counter/Timers The IA88C00 provides two identical 16 bit timer/counters with an 8-bit prescaler. The counters are driven from a divide-by-4 clock derived from the oscillator. Each count provides robust functionality including:
- Up or down count
- Single or continuous count
- Output pulse train with variable duty cycle
- Input capture
- External gating/triggering For longer events, the counters may be cascaded to form a 32-bit counter. For program model details see registers R224 through R230. DMA The IA88C00 supports high speed data transfer support for the UART and handshake channel 0 via Direct Memory Access (DMA). Data can be transferred between these peripherals and contiguous locations in either the register file or external data memory. For details on the programming model see registers R235 (UART transmit control) R236 (UART receive control), R244 (Handshake Channel 0 Control) and R240/241, Bank 1 (DMA Count). WDT The IA88C00 provides a “Watchdog” (WDT) timer to provide sanity checks on the processor. Should program execution hang, the WDT timeout will expire and the RESET pin will be held active for 5 ms. The WDT is prevented from timing out by periodically writing a “1” to bit D5 in the WDT/SMR register. The WDT clock is derived from either an internal ring oscillator or from the crystal oscillator input. It should be noted that the frequency of the internal oscillator and associated WDT time-out can vary widely (as much as 3 times) with voltage and temperature. For details on the WDT programming model see register R230 (WDT/SMR register). Stop Mode When a STOP instruction is executed, the process enter Stop Mode. During Stop mode, the system clock and external oscillator are disabled. Stop Mode is exited via a hard reset, or by applying an edge to a pre- defined bit of either Port 2, 3, or 4. For details on the Stop Mode programming model see register R230 (WDT/SMR register).
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 60 of 80 1.888.824.4184 Halt Mode When the IA88C00 execute the Wait for Interrupt (WFI) instruction and bit 3 of R223 (Halt Mode register) is cleared, the processor enters HALT mode. The internal CPU clock is disabled, however, the oscillator remains active. Use of the UART, timers and DMA remains under user control. The Halt mode is exited via an interrupt or DMA request. The programming model for Halt Mode is detailed in R223 (Halt Mode register)
configured as open-drain outputs. The ports can be configured as shown in Figure 59. Figure 59. Port Configuration
0 High address and/or 0
1 Multiplexed Low address/data or data only
4 Low address or general I/O
Port 0 can be assigned on a bit-by-bit basis as either general I/O or as address bits for external memory. register R241. Push-pull or open-drain selection is controlled by mode control register R241. Port 0 can be placed under handshake control handshake channel 1. Any bits configured as I/O can be accessed via R208. bits are configured as addresses eight through twelve.
as general purpose I/O lines and/or external interrupt inputs. Figure 60. Pin Assignments for Port 2 and 3
0 UART receive clock 0 UART receive clock
1 UART transmit 1 UART transmit
2 Reserved 2 Reserved
3 Reserved 3 Reserved
4 Handshake 0 input 4 Handshake 1 input/WAIT
5 Handshake 0 output 5 Handshake 1 output/DM
6 Counter 0 input 6 Counter 1 input
7 Counter 0 I/O 7 Counter 1 I/O
control handshake channel 0. Port 4 register address is R212. per character and contains options for even- or odd-bit parity and a wake-up feature. R248/249 bank 1 (UART Baud Rate Generator), R250/251 bank 1 (UART Mode A/B Registers).
Figure 61. Port 2 and 3 Pins stop bits. It can also add a wake-up bit if that option is selected. The extra bits in R239 are ignored if the UART is programmed to a 5-, 6-, or 7-bit character. of the transmitter clock rate. All data is sent out on the falling edge of the clock input. byte is placed in the Receive Data register. sampled on the rising edge of the clock. and manipulate the data character in UIO.
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 64 of 80 1.888.824.4184 Once the complete character is assembled, the UART checks it and performs the following actions: 1. Sets the Control Character status bit, if it is an ASCII control character. 2. Checks the wake-up settings and completes any indicated action. 3. Checks to see if the calculated parity matches the programmed parity bit, if parity is enabled. If they do not match, it sets the parity Error bit in URC (R236, Bank 0), which remains set until reset by software. 4. Resets the Framing Error bit (URC, bit 4), if the character is assembled without any stop bits. This bit remains set until cleared by software. Overrun errors occur when characters are received faster than they are read. That is, when the UART has assembled a complete character before the CPU has read current character, the UART sets the Overrun Error bit (URC, bit 3), and the character currently in the receive buffer is lost. The overrun bit remains set until cleared by software. Address Space The IA88C00 can access 64 Kbytes of program memory and 64 Kbytes of data memory. These spaces can be either combined or separate. If separate, they are controlled by the DM line (Port P35), which selects data memory when Low and program memory when High. CPU Program Memory Program memory occupies address 0 to 64K. External program memory is accessed by configuring Ports 0 and/or 1 and/or 4 as the memory interface. The address/data lines are controlled by AS, DS and R/W. The first 32 program memory bytes are reserved for interrupt vectors. The lowest address available for user programs is 32 (decimal). This value is automatically loaded into the program counter after a hardware reset. Port 0 can be configured to provide from 0 to 8 additional address lines. Port 1 is used as an 8-bit multiplexed address/data port or as a data port when in de-mux mode. CPU Data Memory If separated from program memory by the DM optional output, the external CPU data memory space can be mapped anywhere from 0 to 64K (full 16-bit address space). Data memory uses the same address/data bit (Port 1) and additional address (chosen from Port 0) as program memory. The DM pin (P35) is mainly what distinguishes data memory from program memory. It is also distinguished by the fact that data memory can begin at address 0000H. Figure 62 shows the system memory space.
Figure 62. Program and Data Memory Address Space
conditions for an extended period may affect device reliability. VSS. Positive current flows into the referenced pin (Standard Test Load). Figure 63. Standard Test Load
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 67 of 80 1.888.824.4184 DC Characteristics Symbol Parameter Min Max Unit Condition VCH Clock Input High Voltage 3.5 V CC V Driven by External Clock Generator VCL Clock Input Low Voltage -0.3 1.5 V Driven by Exter nal Clock Generator VIH Input High Voltage 2.2 V CC V VIL Input Low Voltage -0.3 0.8 V VRH Reset Input High Voltage 3.8 V CC V VRL Reset Input Low Voltage -0.3 0.8 V VOH Output High Voltage 3.5 V I OH = -400 µA VOL Output Low Voltage 0.4 V I OL = +400 mA VIL Input Leakage -10 10 µA IOL Output Leakage -10 10 µA IIR Reset Input Current -50 µA ICC V CC Supply Current 90 mA [1] ICC1 Standby Current 5 mA @ 20 MHz [2] 10 mA @ 30 MHz [2] I CC2 Standby Current 20 µA [3] NOTES Following are estimated values: 1. In this case all outputs and I/O pins are floating. 2. Estimated Values, not tested. HALT mode is invoked with UART CT0 and CT1 deactivated with all input pins tied to V CC or V SS . 3. Estimated Values, not tested. STOP mode is invoked with all input pins tied to V CC or V SS .
Figure 64. External I/O or Memory Read and Write Timing
1 TdA(AS) Address valid to /AS Rise Delay
2 ThAS(A) /AS Rise to Address Valid
3 TdAS(DI) /AS Rise to Data in Required Valid Delay
4 TwAS /AS Low Width
5 TdAZ (DSR) Address Float to /DS (Read)
6 TwDSR /DS (Read) Low Width
7 TwDSW /DS (Write) Low Width
8 TdDSR (DI) /DS (Read) to Data
9 ThDSR (DI) /DS Rise (Read) to Data in Hold Time
10 TdDS (A) /DS Rise to Address Active Delay
11 TdDA (AS) /DS Rise to /AS Delay
12 TdR/W (AS) R/W to AS Rise Delay
13 TdDS (R/W) DS Rise to R/W Valid Delay
14 TdDO (DSW) Data Out to /DS (Write) Delay
15 ThDSW (DO) /DS Rise (Write) to Data Out Hold Tim e
16 TdA (DI) Address to Data In Required Valid Delay
17 TdAS (DSR) /AS Rise to D/S (Read) Delay
18 TsDI (DSR) Data in Setup Time to DS Rise (Read)
19 TdDM (AS) /DM to /AS Rise Delay
20 TdDS (DM) /DS Rise to /DM Valid Delay
21 ThDS (A) /DS Rise to Address Valid Hold Time
22 TwW Wait Width (One Wait) Window
23 TdAS (W) /AS Rise to Wait Delay
Figure 65. 20 MHz Timing
1 TdA (AS) 25 70
2 ThAS (A) 25 70
3 TdAS (DI) 180 375
4 TwAS 35 85
5 TdAZ (DSR) 0 0
6 TwDSR 140 285
7 TwDSW 85 185
8 TdDSR (DI) 115 260
9 ThDSR (DI) 0 0
10 TdDS (A) 25 25
11 TdDS (AS) 20 65
12 TdR/W (AS) 25 70
13 TdDS (R/W) 20 65
14 TdDO (DSW) 30 70
15 ThDSW (DO) 20 65
16 TdA (DI) 205 445
17 TdAS (DSR) 25 70
18 TsDI (DSR) 25 65
19 TdDM (AS) 20 65
20 TdDS (DM) 20 65
21 ThDS (A) 20 65
Figure 66. 12 MHz Timing
1 TdA (AS) 55 135
2 ThAS (A) 55 135
3 TdAS (DI) 305 630
4 TwAS 70 150
6 TwDSR 240 480
7 TwDSW 150 320
8 TdDSR (DI) 215 440
10 TdDS (A) 55 130
11 TdDS (AS) 45 125
12 TdR/W (AS) 55 135
13 TdDS (R/W) 45 125
14 TdDO (DSW) 65 150
15 ThDSW (DO) 45 125
16 TdA (DI) 365 770
17 TdAS (DSR) 55 135
18 TsDI (DSR) 25 25
19 TdDM (AS) 50 130
20 TdDS (DM) 45 125
21 ThDS (A) 45 125
Figure 67. 25 MHz Timing
1 TdA (AS) 15 50
2 ThAS (A) 15 50
3 TdAS (DI) 140 280
4 TwAS 26 65
6 TwDSR 110 220
7 TwDSW 65 142
8 TdDSR (DI) 85 195
10 TdDS (A) 20 55
11 TdDS (AS) 15 50
12 TdR/W (AS) 15 50
13 TdDS (R/W) 15 50
14 TdDO (DSW) 20 50
15 ThDSW (DO) 15 50
16 TdA (DI) 155 330
17 TdAS (DSR) 15 50
19 TdDM (AS) 10 45
20 TdDS (DM) 15 50
21 ThDS (A) 15 50
Figure 68. Fully Interlocked Mode (Input Handshake)
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Figure 69. Strobed Mode (Input Handshake)
1 TsDI(DAV) Data In to Setup Time 0
2 TdDAVlf(RDY) /DAV Fall Input to RDY Fall Delay 2 00 1
3 ThDI(RDY) Data In Hold Time from RDY Fall 0
4 TwDAV /DAV In Width 45
5 ThD(DAV) Data In Hold Time from /DAV Fall 130
6 TdDAV(RDY) /DAV Rise Input to RDY Rise Delay 100 2
7 TdRDYf(DAV) RDY Rise Output to /DAV Rise Delay
- This time assumes user program reads data before /DAV Input goes High. RDY will not go high before data is read.
- Times are given in nanoseconds.
† Times are preliminary and subject to change. Figure 70. Fully Interlocked Mode (Output Handshake)
Figure 71. Strobed Mode (Output Handshake)
1 TdDO(DAV) Data Out to /DAV Fall Delay 90 1, 2
2 TdRDYr(DAV) RDY Rise Input to /DAV Fall Delay 11 0 1
3 ThDAV(RDY) /DAV Fall Output to RDY Fall Delay 0
4 TdRDY(DAV) /RDY Fall Input to /DAV Rise Delay 0 1 10 1
5 TdDAVOr(RDY) /DAV Rise Output to RDY Rise Delay 0
6 TwDAVO /DAV Output Width 150 2
- Time given is for zero value in Deskew Counter. For non-zero value of n where n = 1,2, …15 add 2 x n x TpC to the given
† Times given are in nanoseconds.
- Times are preliminary and subject to change.
Figure 72. EPROM READ Timing
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 75 of 80 1.888.824.4184 EPROM Read Cycle No. Symbol Parameter Min Max Notes †*
1 TdA(DR) Address Valid to Read Data Required Valid 170 1
- WAIT states add 167 ns to these times. † All times are in nanoseconds and are for 12 MHz input frequency. * Timings are preliminary and subject to change. Wait Timing SCLK /AS /DS /WAIT T1 T2 TWAIT T3 a b c d Tc Tc e F G
Figure 73. Wait Timing
Description
a Skew of T1 SCLK Rise to /AS Fall 10.0 Max b Skew of T1 SCLK Rise to /AS Rise 10.0 Max c Skew of T2 SCLK Rise to Read /DS Fall 20.0 Max d Skew T2 SCLK Fall to Write /DS Fall 20.0 Max e Skew T3 SCLK Fall to /DS Rise 20.0 Max F /WAIT Fall Delay After T2 SCLK Fall to Generate at Least 1 WAIT State 20.0 Max G /WAIT Fall Delay after T2 SCLK Fall to Prevent an Additional WAIT State 15.0 Max NOTES All figures are in nanoseconds.
Microcontroller As of Production Version -01 Copyright 2005 ENG21 1 0 30617-04 www.Innovasic Innovasic.com Innovasic Semiconductor Page 76 of 80 1.888.824.4184 De-Multiplexed Bus Timing Demixed A/D Bus T1 T2 T3 CLK /AS /DS R/W /DM A8 - A15 D0 - D7 A0 - A7 NOTES /AS, /DS, R/W, /DM Timing remains unchanged in demuxed A/D bus mode.
Figure 79. 68-Lead Package Side View
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Ordering Information
Semiconductor Part Number Package Type Temperature Grades IA88C00-PDW48C (standard packaging) IA88C00-PDW48I (standard packaging) 48-Pin Plastic Dual In- line Package (DIP) Commercial Industrial IA88C00-PDW48C-R (RoHS packaging) IA88C00-PDW48I-R (RoHS packaging) Commercial Industrial IA88C00-PLC68C (standard packaging) IA88C00-PLC68I (standard packaging) 68-Pin Plastic Leaded Chip Carrier (PLCC) Commercial Industrial IA88C00-PLC68C-R (RoHS packaging) IA88C00-PLC68I-R (RoHS packaging) Commercial Industrial