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Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 AIIGX53001-4.4 Subscribe and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 1. Device Datasheet for Arria II Devices This chapter describes the electrical and switching characteristics of the Arria® II device family. The Arria II device family includes the Arria II GX and GZ devices. Electrical characteristics include operating conditions and power consumption. Switching characteristics include transceiver specifications, core, and periphery performance. This chapter also describes I/O timing, including programmable I/O element (IOE) delay and programmable output buffer delay. f For information regarding the densities and packages of devices in the Arria II device family, refer to Overview for the Arria II Device Family chapter. This chapter contains the following sections: ■ “Electrical Characteristics” on page 1–1 ■ “Transceiver Performance Specifications” on page 1–21 ■ “Glossary” on page 1–74

Electrical Characteristics

The following sections describe the electrical characteristics. Operating Conditions Arria II devices are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Arria II devices, you must consider the operating requirements described in this chapter. Arria II devices are offered in both commercial and industrial grades. Arria II GX devices are offered in –4 (fastest), –5, and –6 (slowest) commercial speed grades and –3 and –5 industrial speed grades. Arria II GZ devices are offered in –3 and –4 speed grades for both commercial and industrial grades.

1 In this chapter, a prefix associated with the operating temperature range is attached to

the speed grades; commercial with the "C" prefix and industrial with the “I” prefix. Commercial devices are indicated as C4, C5, and C6 speed grade, and the industrial devices are indicated as I3 and I5. Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for Arria II devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied under these conditions. Table 1–1 lists the absolute maximum ratings for Arria II GX devices. Table 1–2 lists the absolute maximum ratings for Arria II GZ devices. December 2013 AIIGX53001-4.4

1–2 Chapter 1: Device Datasheet for Arria II Devices Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation c Conditions beyond those listed in Table 1–1 and Table 1–2 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse effects on the device. Table 1–1 lists the absolute maximum ratings for Arria II GX devices. Table 1–2 lists the absolute maximum ratings for Arria II GZ devices. Table 1–1. Absolute Maximum Ratings for Arria II GX Devices Symbol Description Minimum Maximum Unit VCC Supplies power to the core, periphery, I/O registers, PCI Express® (PIPE) (PCIe) HIP block, and transceiver PCS –0.5 1.35 V VCCCB Supplies power for the configuration RAM bits –0.5 1.8 V VCCBAT Battery back-up power supply for design security volatile key register –0.5 3.75 V VCCPD Supplies power to the I/O pre-drivers, differential input buffers, and MSEL circuitry –0.5 3.75 V VCCIO Supplies power to the I/O banks –0.5 3.9 V VCCD_PLL Supplies power to the digital portions of the PLL –0.5 1.35 V VCCA_PLL Supplies power to the analog portions of the PLL and device-wide power management circuitry –0.5 3.75 V VI DC input voltage –0.5 4.0 V IOUT DC output current, per pin –25 40 mA VCCA Supplies power to the transceiver PMA regulator — 3.75 V VCCL_GXB Supplies power to the transceiver PMA TX, PMA RX, and clocking — 1.21 V VCCH_GXB Supplies power to the transceiver PMA output (TX) buffer — 1.8 V TJ Operating junction temperature –55 125 °C TSTG Storage temperature (no bias) –65 150 °C Table 1–2. Absolute Maximum Ratings for Arria II GZ Devices (Part 1 of 2) Symbol Description Minimum Maximum Unit VCC Supplies power to the core, periphery, I/O registers, PCIe HIP block, and transceiver PCS -0.5 1.35 V VCCCB Power supply to the configuration RAM bits -0.5 1.8 V VCCPGM Supplies power to the configuration pins -0.5 3.75 V VCCAUX Auxiliary supply -0.5 3.75 V VCCBAT Supplies battery back-up power for design security volatile key register -0.5 3.75 V VCCPD Supplies power to the I/O pre-drivers, differential input buffers, and MSEL circuitry -0.5 3.75 V VCCIO Supplies power to the I/O banks -0.5 3.9 V VCC_CLKIN Supplies power to the differential clock input -0.5 3.75 V VCCD_PLL Supplies power to the digital portions of the PLL -0.5 1.35 V VCCA_PLL Supplies power to the analog portions of the PLL and device-wide power management circuitry -0.5 3.75 V VI DC input voltage -0.5 4.0 V IOUT DC output current, per pin -25 40 mA

Chapter 1: Device Datasheet for Arria II Devices 1–3 December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Maximum Allowed Overshoot and Undershoot Voltage During transitions, input signals may overshoot to the voltage shown in Table 1–3 and undershoot to –2.0 V for magnitude of currents less than 100 mA and periods shorter than 20 ns. Table 1–3 lists the Arria II GX and GZ maximum allowed input overshoot voltage and the duration of the overshoot voltage as a percentage over the device lifetime. The maximum allowed overshoot duration is specified as a percentage of high-time over the lifetime of the device. A DC signal is equivalent to 100% duty cycle. For example, a signal that overshoots to 4.3 V can only be at 4.3 V for 5.41% over the lifetime of the device; for a device lifetime of 10 years, this amounts to 5.41/10ths of a year. VCCA_L Supplies transceiver high voltage power (left side) -0.5 3.75 V VCCA_R Supplies transceiver high voltage power (right side) -0.5 3.75 V VCCHIP_L Supplies transceiver HIP digital power (left side) -0.5 1.35 V VCCR_L Supplies receiver power (left side) -0.5 1.35 V VCCR_R Supplies receiver power (right side) -0.5 1.35 V VCCT_L Supplies transmitter power (left side) -0.5 1.35 V VCCT_R Supplies transmitter power (right side) -0.5 1.35 V VCCL_GXBLn (1) Supplies power to the transceiver PMA TX, PMA RX, and clocking (left side) -0.5 1.35 V VCCL_GXBRn (1) Supplies power to the transceiver PMA TX, PMA RX, and clocking (right side) -0.5 1.35 V VCCH_GXBLn (1) Supplies power to the transceiver PMA output (TX) buffer (left side) -0.5 1.8 V VCCH_GXBRn (1) Supplies power to the transceiver PMA output (TX) buffer (right side) -0.5 1.8 V TJ Operating junction temperature -55 125 °C TSTG Storage temperature (no bias) -65 150 °C Note to Table 1–2: Table 1–2. Absolute Maximum Ratings for Arria II GZ Devices (Part 2 of 2) Symbol Description Minimum Maximum Unit

1–4 Chapter 1: Device Datasheet for Arria II Devices Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Maximum Allowed I/O Operating Frequency Table 1–4 lists the maximum allowed I/O operating frequency for Arria II GX I/Os using the specified I/O standards to ensure device reliability. Table 1–3. Maximum Allowed Overshoot During Transitions for Arria II Devices Symbol Description Condition (V) Overshoot Duration as % of High Time Unit VI (AC) AC Input Voltage 4.0 100.000 % 4.05 79.330 % 4.1 46.270 % 4.15 27.030 % 4.2 15.800 % 4.25 9.240 % 4.3 5.410 % 4.35 3.160 % 4.4 1.850 % 4.45 1.080 % 4.5 0.630 % 4.55 0.370 % 4.6 0.220 % Table 1–4. Maximum Allowed I/O Operating Frequency for Arria II GX Devices I/O Standard I/O Frequency (MHz) HSTL-18 and HSTL-15 333 SSTL -15 400 SSTL-18 333 2.5-V LVCMOS 260 3.3-V and 3.0-V LVTTL 250 3.3-V, 3.0-V, 1.8-V, and 1.5-V LVCMOS PCI and PCI-X SSTL-2 1.2-V LVCMOS HSTL-12 200

Chapter 1: Device Datasheet for Arria II Devices 1–5 December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Recommended Operating Conditions This section lists the functional operation limits for AC and DC parameters for Arria II GX and GZ devices. All supplies are required to monotonically reach their full-rail values without plateaus within tRAMP . Table 1–5 lists the recommended operating conditions for Arria II GX devices. Table 1–5. Recommended Operating Conditions for Arria II GX Devices (Note 1) (Part 1 of 2) Symbol Description Condition Minimum Typical Maximum Unit VCC Supplies power to the core, periphery, I/O registers, PCIe HIP block, and transceiver PCS — 0.87 0.90 0.93 V VCCCB Supplies power to the configuration RAM bits — 1.425 1.50 1.575 V VCCBAT (2) Battery back-up power supply for design security volatile key registers — 1.2 — 3.3 V VCCPD (3) Supplies power to the I/O pre-drivers, differential input buffers, and MSEL circuitry — 3.135 3.3 3.465 V — 2.85 3.0 3.15 V — 2.375 2.5 2.625 V V CCIO Supplies power to the I/O banks (4) — 3.135 3.3 3.465 V — 2.85 3.0 3.15 V — 2.375 2.5 2.625 V — 1.71 1.8 1.89 V — 1.425 1.5 1.575 V — 1.14 1.2 1.26 V V CCD_PLL Supplies power to the digital portions of the PLL — 0.87 0.90 0.93 V VCCA_PLL Supplies power to the analog portions of the PLL and device-wide power management circuitry — 2.375 2.5 2.625 V VI DC Input voltage — –0.5 — 3.6 V VO Output voltage — 0 — V CCIO V VCCA Supplies power to the transceiver PMA regulator — 2.375 2.5 2.625 V VCCL_GXB Supplies power to the transceiver PMA TX, PMA RX, and clocking — 1.045 1.1 1.155 V VCCH_GXB Supplies power to the transceiver PMA output (TX) buffer — 1.425 1.5 1.575 V TJ Operating junction temperature Commercial 0 — 85 °C Industrial –40 — 100 °C

1–6 Chapter 1: Device Datasheet for Arria II Devices Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–6 lists the recommended operating conditions for Arria II GZ devices. tRAMP Power Supply Ramp time Normal POR 0.05 — 100 ms Fast POR 0.05 — 4 ms Notes to Table 1–5: (1) For more information about su pply pin connections, refer to the Arria II Device Family Pin Connection Guidelines. (2) Altera recommends a 3.0-V nominal battery voltage when connecting VCCBAT to a battery for volatile key backup. If you do not use the volatile security key, you may connect the VCCBAT to either GND or a 3.0-V power supply. Table 1–5. Recommended Operating Conditions for Arria II GX Devices (Note 1) (Part 2 of 2) Symbol Description Condition Minimum Typical Maximum Unit Table 1–6. Recommended Operating Conditions for Arria II GZ Devices (Note 6) (Part 1 of 2) Symbol Description Condition Minimum Typical Maximum Unit VCC Core voltage and periphery circuitry power supply — 0.87 0.90 0.93 V VCCCB Supplies power for the configuration RAM bits — 1.45 1.50 1.55 V VCCAUX Auxiliary supply — 2.375 2.5 2.625 V VCCPD (2) I/O pre-driver (3.0 V) power supply — 2.85 3.0 3.15 V I/O pre-driver (2.5 V) power supply — 2.375 2.5 2.625 V VCCIO I/O buffers (3.0 V) power supply — 2.85 3.0 3.15 V I/O buffers (2.5 V) power supply — 2.375 2.5 2.625 V I/O buffers (1.8 V) power supply — 1.71 1.8 1.89 V I/O buffers (1.5 V) power supply — 1.425 1.5 1.575 V I/O buffers (1.2 V) power supply — 1.14 1.2 1.26 V V CCPGM Configuration pins (3.0 V) power supply — 2.85 3.0 3.15 V Configuration pins (2.5 V) power supply — 2.375 2.5 2.625 V Configuration pins (1.8 V) power supply — 1.71 1.8 1.89 V VCCA_PLL PLL analog voltage regulator power supply — 2.375 2.5 2.625 V VCCD_PLL PLL digital voltage regulator power supply — 0.87 0.90 0.93 V VCC_CLKIN Differential clock input power supply — 2.375 2.5 2.625 V VCCBAT (1) Battery back-up power supply (For design security volatile key register) — 1 . 2—3 . 3 V VI DC input voltage — –0.5 — 3.6 V VO Output voltage — 0 — V CCIO V VCCA_L Transceiver high voltage power (left side) — VCCA_R Transceiver high voltage power (right side) — VCCHIP_L Transceiver HIP digital power (left side) — 0.87 0.9 0.93 V VCCR_L Receiver power (left side) — 1.05 1.1 1.15 V VCCR_R Receiver power (right side) — 1.05 1.1 1.15 V VCCT_L Transmitter power (left side) — 1.05 1.1 1.15 V VCCT_R Transmitter power (right side) — 1.05 1.1 1.15 V

Chapter 1: Device Datasheet for Arria II Devices 1–7 December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum DC Characteristics This section lists the supply current, I/O pin leakage current, on-chip termination (OCT) accuracy and variation, input pin capacitance, internal weak pull-up and pull-down resistance, hot socketing, and Schmitt trigger input specifications. Supply Current Standby current is the current the device draws after the device is configured with no inputs or outputs toggling and no activity in the device. Because these currents vary largely with the resources used, use the Microsoft Excel-based Early Power Estimator (EPE) to get supply current estimates for your design. f For more information about power estimation tools, refer to the PowerPlay Early Power Estimator User Guide and the PowerPlay Power Analysis chapter. VCCL_GXBLn (3) Transceiver clock power (left side) — 1.05 1.1 1.15 V VCCL_GXBRn (3) Transceiver clock power (right side) — 1.05 1.1 1.15 V VCCH_GXBLn (3) Transmitter output buffer power (left side) — VCCH_GXBRn (3) Transmitter output buffer power (right side) — TJ Operating junction temperature Commercial 0 — 85 °C Industrial –40 — 100 °C tRAMP Power supply ramp time Normal POR (PORSEL=0) 0.05 — 100 ms Fast POR (PORSEL=1) 0.05 — 4 ms Notes to Table 1–6: (1) Altera recommends a 3.0-V nominal battery voltage when connecting VCCBAT to a battery for volatile key backup. If you do not use the volatile security key, you may connect the VCCBAT to either GND or a 3.0-V power supply. (4) V CCA_L/R must be connected to a 3.0-V supply if the clock multiplier unit (CMU) phase-locked loop (PLL), receiver clock data recovery (CDR), or (5) V CCH_GXBL/R must be connected to a 1.4-V supply if the transmitter channel data rate is > 6.5 Gbps. For data rates up to 6.5 Gbps, you can connect VCCH_GXBL/R to either 1.4 V or 1.5 V. (6) Transceiver power supplies do not have power-on-reset (POR) circuitry. After initial power-up, violating the transceiver power supply operating conditions could lead to unpredictable link behavior. Table 1–6. Recommended Operating Conditions for Arria II GZ Devices (Note 6) (Part 2 of 2) Symbol Description Condition Minimum Typical Maximum Unit

1–8 Chapter 1: Device Datasheet for Arria II Devices Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation I/O Pin Leakage Current Table 1–7 lists the Arria II GX I/O pin leakage current specifications. Table 1–8 lists the Arria II GZ I/O pin leakage current specifications. Bus Hold Bus hold retains the last valid logic state after the source driving it either enters the high impedance state or is removed. Each I/O pin has an option to enable bus hold in user mode. Bus hold is always disabled in configuration mode. Table 1–9 lists bus hold specifications for Arria II GX devices. Table 1–7. I/O Pin Leakage Current for Arria II GX Devices Symbol Description Conditions Min Typ Max Unit II Input pin V I = 0 V to VCCIOMAX –10 — 10 µA IOZ Tri-stated I/O pin V O = 0 V to VCCIOMAX –10 — 10 µA Table 1–8. I/O Pin Leakage Current for Arria II GZ Devices Symbol Description Conditions Min Typ Max Unit II Input pin V I = 0 V to VCCIOMAX –20 — 20 µA IOZ Tri-stated I/O pin V O = 0 V to VCCIOMAX –20 — 20 µA Table 1–9. Bus Hold Parameters for Arria II GX Devices (Note 1) Parameter Symbol Cond. VCCIO (V) Min Max Min Max Min Max Min Max Min Max Min Max Bus-hold low, sustaining current ISUSL VIN > VIL (max.) 8—1 2—3 0—5 0— 7 0 — 7 0 — µ A Bus-hold high, sustaining current ISUSH VIN < VIL Bus-hold low, overdrive current IODL 0V<V IN < VCCIO — 125 — 175 — 200 — 300 — 500 — 500 µA Bus-hold high, overdrive current IODH 0V<V IN < VCCIO Bus-hold Note to Table 1–9: (1) The bus-hold trip points are based on calcul ated input voltages from the JEDEC standard.

Chapter 1: Device Datasheet for Arria II Devices 1–9 December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Table 1–10 lists the bus hold specifications for Arria II GZ devices. OCT Specifications Table 1–11 lists the Arria II GX device and differential OCT with and without calibration accuracy. Table 1–10. Bus Hold Parameters for Arria II GZ Devices Parameter Symbol Cond. VCCIO (V) Min Max Min Max Min Max Min Max Min Max Bus-hold Low sustaining current ISUSL VIN > VIL (max.) Bus-hold High sustaining current ISUSH VIN < VIH (min.) Bus-hold Low overdrive current IODL 0V < VIN < VCCIO — 120 — 160 — 200 — 300 — 500 µA Bus-hold High overdrive current IODH 0V < VIN < VCCIO Bus-hold Table 1–11. OCT With and Without Calibration Specification for Arria II GX Device I/Os (Note 1) (Part 1 of 2) Symbol Description Conditions (V) Calibration Accuracy Unit Commercial Industrial 25- RS 3.0, 2.5 25- series OCT without calibration VCCIO = 3.0, 2.5 ± 30 ± 40 % 50- RS 3.0, 2.5 50- series OCT without calibration VCCIO = 3.0, 2.5 ± 30 ± 40 % 25- RS 1.8 25- series OCT without calibration VCCIO = 1.8 ± 40 ± 50 % 50- RS 1.8 50- series OCT without calibration VCCIO = 1.8 ± 40 ± 50 % 25- RS 1.5, 1.2 25- series OCT without calibration VCCIO = 1.5, 1.2 ± 50 ± 50 % 50- RS 1.5, 1.2 50- series OCT without calibration VCCIO = 1.5, 1.2 ± 50 ± 50 % 25- RS 1.2 25- series OCT with calibration V CCIO = 3.0, 2.5,

1–10 Chapter 1: Device Datasheet for Arria II Devices Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–12 lists the OCT termination calibration accuracy specifications for Arria II GZ devices. 50- RS 1.2 50- series OCT with calibration VCCIO = 3.0, 2.5, 100- RD 2.5 100- differential OCT without calibration V CCIO = 2.5 ± 30 ± 30 % Note to Table 1–11: (1) OCT with calibration accuracy is vali d at the time of calibration only. Table 1–11. OCT With and Without Calibration Specification for Arria II GX Device I/Os (Note 1) (Part 2 of 2) Symbol Description Conditions (V) Calibration Accuracy Unit Commercial Industrial Table 1–12. OCT with Calibration Accuracy Specifications for Arria II GZ Devices (Note 1) Symbol Description Conditions (V) Calibration Accuracy Unit C2 C3,I3 C4,I4 25- RS 1.2 (2) 25- series OCT with calibration VCCIO = 3.0, 2.5, 50- RS 1.2 50-internal series OCT with calibration V CCIO = 3.0, 2.5, 50- RT 2.5, 1.8, 1.5, 1.2 50- internal parallel OCT with calibration VCCIO = 2.5, 1.8, 20-, 40-, and 60- RS 1.2 (3) 20-, 40- and 60- RS expanded range for internal series OCT with calibration VCCIO = 3.0, 2.5, 25- RS_left_shift 1.2 25- RS_left_shift internal left shift series OCT with calibration VCCIO = 3.0, 2.5, Notes to Table 1–12: (1) OCT calibration accuracy is valid at the time of calibration only. (2) 25-  RS is not supported for 1.5 V and 1.2 V in Row I/O. (3) 20-  RS is not supported for 1.5 V and 1.2 V in Row I/O.

Chapter 1: Device Datasheet for Arria II Devices 1–11 December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum The calibration accuracy for calibrated series and parallel OCTs are applicable at the moment of calibration. When process, voltage, and temperature (PVT) conditions change after calibration, the tolerance may change. Table 1–13 lists the Arria II GZ OCT without calibration resistance tolerance to PVT changes. OCT calibration is automatically performed at power up for OCT-enabled I/Os. When voltage and temperature conditions change after calibration, the resistance may change. Use Equation 1–1 and Table 1–14 to determine the OCT variation when voltage and temperature vary after power-up calibration for Arria II GX and GZ devices. Table 1–13. OCT Without Calibration Resistance Tolerance Specifications for Arria II GZ Devices Symbol Description Conditions (V) Resistance Tolerance Unit C3,I3 C4,I4 25- RS 3.0 and 2.5 25-internal series OCT without calibration VCCIO = 3.0, 2.5 ± 40 ± 40 % 25- RS 1.8 and 1.5 25- internal series OCT without calibration VCCIO = 1.8, 1.5 ± 40 ± 40 % 25- RS 1.2 25-internal series OCT without calibration VCCIO = 1.2 ± 50 ± 50 % 50- RS 3.0 and 2.5 50- internal series OCT without calibration VCCIO = 3.0, 2.5 ± 40 ± 40 % 50- RS 1.8 and 1.5 50-internal series OCT without calibration VCCIO = 1.8, 1.5 ± 40 ± 40 % 50- RS 1.2 50-internal series OCT without calibration VCCIO = 1.2 ± 50 ± 50 % 100- RD 2.5 100-internal differential OCT VCCIO = 2.5 ± 25 ± 25 % Equation 1–1. OCT Variation (Note 1) Notes to Equation 1–1: (1) R OCT value calculated from Equation 1–1shows the range of OCT resistance with the variation of temperature and VCCIO. ROCT RSCAL 1 dR =

1–12 Chapter 1: Device Datasheet for Arria II Devices Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Use the following with Equation 1–1: ■ RSCAL is the OCT resistance value at power up. ■ T is the variation of temperature with respect to the temperature at power up. ■ V is the variation of voltage with respect to the VCCIO at power up. ■ dR/dT is the percentage change of RSCAL with temperature. ■ dR/dV is the percentage change of RSCAL with voltage. Table 1–14 lists the OCT variation with temperature and voltage after power-up calibration for Arria II GX devices. Table 1–15 lists the OCT variation with temperature and voltage after power-up calibration for Arria II GZ devices. Pin Capacitance Table 1–16 lists the pin capacitance for Arria II GX devices. Table 1–14. OCT Variation after Power-up Calibration for Arria II GX Devices Nominal Voltage VCCIO (V) dR/dT (%/°C) dR/dV (%/mV) 3.0 0.262 0.035 2.5 0.234 0.039 1.8 0.219 0.086 1.5 0.199 0.136 1.2 0.161 0.288 Table 1–15. OCT Variation after Power-Up Calibration for Arria II GZ Devices (Note 1) Nominal Voltage, V CCIO (V) dR/dT (%/°C) dR/dV (%/mV) 3.0 0.189 0.0297 2.5 0.208 0.0344 1.8 0.266 0.0499 1.5 0.273 0.0744 1.2 0.317 0.1241 Note to Table 1–15: (1) Valid for V CCIO range of ±5% and temperature range of 0° to 85°C. Table 1–16. Pin Capacitance for Arria II GX Devices Symbol Description Typical Unit CIO Input capacitance on I/O pins, dual-purpose pins (differential I/O, clock, Rup, Rdn), and dedicated clock input pins 7p F

Chapter 1: Device Datasheet for Arria II Devices 1–13 December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Table 1–17 lists the pin capacitance for Arria II GZ devices. Internal Weak Pull-Up and Weak Pull-Down Resistors Table 1–18 lists the weak pull-up and pull-down resistor values for Arria II GX devices. Table 1–17. Pin Capacitance for Arria II GZ Devices Symbol Description Typical Unit CIOTB Input capacitance on the top and bottom I/O pins 4 pF CIOLR Input capacitance on the left and right I/O pins 4 pF CCLKTB Input capacitance on the top and bottom non-dedicated clock input pins 4 pF CCLKLR Input capacitance on the left and right non-dedicated clock input pins 4 pF COUTFB Input capacitance on the dual-purpose clock output and feedback pins 5 pF CCLK1, CCLK3, CCLK8, and CCLK10 Input capacitance for dedicated clock input pins 2 pF Table 1–18. Internal Weak Pull-up and Weak Pull-Down Resistors for Arria II GX Devices (Note 1) Symbol Description Conditions Min Typ Max Unit RPU Value of I/O pin pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled. V CCIO = 3.3 V ±5% (2) 72 5 4 1 k  VCCIO = 3.0 V ±5% (2) 72 8 4 7 k  VCCIO = 2.5 V ±5% (2) 83 5 6 1 k  VCCIO = 1.8 V ±5% (2) 10 57 108 k  VCCIO = 1.5 V ±5% (2) 13 82 163 k  VCCIO = 1.2 V ±5% (2) 19 143 351 k  RPD Value of TCK pin pull-down resistor VCCIO = 3.3 V ±5% 6 19 29 k  VCCIO = 3.0 V ±5% 6 22 32 k  VCCIO = 2.5 V ±5% 6 25 42 k  VCCIO = 1.8 V ±5% 7 35 70 k  VCCIO = 1.5 V ±5% 8 50 112 k  Notes to Table 1–18: (1) All I/O pins have an option to enable weak pull-up except configuration, test, and JTAG pins. The weak pull-down feature is only available for JTAG TCK. (2) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.

1–14 Chapter 1: Device Datasheet for Arria II Devices Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–19 lists the weak pull-up resistor values for Arria II GZ devices. Hot Socketing Table 1–20 lists the hot-socketing specification for Arria II GX and GZ devices. Schmitt Trigger Input The Arria II GX device supports Schmitt trigger input on the TDI, TMS, TCK, nSTATUS, nCONFIG, nCE, CONF_DONE, and DCLK pins. A Schmitt trigger feature introduces hysteresis to the input signal for improved noise immunity, especially for signals with slow edge rates. Table 1–21 lists the hysteresis specifications across the supported VCCIO range for Schmitt trigger inputs in Arria II GX devices. Table 1–19. Internal Weak Pull-Up Resistor for Arria II GZ Devices (Note 1), (2) Symbol Description Conditions Min Typ Max Unit RPU Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if the programmable pull-up resistor option is enabled. V Notes to Table 1–19: (1) All I/O pins have an option to enable weak pul l-up except configuration, test, and JTAG pins. (2) The internal weak pull-down feature is only available for the JTAG TCK pin. The typical value for this internal weak pull-down resistor is approximately 25 k (3) Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO. Table 1–20. Hot Socketing Specifications for Arria II Devices Symbol Description Maximum IIIOPIN(DC) DC current per I/O pin 300 A IIOPIN(AC) AC current per I/O pin 8 mA (1) IXCVRTX(DC) DC current per transceiver TX pin 100 mA IXCVRRX(DC) DC current per transceiver RX pin 50 mA Note to Table 1–20: (1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |I IOPIN| = C dv/dt, in which “C” is I/O pin capacitance and “dv/dt” is slew rate. Table 1–21. Schmitt Trigger Input Hysteresis Specifications for Arria II GX Devices Symbol Description Condition (V) Minimum Unit VSchmitt Hysteresis for Schmitt trigger input VCCIO = 3.3 220 mV VCCIO = 2.5 180 mV VCCIO = 1.8 110 mV VCCIO = 1.5 70 mV

Chapter 1: Device Datasheet for Arria II Devices 1–15 December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum I/O Standard Specifications Table 1–22 through Table 1–35 list input voltage (VIH and VIL), output voltage (VOH and VOL), and current drive characteristics (IOH and IOL) for various I/O standards supported by the Arria II device family. They also show the Arria II device family I/O standard specifications. VOL and VOH values are valid at the corresponding IOH and IOL, respectively.

1 For an explanation of terms used in Table 1–22 through Table 1–35, refer to “Glossary”

on page 1–74. Table 1–22 lists the single-ended I/O standards for Arria II GX devices. Table 1–23 lists the single-ended I/O standards for Arria II GZ devices. Table 1–22. Single-Ended I/O Standards for Arria II GX Devices I/O Standard VCCIO (V) V IL (V) V IH (V) V OL (V) V OH (V) IOL (mA) IOH (mA)Min Typ Max Min Max Min Max Max Min 0.3 0.45 2.4 4 –4 0.3 0.4 2 1 –1 VCCIO 0.65 × VCCIO VCCIO + 0.3 0.45 VCCIO - 0.45 2– 2 VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2– 2 VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2– 2 3.0-V PCI 2.85 3 3.15 — 0.3 × VCCIO 0.5 × VCCIO VCCIO + 0.3 0.1 × VCCIO 0.9 × VCCIO 1.5 –0.5 3.0-V PCI-X 2.85 3 3.15 — 0.35 × VCCIO 0.5 × VCCIO VCCIO + 0.3 0.1 × VCCIO 0.9 × VCCIO 1.5 –0.5 Table 1–23. Single-Ended I/O Standards for Arria II GZ Devices (Part 1 of 2) I/O Standard VCCIO (V) V IL (V) V IH (V) V OL (V) V OH (V) IOL (mA) IOH (mA)Min Typ Max Min Max Min Max Max Min VCCIO 0.65 × VCCIO VCCIO + 0.3 0.45 VCCIO - 0.45 2- 2 VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2- 2

1–16 Chapter 1: Device Datasheet for Arria II Devices Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–24 lists the single-ended SSTL and HSTL I/O reference voltage specifications for Arria II GX devices. Table 1–25 lists the single-ended SSTL and HSTL I/O reference voltage specifications for Arria II GZ devices. VCCIO 0.65 × VCCIO VCCIO + 0.3 0.25 × VCCIO 0.75 × VCCIO 2- 2 3.0-V PCI 2.85 3 3.15 — 0.3 × VCCIO 0.5 × VCCIO 3.6 0.1 × VCCIO 0.9 × VCCIO 1.5 -0.5 3.0-V PCI-X 2.85 3 3.15 — 0.35 × VCCIO 0.5 × VCCIO — 0.1 × VCCIO 0.9 × VCCIO 1.5 -0.5 Table 1–23. Single-Ended I/O Standards for Arria II GZ Devices (Part 2 of 2) I/O Standard VCCIO (V) V IL (V) V IH (V) V OL (V) V OH (V) IOL (mA) IOH (mA)Min Typ Max Min Max Min Max Max Min Table 1–24. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Arria II GX Devices I/O Standard VCCIO (V) V REF (V) V TT (V) Min Typ Max Min Typ Max Min Typ Max SSTL-2 Class I, II 2.375 2.5 2.625 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO VREF -

0.04 VREF

0.04 0.04 SSTL-15 Class I, II 1.425 1.5 1.575 0.47 × VCCIO 0.5 × VCCIO 0.53 × VCCIO 0.47 × VCCIO 0.5 × VCCIO 0.53 × VCCIO HSTL-12 Class I, II 1.14 1.2 1.26 0.48 × VCCIO 0.5 × VCCIO 0.52 × VCCIO —V CCIO/2 — Table 1–25. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications for Arria II GZ Devices I/O Standard VCCIO (V) V REF (V) V TT (V) Min Typ Max Min Typ Max Min Typ Max SSTL-2 Class I, II 2.375 2.5 2.625 0.49 × VCCIO 0.5 × VCCIO 0.51 × VCCIO VREF - 0.04 0.04 SSTL-15 Class I, II 1.425 1.5 1.575 0.47 × VCCIO 0.5 × VCCIO 0.53 × VCCIO 0.47 × VCCIO VREF 0.53 × VCCIO HSTL-12 Class I, II 1.14 1.2 1.26 0.47 × VCCIO 0.5 × VCCIO 0.53 × VCCIO —V CCIO/2 —

Chapter 1: Device Datasheet for Arria II Devices 1–17 December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Table 1–26 lists the single-ended SSTL and HSTL I/O standard signal specifications for Arria II GX devices. Table 1–27 lists the single-ended SSTL and HSTL I/O standard signal specifications for Arria II GZ devices. Table 1–26. Single-Ended SSTL and HSTL I/O Standard Signal Specifications for Arria II GX Devices I/O Standard VIL(DC) (V) V IH(DC) (V) V IL(AC) (V) V IH(AC) (V) V OL (V) V OH (V) IOL (mA) IOH (mA)Min Max Min Max Max Min Max Min SSTL-2 Class I –0.3 VREF - 0.18 VREF + 0.18 VCCIO + 0.3 VREF - 0.35 VREF + 0.35 VTT - 0.57 VTT + 0.57 8.1 –8.1 SSTL-2 Class II –0.3 VREF - 0.18 VREF + 0.18 VCCIO + 0.3 VREF - 0.35 VREF + 0.35 VTT - 0.76 VTT + 0.76 16.4 –16.4 SSTL-18 Class I –0.3 VREF - 0.125 VREF + 0.125 VCCIO + 0.3 VREF - 0.25 VREF + 0.25 VTT - 0.475 VTT + 0.475 6.7 –6.7 SSTL-18 Class II –0.3 VREF - 0.125 VREF + 0.125 VCCIO + 0.3 VREF - 0.25 VREF + 0.25 0.28 VCCIO - 0.28 13.4 –13.4 SSTL-15 Class I –0.3 VREF - 0.1 VREF + 0.1 VCCIO + 0.3 VREF - 0.175 VREF + 0.175 0.2 × VCCIO 0.8 × VCCIO 8– 8 SSTL-15 Class II –0.3 VREF - 0.1 VREF + 0.1 VCCIO + 0.3 VREF - 0.175 VREF + 0.175 0.2 × VCCIO 0.8 × VCCIO 16 –16 HSTL-18 Class I –0.3 VREF - 0.1 VREF + 0.1 VCCIO + 0.3 VREF - 0.2 V REF + 0.2 0.4 VCCIO - 0.4 8– 8 HSTL-18 Class II –0.3 VREF - 0.1 VREF + 0.1 VCCIO + 0.3 VREF - 0.2 V REF + 0.2 0.4 VCCIO - 0.4 16 –16 HSTL-15 Class I –0.3 VREF - 0.1 VREF + 0.1 VCCIO + 0.3 VREF - 0.2 V REF + 0.2 0.4 VCCIO - 0.4 8– 8 HSTL-15 Class II –0.3 VREF - 0.1 VREF + 0.1 VCCIO + 0.3 VREF - 0.2 V REF + 0.2 0.4 VCCIO - 0.4 16 –16 HSTL-12 Class I –0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO 8– 8 HSTL-12 Class II –0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 0.25 × VCCIO 0.75 × VCCIO 14 –14 Table 1–27. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Arria II GZ Devices (Part 1 of 2) I/O Standard VIL(DC) (V) V IH(DC) (V) V IL(AC) (V) V IH(AC) (V) V OL (V) V OH (V) IOL (mA) IOH (mA)Min Max Min Max Max Min Max Min SSTL-2 Class I -0.3 VREF - 0.15 VREF + 0.15 VCCIO + 0.3 VREF - 0.31 VREF + 0.31 VTT - 0.57 VTT + 0.57 8.1 -8.1 SSTL-2 Class II -0.3 VREF - 0.15 VREF + 0.15 VCCIO + 0.3 VREF - 0.31 VREF + 0.31 VTT - 0.76 VTT + 0.76 16.2 -16.2 SSTL-18 Class I -0.3 VREF - 0.125 VREF + 0.125 VCCIO + 0.3 VREF - 0.25 VREF + 0.25 VTT - 0.475 VTT + 0.475 6.7 -6.7 SSTL-18 Class II -0.3 VREF - 0.125 VREF + 0.125 VCCIO + 0.3 VREF - 0.25 VREF + 0.25 0.28 VCCIO - 0.28 13.4 -13.4 SSTL-15 Class I — VREF - 0.1 VREF + 0.1 — VREF - 0.175 VREF + 0.175 0.2 × VCCIO 0.8 × VCCIO 8- 8

1–18 Chapter 1: Device Datasheet for Arria II Devices Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–28 lists the differential SSTL I/O standards for Arria II GX devices. Table 1–29 lists the differential SSTL I/O standards for Arria II GZ devices SSTL-15 Class II — VREF - 0.1 VREF + 0.1 — VREF - 0.175 VREF + 0.175 0.2 × VCCIO 0.8 × VCCIO 16 -16 HSTL-18 Class I — VREF - 0.1 VREF + 0.1 —V REF - 0.2 V REF + 0.2 0.4 VCCIO - 0.4 8- 8 HSTL-18 Class II — VREF - 0.1 VREF + 0.1 —V REF - 0.2 V REF + 0.2 0.4 VCCIO - 0.4 16 -16 HSTL-15 Class I — VREF - 0.1 VREF + 0.1 —V REF - 0.2 V REF + 0.2 0.4 VCCIO - 0.4 8- 8 HSTL-15 Class II — VREF - 0.1 VREF + 0.1 —V REF - 0.2 V REF + 0.2 0.4 VCCIO - 0.4 16 -16 HSTL-12 Class I -0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 0.25× VCCIO 0.75× VCCIO 8- 8 HSTL-12 Class II -0.15 VREF - 0.08 VREF + 0.08 VCCIO + 0.15 VREF - 0.15 VREF + 0.15 0.25× VCCIO 0.75 × VCCIO 16 -16 Table 1–27. Single-Ended SSTL and HSTL I/O Standards Signal Specifications for Arria II GZ Devices (Part 2 of 2) I/O Standard VIL(DC) (V) V IH(DC) (V) V IL(AC) (V) V IH(AC) (V) V OL (V) V OH (V) IOL (mA) IOH (mA)Min Max Min Max Max Min Max Min Table 1–28. Differential SSTL I/O Standards for Arria II GX Devices I/O Standard VCCIO (V) V SWING(DC) (V) V X(AC) (V) V SWING(AC) (V) V OX(AC) (V) Min Typ Max Min Max Min Typ Max Min Max Min Typ Max SSTL-2 Class I, II 2.375 2.5 2.625 0.36 V CCIO VCCIO/2 - 0.2 — VCCIO/2 + 0.2 0.7 V CCIO VCCIO/2 - 0.15 — VCCIO/2 + 0.15 SSTL-18 Class I, II 1.71 1.8 1.89 0.25 V CCIO VCCIO/2 - 0.175 — VCCIO/2 + 0.175 0.5 V CCIO VCCIO/2 0.125 VCCIO/2 0.125 SSTL-15 Class I, II 1.425 1.5 1.575 0.2 — — VCCIO/ 2 —0 . 3 5 — — VCCIO/ 2 — Table 1–29. Differential SSTL I/O Standards for Arria II GZ Devices I/O Standard VCCIO (V) V SWING(DC) (V) V X(AC) (V) V SWING(AC) (V) V OX(AC) (V) Min Typ Max Min Max Min Typ Max Min Max Min Typ Max SSTL-2 Class I, II 2.375 2.5 2.625 0.3 VCCIO + 0.6 VCCIO/2 - 0.2 — VCCIO/2 + 0.2 0.62 VCCIO + 0.6 VCCIO/2 - 0.15 — VCCIO/2 + 0.15 SSTL-18 Class I, II 1.71 1.8 1.89 0.25 VCCIO + 0.6 VCCIO/2 0.175 VCCIO/2 0.175

0.5 VCCIO

+ 0.6 VCCIO/2 - 0.125 — VCCIO/2 + 0.125 SSTL-15 Class I, II 1.425 1.5 1.575 0.2 — — VCCIO/ 2 —0 . 3 5 — — VCCIO/ 2 —

Chapter 1: Device Datasheet for Arria II Devices 1–19 December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Table 1–30 lists the HSTL I/O standards for Arria II GX devices. Table 1–31 lists the HSTL I/O standards for Arria II GZ devices. Table 1–32 lists the differential I/O standard specifications for Arria II GX devices. Table 1–30. Differential HSTL I/O Standards for Arria II GX Devices I/O Standard VCCIO (V) V DIF(DC) (V) V X(AC) (V) V CM(DC) (V) V DIF(AC) (V) Min Typ Max Min Max Min Typ Max Min Typ Max Min Max VCCIO 0.48 VCCIO 0.5 × VCCIO 0.52 × VCCIO 0.3 — Table 1–31. Differential HSTL I/O Standards for Arria II GZ Devices I/O Standard VCCIO (V) V DIF(DC) (V) V X(AC) (V) V CM(DC) (V) V DIF(AC) (V) Min Typ Max Min Max Min Typ Max Min Typ Max Min Max HSTL-12 Class I, II 1.14 1.2 1.26 0.16 VCCIO + 0.3 — 0.5 × VCCIO — 0.4 × VCCIO 0.5 × VCCIO 0.6 × VCCIO 0.3 VCCIO 0.48 Table 1–32. Differential I/O Standard Specifications for Arria II GX Devices (Note 1) I/O Standard VCCIO (V) V ID (mV) V ICM (V) (2) VOD (V) (3) VOCM (V) Min Typ Max Min Cond. Max Min Max Min Typ Max Min Typ Max 2.5 V LVDS 2.375 2.5 2.625 100 VCM = Mini-LVDS LVPECL Notes to Table 1–32: (1) The 1.5 V PCML transceiver I/O standa rd specifications are described in “Transceiver Performance Specifications” on page 1–21. (2) V IN range: 0 <= VIN <= 1.85 V. (3) R L range: 90 <= RL <= 110 . (4) The RSDS and mini-LVDS I/O standards ar e only supported for differential outputs. (5) The LVPECL input standard is supported at the dedicated clock input pins (GCLK) only. (6) There are no fixed V ICM, VOD, and VOCM specifications for BLVDS. These specifications depend on the system topology.

1–20 Chapter 1: Device Datasheet for Arria II Devices Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–33 lists the differential I/O standard specifications for Arria II GZ devices. Power Consumption for the Arria II Device Family Altera offers two ways to estimate power for a design: ■ Using the Microsoft Excel-based Early Power Estimator ■ Using the Quartus® II PowerPlay Power Analyzer feature The interactive Microsoft Excel-based Early Power Estimator is typically used prior to designing the FPGA in order to get a magnitude estimate of the device power. The Quartus II PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The PowerPlay Power Analyzer can apply a combination of user-entered, simulation-derived, and estimated signal activities which, when combined with detailed circuit models, can yield very accurate power estimates. f For more information about power estimation tools, refer to the PowerPlay Early Power Estimator User Guide and the PowerPlay Power Analysis chapter in volume 3 of the Quartus II Handbook. Table 1–33. Differential I/O Standard Specifications for Arria II GZ Devices (Note 1) I/O Standard (2) VCCIO (V) V ID (mV) V ICM(DC) (V) V OD (V) (3) VOCM (V) (3) Min Typ Max Min Cond. Max Min Max Min Typ Max Min Typ Max 2.5 V LVDS (HIO) 2.375 2.5 2.625 100 VCM = 2.5 V LVDS (VIO) 2.375 2.5 2.625 100 VCM = RSDS (HIO) 2.375 2.5 2.625 100 VCM = RSDS (VIO) 2.375 2.5 2.625 100 VCM = Mini-LVDS 5 0.25 — 0.6 1 1.2 1.4 Mini-LVDS 5 0.25 — 0.6 1 1.2 1.5 Notes to Table 1–33: (1) 1.4-V/1.5-V PCML transceiver I/O stan dard specifications are described in “Transceiver Performance Specifications” on page 1–21. (2) Vertical I/O (VIO) is top and bottom I/Os; horizontal I/O (HIO) is left and right I/Os. (3) R L range: 90  RL  110 . (4) There are no fixed V ICM, VOD, and VOCM specifications for BLVDS. These specifications depend on the system topology.

Chapter 1: Device Datasheet for Arria II Devices 1–21 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Switching Characteristics This section provides performance characteristics of the Arria II GX and GZ core and periphery blocks for commercial grade devices. The following tables are considered final and are based on actual silicon characterization and testing. These numbers reflect the actual performance of the device under worst-case silicon process, voltage, and junction temperature conditions. Transceiver Performance Specifications Table 1–34 lists the Arria II GX transceiver specifications. Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 1 of 7) Symbol/ Description Condition I3 C4 C5 and I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Reference Clock Supported I/O Standards 1.2-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and HCSL Input frequency from REFCLK input pins — 50 — 622.08 50 — 622.08 50 — 622.08 50 — 622.08 MHz Input frequency from PLD input — 50 — 200 50 — 200 50 — 200 50 — 200 MHz Absolute VMAX for a REFCLK pin — — — 2.2 — — 2.2 — — 2.2 — — 2.2 V Absolute VMIN for Rise/fall time (2) — — — 0.2 — — 0.2 — — 0.2 — — 0.2 UI Duty cycle — 45 — 55 45 — 55 45 — 55 45 — 55 % Peak-to-peak differential input voltage — 200 — 2000 200 — 2000 200 — 2000 200 — 2000 mV Spread-spectrum modulating clock frequency PCIe 30 — 33 30 — 33 30 — 33 30 — 33 kHz

Chapter 1: Device Datasheet for Arria II Devices 1–22 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Spread-spectrum downspread PCIe — 0 to –0.5% —— 0 to –0.5% —— 0 to –0.5% —— 0 to –0.5% —— On-chip termination resistors VICM (AC coupled) — 1100 ± 5% 1100 ± 5% 1100 ± 5% 1100 ± 5% mV VICM (DC coupled) HCSL I/O standard for PCIe reference clock 250 — 550 250 — 550 250 — 550 250 — 550 mV Transmitter REFCLK Phase Noise Transmitter REFCLK Phase Jitter (rms) for

100 MHz

REFCLK (3)

10 KHz to

20 MHz

R ref —— 2000 ±1 % —— 2000 ±1 % —— 2000 ±1 % —— 2000 ± 1% —  Transceiver Clocks Calibration block clock frequency (cal_blk_clk) — 10 — 125 10 — 125 10 — 125 10 — 125 MHz Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 2 of 7) Symbol/ Description Condition I3 C4 C5 and I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–23 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum fixedclk clock frequency PCIe Receiver Detect reconfig_ clk clock frequency Dynamic reconfig. clock frequency 2.5/ 37.5 (4) —5 0 2.5/ 37.5 (4) —5 0 2.5/ 37.5 (4) —5 0 2.5/ 37.5 (4) —5 0M H z Delta time between reconfig_ clks (5) Transceiver block minimum power-down pulse width Receiver Supported I/O Standards 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, 2.5-V PCML, LVPECL, and LVDS Data rate (13) — 600 — 6375 600 — 3750 600 — 3750 600 — 3125 Mbps Absolute V MAX for a receiver pin (6) Absolute VMIN for Maximum peak-to-peak differential input voltage V ID (diff p-p) VICM = 0.82 V VICM =1.1 V Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 3 of 7) Symbol/ Description Condition I3 C4 C5 and I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

1–24 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2 013 Altera Corporation Minimum peak-to-peak differential input voltage V ID (diff p-p) VICM VICM = 0.82 V setting — 820 — — 820 — — 820 — — 820 — mV VICM =1.1 V setting (7) — 1100 — — 1100 — — 1100 — — 1100 — mV Differential on-chip termination resistors 100 Return loss differential mode PCIe 50 MHz to 1.25 GHz: –10dB XAUI 100 MHz to 2.5 GHz: –10dB Return loss common mode PCIe 50 MHz to 1.25 GHz: –6dB XAUI 100 MHz to 2.5 GHz: –6dB Programmable PPM detector (8) 250, 300, 500, 1000 ppm Programmable Signal detect/loss threshold PCIe Mode 65 — 175 65 — 175 65 — 175 65 — 175 mV CDR LTR time CDR minimum Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 4 of 7) Symbol/ Description Condition I3 C4 C5 and I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–25 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum LTD lock time (11) — 0 100 4000 0 100 4000 0 100 4000 0 100 4000 ns Data lock time from rx_ freqlocked (12) Programmable DC gain DC Gain DC Gain DC Gain Transmitter Supported I/O Standards 1.5-V PCML Data rate — 600 — 6375 600 — 3750 600 — 3750 600 — 3125 Mbps VOCM 0.65 V setting — 650 — — 650 — — 650 — — 650 — mV Differential on-chip termination resistors 100 Return loss differential mode PCIe 50 MHz to 1.25 GHz: –10dB XAUI 312 MHz to 625 MHz: –10dB 625 MHz to 3.125 GHz: –10dB/decade slope Return loss common mode PCIe 50 MHz to 1.25 GHz: –6dB Rise time (2) — 50 — 200 50 — 200 50 — 200 50 — 200 ps Fall time — 50 — 200 50 — 200 50 — 200 50 — 200 ps Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 5 of 7) Symbol/ Description Condition I3 C4 C5 and I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

1–26 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2 013 Altera Corporation Intra- differential pair skew Intra-transceiver block skew PCIe ×4 — — 120 — — 120 — — 120 — — 120 ps Inter-transceiver block skew PCIe ×8 — — 300 — — 300 — — 300 — — 300 ps CMU PLL0 and CMU PLL1 CMU PLL lock time from CMUPLL_ reset deassertion PLD-Transceiver Interface Interface speed — 25 — 320 25 — 240 25 — 240 25 — 200 MHz Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 6 of 7) Symbol/ Description Condition I3 C4 C5 and I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–27 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Digital reset pulse width — Minimum is 2 parallel clock cycles Notes to Table 1–34: (1) For AC-coupled links, the on-chip biasing circuit is switched off before and during configuration. Ensure that input specifi cations are not violated during this period. (2) The rise/fall time is sp ecified from 20% to 80%. (3) To calculate the REFCLK rms phase jitter re quirement at reference clock frequencies other than 100 MHz, use the following formula: REFCLK rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f. (4) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum reconfig_clk frequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode. For more information, refer to AN 558: Implementing Dynamic Reconfiguration in Arria II Devices. (5) If your design uses more than one dynami c reconfiguration controller instances (altgx_reconfig) to control the transceiver channels (altgx) physically located on the same side of the device, and if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed. (6) The device cannot tolerate prolonged operation at this absolute maximum. (7) You must use the 1.1-V RX V ICM setting if the input serial data standard is LVDS and the link is DC-coupled. (8) The rate matcher supports only up to ±300 parts per million (ppm). (9) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to Figure 1–1. (10) The time in which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. Refer to Figure 1–1. (11) The time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1–1. (12) The time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1–2. (13) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only. Table 1–34. Transceiver Specifications for Arria II GX Devices (Note 1) (Part 7 of 7) Symbol/ Description Condition I3 C4 C5 and I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

1–28 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–35 lists the transceiver specifications for Arria II GZ devices. Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 1 of 5) Symbol/ Description Conditions –C3 and –I3 (1) –C4 and –I4 Unit Min Typ Max Min Typ Max Reference Clock Supported I/O Standards 1.2-V PCML, 1.5-V PCML, 2.5-V PCML, Differential LVPECL, LVDS, and HCSL Input frequency from REFCLK input pins — 50 — 697 50 — 637.5 MHz Phase frequency detector (CMU PLL and receiver CDR) — 50 — 325 50 — 325 MHz Absolute VMAX for a REFCLK Operational VMAX for a REFCLK pin —— — 1 . 5 — — 1 . 5 V Absolute VMIN for a REFCLK Rise/fall time (2) — — — 0.2 — — 0.2 UI Duty cycle — 45 — 55 45 — 55 % Peak-to-peak differential input voltage — 200 — 1600 200 — 1600 mV Spread-spectrum modulating clock frequency PCIe 30 — 33 30 — 33 kHz Spread-spectrum downspread PCIe — 0 to -0.5% 0 to -0.5% On-chip termination VICM (AC coupled) — 1100 ± 10% 1100 ± 10% mV VICM (DC coupled) HCSL I/O standard for PCIe reference clock 250 — 550 250 — 550 mV Transmitter REFCLK Phase Noise

10 Hz — — -50 — — -50 dBc/Hz

100 Hz — — -80 — — -80 dBc/Hz

1 KHz — — -110 — — -110 dBc/Hz

10 KHz — — -120 — — -120 dBc/Hz

100 KHz — — -120 — — -120 dBc/Hz

 1 MHz — — -130 — — -130 dBc/Hz Transmitter REFCLK Phase Jitter (rms) for 100 MHz REFCLK (3)

10 KHz to 20 MHz — — 3 — — 3 ps

R REF —— 2000 ± 1% —— 2000 ± 1% — 

Chapter 1: Device Datasheet for Arria II Devices 1–29 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Transceiver Clocks Calibration block clock frequency (cal_blk_clk) — 10 — 125 10 — 125 MHz fixedclk clock frequency PCIe Receiver Detect — 125 — — 125 — MHz reconfig_clk clock frequency Dynamic reconfiguration clock frequency 2.5/ 37.5 (4) —5 0 2.5/ 37.5 (4) —5 0 M H z Delta time between reconfig_clks (5) —— — 2 — — 2 m s Transceiver block minimum power-down gxb_powerdown) pulse width Receiver Supported I/O Standards 1.4-V PCML, 1.5-V PCML, 2.5-V PCML, LVPECL, and LVDS Data rate (16) — 600 — 6375 600 — 3750 Mbps Absolute VMAX for a receiver Operational VMAX for a receiver pin —— — 1 . 5 — — 1 . 5 V Absolute VMIN for a receiver Maximum peak-to-peak differential input voltage VID (diff p-p) before device configuration Maximum peak-to-peak differential input voltage V ID (diff p-p) after device configuration VICM = 0.82 V setting — — 2.7 — — 2.7 V VICM =1.1 V setting Minimum differential eye opening at receiver serial input pins (8) Data Rate =

600 Mbps to

5 Gbps

Equalization = 0 DC gain = 0 dB 100 — — 165 — — mV Data Rate > 5 Gbps Equalization = 0 DC gain = 0 dB 165 — — 165 — — mV VICM VICM = 0.82 V setting 820 ± 10% 820 ± 10% mV VICM = 1.1 V setting (7) 1100 ± 10% 1100 ± 10% mV Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 2 of 5) Symbol/ Description Conditions –C3 and –I3 (1) –C4 and –I4 Unit Min Typ Max Min Typ Max

1–30 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Receiver DC Coupling Support — For more information about receiver DC coupling support, refer to the “DC-Coupled Links” section in the Transceiver Architecture for Arria II Devices chapter. Differential on-chip termination resistors 85 setting 85 ± 20% 85 ± 20%  100 setting 100 ± 20% 100 ± 20%  120 setting 120 ± 20% 120 ± 20%  150- setting 150 ± 20% 150 ± 20%  Differential and common mode return loss PCIe (Gen 1 and Gen 2), XAUI, HiGig+, CEI SR/LR, SRIO SR/LR, CPRI LV/HV, OBSAI, SATA Compliant — Programmable PPM detector (9) — ± 62.5, 100, 125, 200, 250, 300, 500, 1,000 ppm Run length — — — 200 — — 200 UI Programmable equalization — — — 16 — — 16 dB tLTR (10) —— — 7 5 — — 7 5 µ s tLTR_LTD_Manual (11) —1 5 — — 1 5 — — µ s tLTD_Manual (12) — — — 4000 — — 4000 ns tLTD_Auto (13) — — — 4000 — — 4000 ns Receiver CDR 3 dB Bandwidth in lock-to-data (LTD) mode PCIe Gen1 2.0 - 3.5 MHz PCIe Gen2 40 - 65 MHz (OIF) CEI PHY at

6.375 Gbps 20 - 35 MHz

SRIO 1.25 Gbps 10 - 18 MHz SRIO 2.5 Gbps 10 - 18 MHz SRIO 3.125 Gbps 6 - 10 MHz GIGE 6 - 10 MHz SONET OC12 3 - 6 MHz SONET OC48 14 - 19 MHz Receiver buffer and CDR offset cancellation time (per channel) recon fig_ clk cycles Programmable DC gain DC Gain Setting = 0 — 0 — — 0 — dB DC Gain Setting = 1 — 3 — — 3 — dB DC Gain Setting = 2 — 6 — — 6 — dB Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 3 of 5) Symbol/ Description Conditions –C3 and –I3 (1) –C4 and –I4 Unit Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–31 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Transmitter Supported I/O Standards 1.5-V PCML Data rate (14) — 600 — 6375 600 — 3750 Mbps VOCM 0.65 V setting — 650 — — 650 — mV Differential on-chip termination resistors 85 setting 85 ± 15% 85 ± 15%  100 setting 100 ± 15% 100 ± 15%  120 setting 120 ± 15% 120 ± 15%  150- setting 150 ± 15% 150 ± 15%  Differential and common mode return loss PCIe Gen1 and Gen2 (TX VOD=4), XAUI (TX VOD=6), HiGig+ (TX VOD=6), CEI SR/LR (TX VOD=8), SRIO SR (VOD=6), SRIO LR (VOD=8), CPRI LV (VOD=6), CPRI HV (VOD=2), OBSAI (VOD=6), SATA (VOD=4), Compliant — Rise time (15) — 50 — 200 50 — 200 ps Fall time (15) — 50 — 200 50 — 200 ps Intra-differential pair skew — — — 15 — — 15 ps Intra-transceiver block transmitter channel-to-channel skew ×4 PMA and PCS bonded mode Example: XAUI, PCIe ×4, Basic ×4 —— 1 2 0——1 2 0p s Inter-transceiver block transmitter channel-to-channel skew ×8 PMA and PCS bonded mode Example: PCIe ×8, Basic ×8 —— 5 0 0——5 0 0p s CMU0 PLL and CMU1 PLL Supported Data Range — 600 — 6375 600 — 3750 Mbps pll_powerdown minimum pulse width (tpll_powerdown) —1 1 s CMU PLL lock time from pll_powerdown de-assertion Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 4 of 5) Symbol/ Description Conditions –C3 and –I3 (1) –C4 and –I4 Unit Min Typ Max Min Typ Max

1–32 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation -3 dB Bandwidth PCIe Gen1 2.5 - 3.5 MHz PCIe Gen2 6 - 8 MHz (OIF) CEI PHY at

4.976 Gbps 7 - 11 MHz

(OIF) CEI PHY at

6.375 Gbps 5 - 10 MHz

SRIO 1.25 Gbps 3 - 5.5 MHz SRIO 2.5 Gbps 3 - 5.5 MHz SRIO 3.125 Gbps 2 - 4 MHz GIGE 2.5 - 4.5 MHz SONET OC12 1.5 - 2.5 MHz SONET OC48 3.5 - 6 MHz Transceiver-FPGA Fabric Interface Interface speed — 25 — 325 25 — 250 MHz Digital reset pulse width — Minimum is two parallel clock cycles — Notes to Table 1–35: (1) The 3x speed grade is the fastest speed grade offered in the following Arria II GZ devices: EP2AGZ225, EP2AGZ300, and EP2AGZ350. (2) The rise and fall time transiti on is specified from 20% to 80%. (3) To calculate the REFCLK rms phase jitter requirement at reference clock frequencies other than 100 MHz, use the following formula: REFCLK rms phase jitter at f (MHz) = REFCLK rms phase jitter at 100 MHz * 100/f. (4) The minimum reconfig_clk frequency is 2.5 MHz if the transceiver channel is configured in Transmitter only mode. The minimum reconfig_clk frequency is 37.5 MHz if the transceiver channel is configured in Receiver only or Receiver and Transmitter mode. (5) If your design uses more than one dynamic reconfiguration controller (altgx_reconfig) instances to control the transceiver (altgx) channels physically located on the same side of the device AND if you use different reconfig_clk sources for these altgx_reconfig instances, the delta time between any two of these reconfig_clk sources becoming stable must not exceed the maximum specification listed. (6) The device cannot tolerate prolonged operation at this absolute maximum. (7) You must use the 1.1-V RX V ICM setting if the input serial data standard is LVDS. (8) The differential eye opening specification at the receiver input pins assumes that Receiver Equalization is disabled. If you enable Receiver Equalization, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level. Use H-Spice simulation to derive the minimum eye opening requirement with Receiver Equalization enabled. (9) The rate matcher supports only up to ± 300 ppm. (10) Time taken to rx_pll_locked goes high from rx_analogreset de-assertion. Refer to Figure 1–1 on page 1–33. (11) Time for which the CDR must be kept in lock-to-reference mode after rx_pll_locked goes high and before rx_locktodata is asserted in manual mode. Refer to Figure 1–1 on page 1–33. (12) Time taken to recover valid data after the rx_locktodata signal is asserted in manual mode. Refer to Figure 1–1 on page 1–33. (13) Time taken to recover valid data after the rx_freqlocked signal goes high in automatic mode. Refer to Figure 1–2 on page 1–33. (14) A GPLL may be required to meet the PMA-FPGA fabric interface timing above certain data rates. For more information, refer to the Transceiver Clocking for Arria II Devices chapter. (15) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode. (16) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only. Table 1–35. Transceiver Specifications for Arria II GZ Devices (Part 5 of 5) Symbol/ Description Conditions –C3 and –I3 (1) –C4 and –I4 Unit Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–35 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Table 1–37 lists the typical VOD for TX term that equals 100 . for Arria II GX and GZ devices. Table 1–38 lists the typical transmitter pre-emphasis levels in dB for the first post tap under the following conditions: low-frequency data pattern (five 1s and five 0s) at 6.375 Gbps. The levels listed in Table 1–38 are a representation of possible pre-emphasis levels under these specified conditions only, the pre-emphasis levels may change with data pattern and data rate. To predict the pre-emphasis level for your specific data rate and pattern, run simulations using the Arria II GX HSSI HSPICE models. Table 1–37. Typical V OD Setting, TX Termination = 100  for Arria II Devices Quartus II Setting V OD Setting (mV) 1 400 2 600 3 (Arria II GZ) 700 4 800 5 900 6 1000 7 1200Table 1–38. Transmitter Pre-Emphasis Levels for Arria II GX Devices Arria II GX (Quartus II Software) First Post Tap Setting Arria II GX (Quartus II Software) VOD Setting

124567 U n i t

0 ( o f f ) 000000 — 10 . 7 00000 d B 2 2.7 1.2 0.3 0 0 0 dB 6 — 7 4.3 3.3 2.7 1.7 dB

1–36 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–39 lists typical transmitter pre-emphasis levels for Arria II GZ devices (in dB) for the first post tap under the following conditions (low-frequency data pattern [five 1s and five 0s] at 6.25 Gbps). The levels listed in Table 1–39 are a representation of possible pre-emphasis levels under the specified conditions only and that the pre- emphasis levels may change with data pattern and data rate. f To predict the pre-emphasis level for your specific data rate and pattern, run simulations using the Arria II HSSI HSPICE models. Table 1–39. Transmitter Pre-Emphasis Levels for Arria II GZ Devices (Part 1 of 2) Pre- Emphasis 1st Post-Tap Setting VOD Setting 01234567 0 00000000 1 N / A 0 . 7 000000 2 N / A 1 0 . 3 00000 3 N / A 1 . 5 0 . 6 00000 4N / A20 . 7 0 . 30 0 0 0 5 N/A 2.7 1.2 0.5 0.3 0 0 0 22 N/A N/A 8 6.1 4.8 3.8 3 2 24 N/A N/A 10 7.6 6 4.8 3.9 2.6 28 N/A N/A N/A 11.3 8.8 7.1 5.8 4

Chapter 1: Device Datasheet for Arria II Devices 1–37 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Table 1–40 lists the transceiver jitter specifications for all supported protocols for Arria II GX devices. 30 N/A N/A N/A N/A 11.4 9 7.4 N/A 31 N/A N/A N/A N/A 12.9 10 8.2 N/A Table 1–39. Transmitter Pre-Emphasis Levels for Arria II GZ Devices (Part 2 of 2) Pre- Emphasis 1st Post-Tap Setting V OD Setting 01234567 Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 1 of 10) Symbol/ Description Conditions I3 C4 C5, I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max SONET/SDH Transmit Jitter Generation (2) Peak-to-peak jitter at

622.08 Mbps

Pattern = RMS jitter at Pattern = Peak-to-peak jitter at

2488.32 Mbps

Pattern = RMS jitter at Pattern = SONET/SDH Receiver Jitter Tolerance (2) Jitter tolerance at Jitter frequency =

0.03 KHz

Pattern = PRBS15 > 15 > 15 > 15 > 15 UI Jitter frequency =

25 KHZ

Pattern = PRBS15 Jitter frequency =

250 KHz

Pattern = PRBS15

1–38 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Jitter tolerance at Jitter frequency =

0.06 KHz

Pattern = PRBS15 > 15 > 15 > 15 > 15 UI Jitter frequency =

100 KHZ

Pattern = PRBS15 Jitter frequency = 1M H z Pattern = PRBS15 Jitter frequency =

10 MHz

Pattern = PRBS15 XAUI Transmit Jitter Generation (3) Total jitter at Deterministic jitter at

3.125 Gbps

Pattern = CJPAT — — 0.17 — — 0.17 — — 0.17 — — 0.17 UI XAUI Receiver Jitter Tolerance (3) Total jitter — > 0.65 > 0.65 > 0.65 > 0.65 UI Deterministic jitter — > 0.37 > 0.37 > 0.37 > 0.37 UI Peak-to-peak jitter Jitter frequency = Peak-to-peak jitter Jitter frequency = Peak-to-peak jitter Jitter frequency = 20 MHz > 0.1 > 0.1 > 0.1 > 0.1 UI PCIe Transmit Jitter Generation (4) Total jitter at

2.5 Gbps (Gen1)

Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 2 of 10) Symbol/ Description Conditions I3 C4 C5, I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–39 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum PCIe Receiver Jitter Tolerance (4) Total jitter at pattern > 0.6 > 0.6 > 0.6 > 0.6 UI PCIe (Gen 1) Electrical Idle Detect Threshold (9) VRX-IDLE- DETDIFF (p-p) Compliance pattern 65 — 175 65 — 175 65 — 175 65 — 175 mV Serial RapidIO® (SRIO) Transmit Jitter Generation (5) Deterministic jitter (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Total jitter (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT SRIO Receiver Jitter Tolerance (5) Deterministic jitter tolerance (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Combined deterministic and random jitter tolerance (peak-to-peak) Data Rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Sinusoidal jitter tolerance (peak-to-peak) Jitter frequency =

22.1 KHz

Data rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Jitter frequency =

1.875 MHz

Data rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Jitter frequency = Data rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT GIGE Transmit Jitter Generation (6) Deterministic jitter (peak-to-peak) Pattern = CRPAT — — 0.14 — — 0.14 — — 0.14 — — 0.14 UI Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 3 of 10) Symbol/ Description Conditions I3 C4 C5, I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

1–40 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Total jitter (peak-to-peak) Pattern = CRPAT — — 0.27 GIGE Receiver Jitter Tolerance (6) Deterministic jitter tolerance (peak-to-peak) Pattern = CJPAT > 0.4 > 0.4 > 0.4 > 0.4 UI Combined deterministic and random jitter tolerance (peak-to-peak) Pattern = CJPAT > 0.66 > 0.66 > 0.66 > 0.66 UI HiGig Transmit Jitter Generation (7) Deterministic jitter (peak-to-peak) Data rate =

3.75 Gbps

Pattern = CJPAT Total jitter (peak-to-peak) Data rate = Pattern = CJPAT HiGig Receiver Jitter Tolerance (7) Deterministic jitter tolerance (peak-to-peak) Data rate = Pattern = CJPAT Combined deterministic and random jitter tolerance (peak-to-peak) Data rate = Pattern = CJPAT Sinusoidal jitter tolerance (peak-to-peak) Jitter frequency = Data rate = Pattern = CJPAT Jitter frequency = 1.875MHz Data rate = Pattern = CJPAT Jitter frequency = Data rate = Pattern = CJPAT Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 4 of 10) Symbol/ Description Conditions I3 C4 C5, I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–41 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum SDI Transmitter Jitter Generation (8) Alignment jitter (peak-to-peak) Data rate =

1.485 Gbps (HD)

pattern = Color Bar Low- frequency Roll-off = 100 KHz Data rate =

2.97 Gbps (3G)

pattern = Color bar Low- frequency Roll-off = 100 KHz SDI Receiver Jitter Tolerance (8) Sinusoidal jitter tolerance (peak-to-peak) Jitter frequency =

15 KHz

Data rate = Pattern = single line scramble color bar > 2 > 2 > 2 > 2 UI Jitter frequency = Data rate = Pattern = single line scramble color bar Jitter frequency =

148.5 MHz

Data rate = Pattern = single line scramble color bar Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 5 of 10) Symbol/ Description Conditions I3 C4 C5, I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

1–42 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Sinusoidal jitter tolerance (peak-to-peak) Jitter frequency =

20 KHz

Data rate = Pattern = 75% color bar > 1 > 1 > 1 > 1 UI Jitter frequency = Data rate = 1.485 Gbps (HD) Pattern = 75% color bar Jitter frequency = Data rate = Pattern =75% color bar SATA Transmit Jitter Generation (10) Total jitter at

1.5 Gbps (G1)

jitter at 1.5 Gbps (G1) Compliance Total jitter at

3.0 Gbps (G2)

jitter at 3.0 Gbps (G2) Compliance Total jitter at

6.0 Gbps (G3)

SATA Receiver Jitter Tolerance (10) Total jitter tolerance at pattern > 0.65 > 0.65 > 0.65 > 0.65 UI Deterministic jitter tolerance at pattern > 0.35 > 0.35 > 0.35 > 0.35 UI SSC modulation frequency at Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 6 of 10) Symbol/ Description Conditions I3 C4 C5, I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–43 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum SSC modulation deviation at pattern 5700 5700 5700 5700 ppm RX differential skew at 1.5 Gbps (G1) Compliance pattern 80 80 80 80 ps RX AC common mode voltage at pattern 150 150 150 150 mV Total jitter tolerance at pattern > 0.65 > 0.65 > 0.65 > 0.65 UI Deterministic jitter tolerance at pattern > 0.35 > 0.35 > 0.35 > 0.35 UI SSC modulation frequency at pattern 5700 5700 5700 5700 ppm RX differential skew at 3.0 Gbps (G2) Compliance pattern 75 75 75 75 ps RX AC common mode voltage at pattern 150 150 150 150 mV Total jitter tolerance at pattern > 0.60 > 0.60 > 0.60 > 0.60 UI Random jitter tolerance at pattern > 0.18 > 0.18 > 0.18 > 0.18 UI SSC modulation frequency at pattern 5700 5700 5700 5700 ppm RX differential skew at 6.0 Gbps (G3) Compliance pattern 30 30 30 30 ps RX AC common mode voltage at pattern 100 100 100 100 mV Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 7 of 10) Symbol/ Description Conditions I3 C4 C5, I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

1–44 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation CPRI Transmit Jitter Generation (11) Total jitter E.6.HV, E.12.HV Pattern = CJPAT —— 0.27 E.6.LV, E.12.LV, E.24.LV, E.30.LV Pattern = CJTPAT Deterministic jitter E.6.HV, E.12.HV Pattern = CJPAT E.6.LV, E.12.LV, E.24.LV, E.30.LV Pattern = CJTPAT CPRI Receiver Jitter Tolerance (11) Total jitter tolerance E.6.HV, E.12.HV Pattern = CJPAT Deterministic jitter tolerance E.6.HV, E.12.HV Pattern = CJPAT Total jitter tolerance E.6.LV, E.12.LV, E.24.LV, E.30.LV Pattern = CJTPAT E.60.LV Pattern = PRBS31 > 0.6 — — — UI Deterministic jitter tolerance E.6.LV, E.12.LV, E.24.LV, E.30.LV Pattern = CJTPAT E.60.LV Pattern = PRBS31 > 0.45 — — — UI Combined deterministic and random jitter tolerance E.6.LV, E.12.LV, E.24.LV, E.30.LV Pattern = CJTPAT OBSAI Transmit Jitter Generation (12) Total jitter at

768 Mbps,

1536 Mbps, and

3072 Mbps

REFCLK =

153.6 MHz

Pattern = CJPAT Deterministic jitter at REFCLK = Pattern = CJPAT Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 8 of 10) Symbol/ Description Conditions I3 C4 C5, I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–45 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum OBSAI Receiver Jitter Tolerance (12) Deterministic jitter tolerance at Pattern = CJPAT > 0.37 > 0.37 > 0.37 > 0.37 UI Combined deterministic and random jitter tolerance at Pattern = CJPAT > 0.55 > 0.55 > 0.55 > 0.55 UI Sinusoidal jitter tolerance at

768 Mbps

Jitter frequency =

5.4 KHz

Pattern = CJPAT Jitter frequency =

460.8 KHz to 20

Pattern = CJPAT Sinusoidal jitter tolerance at

1536 Mbps

Jitter frequency =

10.9 KHz

Pattern = CJPAT Jitter frequency =

921.6 KHz to 20

Pattern = CJPAT Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 9 of 10) Symbol/ Description Conditions I3 C4 C5, I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max

1–46 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–41 lists the transceiver jitter specifications for all supported protocols for Arria II GZ devices. Sinusoidal jitter tolerance at Jitter frequency =

21.8 KHz

Pattern = CJPAT Jitter frequency =

1843.2 KHz to 20

Pattern = CJPAT Notes to Table 1–40: (1) Dedicated refclk pins are used to drive the input reference clocks. The jitter numbers are valid for the stated conditions only. (2) The jitter numbers for SONET/SDH are compli ant to the GR-253-CORE Issue 3 Specification. (3) The jitter numbers for XAUI are compli ant to the IEEE802.3ae-2002 Specification. (4) The jitter numbers for PCIe are compli ant to the PCIe Base Specification 2.0. (5) The jitter numbers for SRIO are comp liant to the RapidIO Specification 1.3. (6) The jitter numbers for GIGE are compli ant to the IEEE802.3-2002 Specification. (7) The jitter numbers for Hi Gig are compliant to the IEEE802.3ae-2002 Specification. (8) The HD-SDI and 3G-SDI jitter numbers are compli ant to the SMPTE292M and SMPTE424M Specifications. (9) Arria II PCIe receivers are compliant to this specification provided the VTX_CM-DC-ACTIVEIDLE-DELTA of the upstream transmitter is less than 50 mV. (10) The jitter numbers for Serial Advanced Technology Attachment (SATA) are compliant to the Serial ATA Revision 3.0 Specification. (11) The jitter numbers for Common Public Radio Interfa ce (CPRI) are compliant to the CPRI Specification V3.0. (12) The jitter numbers for Open Base Station Architecture Initiative (OBSAI) are compliant to the OBSAI RP3 Specification V4.1. Table 1–40. Transceiver Block Jitter Specifications for Arria II GX Devices (Note 1) (Part 10 of 10) Symbol/ Description Conditions I3 C4 C5, I5 C6 Unit Min Typ Max Min Typ Max Min Typ Max Min Typ Max Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 1 of 7) Symbol/ Description Conditions –C3 and –I3 –C4 and –I4 Unit Min Typ Max Min Typ Max SONET/SDH Transmit Jitter Generation (3) Peak-to-peak jitter at 622.08 Mbps Pattern = PRBS15 — — 0.1 — — 0.1 UI RMS jitter at 622.08 Mbps Pattern = PRBS15 — — 0.01 — — 0.01 UI Peak-to-peak jitter at 2488.32 Mbps Pattern = PRBS15 — — 0.1 — — 0.1 UI RMS jitter at 2488.32 Mbps Pattern = PRBS15 — — 0.01 — — 0.01 UI SONET/SDH Receiver Jitter Tolerance (3) Jitter tolerance at 622.08 Mbps Jitter frequency = 0.03 KHz Pattern = PRBS15 > 15 > 15 UI Jitter frequency = Pattern = PRBS15 > 1.5 > 1.5 UI Jitter frequency = 250 KHz Pattern = PRBS15 > 0.15 > 0.15 UI

Chapter 1: Device Datasheet for Arria II Devices 1–47 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Jitter tolerance at 2488.32 Mbps Jitter frequency = 0.06 KHz Pattern = PRBS15 > 15 > 15 UI Jitter frequency = 100 KHZ Pattern = PRBS15 > 1.5 > 1.5 UI Jitter frequency = 1M H z Pattern = PRBS15 > 0.15 > 0.15 UI Jitter frequency = 10 MHz Pattern = PRBS15 > 0.15 > 0.15 UI Fibre Channel Transmit Jitter Generation (4), (5) Total jitter FC-1 Pattern = CRPAT — — 0.23 — — 0.23 UI Deterministic jitter FC-1 Pattern = CRPAT — — 0.11 — — 0.11 UI Total jitter FC-2 Pattern = CRPAT — — 0.33 — — 0.33 UI Deterministic jitter FC-2 Pattern = CRPAT — — 0.2 — — 0.2 UI Total jitter FC-4 Pattern = CRPAT — — 0.52 — — 0.52 UI Deterministic jitter FC-4 Pattern = CRPAT — — 0.33 — — 0.33 UI Fibre Channel Receiver Jitter Tolerance (4), (6) Deterministic jitter FC-1 Pattern = CJTPAT > 0.37 > 0.37 UI Random jitter FC-1 Pattern = CJTPAT > 0.31 > 0.31 UI Sinusoidal jitter FC-1 Fc/25000 > 1.5 > 1.5 UI Fc/1667 > 0.1 > 0.1 UI Deterministic jitter FC-2 Pattern = CJTPAT > 0.33 > 0.33 UI Random jitter FC-2 Pattern = CJTPAT > 0.29 > 0.29 UI Sinusoidal jitter FC-2 Fc/25000 > 1.5 > 1.5 UI Fc/1667 > 0.1 > 0.1 UI Deterministic jitter FC-4 Pattern = CJTPAT > 0.33 > 0.33 UI Random jitter FC-4 Pattern = CJTPAT > 0.29 > 0.29 UI Sinusoidal jitter FC-4 Fc/25000 > 1.5 > 1.5 UI Fc/1667 > 0.1 > 0.1 UI XAUI Transmit Jitter Generation (7) Total jitter at 3.125 Gbps Pattern = CJPAT — — 0.3 — — 0.3 UI Deterministic jitter at 3.125 Gbps Pattern = CJPAT — — 0.17 — — 0.17 UI XAUI Receiver Jitter Tolerance (7) Total jitter — > 0.65 > 0.65 UI Deterministic jitter — > 0.37 > 0.37 UI Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 2 of 7) Symbol/ Description Conditions –C3 and –I3 –C4 and –I4 Unit Min Typ Max Min Typ Max

1–48 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Peak-to-peak jitter Jitter frequency = 22.1 KHz > 8.5 > 8.5 UI Peak-to-peak jitter Jitter frequency = 1.875 MHz > 0.1 > 0.1 UI Peak-to-peak jitter Jitter frequency = 20 MHz > 0.1 > 0.1 UI PCIe Transmit Jitter Generation (8) Total jitter at 2.5 Gbps (Gen1)— x1, x4, and x8 Compliance pattern — — 0.25 — — 0.25 UI Total jitter at 5 Gbps (Gen2)— x1, x4, and x8 Compliance pattern — — 0.25 — — — UI PCIe Receiver Jitter Tolerance (8) Total jitter at 2.5 Gbps (Gen1) Compliance pattern > 0.6 > 0.6 UI Total jitter at 5 Gbps (Gen2) Compliance pattern Not supported Not supported UI PCIe (Gen 1) Electrical Idle Detect Threshold VRX-IDLE-DETDIFFp-p (9) Compliance pattern 65 — 175 65 — 175 UI SRIO Transmit Jitter Generation (10) Deterministic jitter (peak-to-peak) Data rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT Total jitter (peak-to-peak) Data rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT SRIO Receiver Jitter Tolerance (10) Deterministic jitter tolerance (peak-to-peak) Data rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT > 0.37 > 0.37 UI Combined deterministic and random jitter tolerance (peak-to- peak) Data rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT > 0.55 > 0.55 UI Sinusoidal jitter tolerance (peak- to-peak) Jitter frequency = 22.1 KHz Data rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT > 8.5 > 8.5 UI Jitter frequency = 1.875 MHz Data rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT > 0.1 > 0.1 UI Jitter frequency = 20 MHz Data rate = 1.25, 2.5, 3.125 Gbps Pattern = CJPAT > 0.1 > 0.1 UI GIGE Transmit Jitter Generation (11) Deterministic jitter (peak-to-peak) Pattern = CRPAT — — 0.14 — — 0.14 UI Total jitter (peak-to-peak) Pattern = CRPAT — — 0.279 — — 0.279 UI Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 3 of 7) Symbol/ Description Conditions –C3 and –I3 –C4 and –I4 Unit Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–49 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum GIGE Receiver Jitter Tolerance (11) Deterministic jitter tolerance (peak-to-peak) Pattern = CJPAT > 0.4 > 0.4 UI Combined deterministic and random jitter tolerance (peak-to- peak) Pattern = CJPAT > 0.66 > 0.66 UI HiGig Transmit Jitter Generation Deterministic jitter (peak-to-peak) Data rate = 3.75 Gbps Pattern = CJPAT Total jitter (peak-to-peak) Data rate = 3.75 Gbps Pattern = CJPAT HiGig Receiver Jitter Tolerance Deterministic jitter tolerance (peak-to-peak) Data rate = 3.75 Gbps Pattern = CJPAT > 0.37 — — — UI Combined deterministic and random jitter tolerance (peak-to- peak) Data rate = 3.75 Gbps Pattern = CJPAT > 0.65 — — — UI Sinusoidal jitter tolerance (peak- to-peak) Jitter frequency = 22.1 KHz Data rate = 3.75 Gbps Pattern = CJPAT > 8.5 — — — UI Jitter frequency = 22.1 KHz Data rate = 3.75 Gbps Pattern = CJPAT > 0.1 — — — UI Jitter frequency = 22.1 KHz Data rate = 3.75 Gbps Pattern = CJPAT > 0.1 — — — UI (OIF) CEI Transmitter Jitter Generation Total jitter (peak-to-peak) Data rate = 6.375 Gbps Pattern = PRBS15 BER = 10 (OIF) CEI Receiver Jitter Tolerance Deterministic jitter tolerance (peak-to-peak) Data rate = 6.375 Gbps Pattern = PRBS31 BER = 10-12 > 0.675 — — — UI Combined deterministic and random jitter tolerance (peak-to- peak) Data rate = 6.375 Gbps Pattern = PRBS31 BER = 10-12 > 0.988 — — — UI Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 4 of 7) Symbol/ Description Conditions –C3 and –I3 –C4 and –I4 Unit Min Typ Max Min Typ Max

1–50 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Sinusoidal jitter tolerance (peak- to-peak) Jitter Frequency = 38.2 KHz Data rate = 6.375 Gbps Pattern = PRBS31 BER = 10-12 > 0.5 — — — UI Jitter Frequency = 3.82 MHz Data rate = 6.375 Gbps Pattern = PRBS31 BER = 10-12 > 0.05 — — — UI Jitter Frequency = 20 MHz Data rate = 6.375 Gbps Pattern = PRBS31 BER = 10-12 > 0.05 — — — UI SDI Transmitter Jitter Generation (12) Alignment jitter (peak-to-peak) Data rate = 1.485 Gbps (HD) Pattern = color bar Low-frequency roll-off = 100 KHz 0.2 — — 0.2 — — UI Data rate = 2.97 Gbps (3G) Pattern = color bar Low-frequency roll-off = 100 KHz 0.3 — — 0.3 — — UI SDI Receiver Jitter Tolerance (12) Sinusoidal jitter tolerance (peak- to-peak) Jitter frequency = 15 KHz Data rate = 2.97 Gbps (3G) Pattern = single line scramble color bar > 2 > 2 UI Jitter frequency = 100 KHz Data rate = 2.97 Gbps (3G) Pattern = single line scramble color bar > 0.3 > 0.3 UI Jitter frequency = 148.5 MHz Data rate = 2.97 Gbps (3G) Pattern = single line scramble color bar > 0.3 > 0.3 UI Sinusoidal jitter tolerance (peak- to-peak) Jitter frequency = 20 KHz Data rate = 1.485 Gbps (HD) pattern = 75% color bar > 1 > 1 UI Jitter frequency = 100 KHz Data rate = 1.485 Gbps (HD) Pattern = 75% color bar > 0.2 > 0.2 UI Jitter frequency = 148.5 MHz Data rate = 1.485 Gbps (HD) Pattern = 75% color bar > 0.2 > 0.2 UI SAS Transmit Jitter Generation (13) Total jitter at 1.5 Gbps (G1) Pattern = CJPAT — — 0.55 — — 0.55 UI Deterministic jitter at 1.5 Gbps (G1) Pattern = CJPAT — — 0.35 — — 0.35 UI Total jitter at 3.0 Gbps (G2) Pattern = CJPAT — — 0.55 — — 0.55 UI Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 5 of 7) Symbol/ Description Conditions –C3 and –I3 –C4 and –I4 Unit Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–51 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Deterministic jitter at 3.0 Gbps (G2) Pattern = CJPAT — — 0.35 — — 0.35 UI Total jitter at 6.0 Gbps (G3) Pattern = CJPAT — — 0.25 — — 0.25 UI Random jitter at 6.0 Gbps (G3) Pattern = CJPAT — — 0.15 — — 0.15 UI SAS Receiver Jitter Tolerance (13) Total jitter tolerance at 1.5 Gbps (G1) Pattern = CJPAT — — 0.65 — — 0.65 UI Deterministic jitter tolerance at 1.5 Gbps (G1) Pattern = CJPAT — — 0.35 — — 0.35 UI Sinusoidal jitter tolerance at 1.5 Gbps (G1) Jitter frequency = 900 KHz to 5 MHz Pattern = CJTPAT BER = 1E-12 > 0.1 > 0.1 UI CPRI Transmit Jitter Generation (14) Total jitter E.6.HV, E.12.HV Pattern = CJPAT Pattern = CJPAT Deterministic jitter E.6.HV, E.12.HV Pattern = CJPAT Pattern = CJPAT CPRI Receiver Jitter Tolerance (14) Total jitter tolerance E.6.HV, E.12.HV Pattern = CJPAT > 0.66 > 0.66 UI Deterministic jitter tolerance E.6.HV, E.12.HV Pattern = CJPAT > 0.4 > 0.4 UI Total jitter tolerance Pattern = CJPAT > 0.65 > 0.65 UI Deterministic jitter tolerance Pattern = CJPAT > 0.37 > 0.37 UI Combined deterministic and random jitter tolerance Pattern = CJPAT > 0.55 > 0.55 UI OBSAI Transmit Jitter Generation (15) Total jitter at 768 Mbps, 1536 Mbps, and 3072 Mbps REFCLK = 153.6 MHz Pattern CJPAT Deterministic jitter at 768 MBps,

1536 Mbps, and 3072 Mbps

REFCLK = 153.6 MHz Pattern CJPAT Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 6 of 7) Symbol/ Description Conditions –C3 and –I3 –C4 and –I4 Unit Min Typ Max Min Typ Max

1–52 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation OBSAI Receiver Jitter Tolerance (15) Deterministic jitter tolerance at

768 Mbps, 1536 Mbps, and

Pattern = CJPAT > 0.37 > 0.37 UI Combined deterministic and random jitter tolerance at 768 Mbps, 1536 Mbps, and 3072 Mbps Pattern = CJPAT > 0.55 > 0.55 UI Sinusoidal jitter tolerance at 768 Mbps Jitter frequency = 5.4 KHz Pattern = CJPAT > 8.5 > 8.5 UI Jitter frequency = 460 MHz to 20 MHz Pattern = CJPAT > 0.1 > 0.1 UI Sinusoidal jitter tolerance at Jitter frequency = 10.9 KHz Pattern = CJPAT > 8.5 > 8.5 UI Jitter frequency = 921.6 MHz to 20 MHz Pattern = CJPAT > 0.1 > 0.1 UI Sinusoidal jitter tolerance at Jitter frequency = 21.8 KHz Pattern = CJPAT > 8.5 > 8.5 UI Jitter frequency = 1843.2 MHz to Pattern = CJPAT > 0.1 > 0.1 UI Notes to Table 1–41: (1) Dedicated refclk pins were used to drive the input reference clocks. (2) The jitter numbers are valid for the stated conditions only. (3) The jitter numbers for SONET/SDH are compli ant to the GR-253-CORE Issue 3 Specification. (4) The jitter numbers for Fibre Ch annel are compliant to the FC-PI-4 Specification revision 6.10. (5) The Fibre Channel transmitter jitter generation numbers are compliant to the specification at the T inter operability point. (6) The Fibre Channel receiver jitte r tolerance numbers are compliant to the specification at the R interpretability point. (7) The jitter numbers for XAUI are compli ant to the IEEE802.3ae-2002 Specification. (8) The jitter numbers for PCIe are compli ant to the PCIe Base Specification 2.0. (9) Arria II GZ PCIe receivers are compliant to this specification provided the VTX-CM-DC-ACTIVEIDLE-DELTA of the upstream transmitter is less than 50 mV. (10) The jitter numbers for SRIO are compliant to the RapidIO Specification 1.3. (11) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification. (12) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M Specifications. (13) The jitter numbers for Serial Attached SCSI (SAS) are compliant to the SAS-2.1 Specification. (14) The jitter numbers for CPRI are compliant to the CPRI Specification V3.0. (15) The jitter numbers for OBSAI are compliant to the OBSAI RP3 Specification V4.1. Table 1–41. Transceiver Block Jitter Specifications for Arria II GZ Devices (Note 1), (2) (Part 7 of 7) Symbol/ Description Conditions –C3 and –I3 –C4 and –I4 Unit Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–53 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Core Performance Specifications for the Arria II Device Family This section describes the clock tree, phase-locked loop (PLL), digital signal processing (DSP), embedded memory, configuration, and JTAG specifications for Arria II GX and GZ devices. Clock Tree Specifications Table 1–42 lists the clock tree specifications for Arria II GX devices. Table 1–43 lists the clock tree specifications for Arria II GZ devices. PLL Specifications Table 1–44 lists the PLL specifications for Arria II GX devices. Table 1–42. Clock Tree Performance for Arria II GX Devices Clock Network Performance Unit I3, C4 C5,I5 C6 GCLK and RCLK 500 500 400 MHz PCLK 420 350 280 MHz Table 1–43. Clock Tree Performance for Arria II GZ Devices Clock Network Performance Unit –C3 and –I3 –C4 and –I4 GCLK and RCLK 700 500 MHz PCLK 500 450 MHz Table 1–44. PLL Specifications for Arria II GX Devices (Part 1 of 3) Symbol Description Min Typ Max Unit fIN Input clock frequency (from clock input pins residing in right/top/bottom banks) (–4 Speed Grade) 5 — 670 (1) MHz Input clock frequency (from clock input pins residing in right/top/bottom banks) (–5 Speed Grade) 5 — 622 (1) MHz Input clock frequency (from clock input pins residing in right/top/bottom banks) (–6 Speed Grade) 5 — 500 (1) MHz fINPFD Input frequency to the PFD 5 — 325 MHz fVCO PLL VCO operating Range (2) 600 — 1,400 MHz fINDUTY Input clock duty cycle 40 — 60 % fEINDUTY External feedback clock input duty cycle 40 — 60 % tINCCJ (3), (4) Input clock cycle-to-cycle jitter (Frequency 100 MHz) — — 0.15 UI (p–p) Input clock cycle-to-cycle jitter (Frequency 100 MHz) — — ±750 ps (p–p)

1–54 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation fOUT Output frequency for internal global or regional clock (–4 Speed Grade) — — 500 MHz Output frequency for internal global or regional clock (–5 Speed Grade) — — 500 MHz Output frequency for internal global or regional clock (–6 Speed Grade) — — 400 MHz fOUT_EXT Output frequency for external clock output (–4 Speed Grade) — — 670 (5) MHz Output frequency for external clock output (–5 Speed Grade) — — 622 (5) MHz Output frequency for external clock output (–6 Speed Grade) — — 500 (5) MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 % tOUTPJ_DC Dedicated clock output period jitter (fOUT  100 MHz) — — 300 ps (p–p) Dedicated clock output period jitter (fOUT  100 MHz) — — 30 mUI (p–p) tOUTCCJ_DC Dedicated clock output cycle-to-cycle jitter (fOUT 100 MHz) — — 300 ps (p–p) Dedicated clock output cycle-to-cycle jitter (fOUT 100 MHz) — — 30 mUI (p–p) fOUTPJ_IO Regular I/O clock output period jitter (fOUT 100 MHz) — — 650 ps (p–p) Regular I/O clock output period jitter (fOUT 100 MHz) — — 65 mUI (p–p) fOUTCCJ_IO Regular I/O clock output cycle-to-cycle jitter (fOUT 100 MHz) — — 650 ps (p–p) Regular I/O clock output cycle-to-cycle jitter (fOUT 100 MHz) — — 65 mUI (p–p) tCONFIGPLL Time required to reconfigure PLL scan chains — 3.5 — SCANCLK cycles tCONFIGPHASE Time required to reconfigure phase shift — 1 — SCANCLK cycles fSCANCLK SCANCLK frequency — — 100 MHz tLOCK Time required to lock from end of device configuration — — 1 ms tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) —— 1 m s fCL B W PLL closed-loop low bandwidth — 0.3 — MHz PLL closed-loop medium bandwidth — 1.5 — MHz PLL closed-loop high bandwidth — 4 — MHz t PLL_PSERR Accuracy of PLL phase shift — — ±50 ps tARESET Minimum pulse width on areset signal 10 — — ns Table 1–44. PLL Specifications for Arria II GX Devices (Part 2 of 3) Symbol Description Min Typ Max Unit

Chapter 1: Device Datasheet for Arria II Devices 1–55 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Table 1–45 lists the PLL specifications for Arria II GZ devices when operating in both the commercial junction temperature range (0° to 85°C) and the industrial junction temperature range (-40° to 100°C). tCASC_ OUTJITTER_ PERIOD_ DEDCLK (6), (7) Period Jitter for dedicated clock output in cascaded PLLs (FOUT  100 MHz) — — 425 ps (p-p) Period Jitter for dedicated clock output in cascaded PLLs (FOUT  100 MHz) — — 42.5 mUI (p-p) Notes to Table 1–44: (1) f IN is limited by the I/O fMAX. (2) The VCO frequency reported by the Qu artus II software in the PLL summary section of the compilation report takes into consideration the VCO post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the fVCO specification. (3) A high-input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean-clock source, which is less than 200 ps. (4) F REF is fIN/N when N = 1. (5) This specification is limited by the lower of the two: I/O fMAX or fOUT of the PLL. (6) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different measurement method and are available in Table 1–62 on page 1–70. (7) The cascaded PLL specification is only applicable with the following condition: a. Upstream PLL: 0.59 Mhz Upstream PLL BW < 1 MHz b. Downstream PLL: Downstream PLL BW > 2 MHz Table 1–44. PLL Specifications for Arria II GX Devices (Part 3 of 3) Symbol Description Min Typ Max Unit Table 1–45. PLL Specifications for Arria II GZ Devices (Part 1 of 2) Symbol Parameter Min Typ Max Unit fIN Input clock frequency (–3 speed grade) 5 — 717 (1) MHz Input clock frequency (–4 speed grade) 5 — 717 (1) MHz fINPFD Input frequency to the PFD 5 — 325 MHz fVCO PLL VCO operating range (–3 speed grade) 600 — 1,300 MHz PLL VCO operating range (–4 speed grade) 600 — 1,300 MHz tEINDUTY Input clock or external feedback clock input duty cycle 40 — 60 % fOUT Output frequency for internal global or regional clock (–3 speed grade) — — 700 (2) MHz Output frequency for internal global or regional clock (–4 speed grade) — — 500 (2) MHz fOUT_EXT Output frequency for external clock output (–3 speed grade) — — 717 (2) MHz Output frequency for external clock output (–4 speed grade) — — 717 (2) MHz tOUTDUTY Duty cycle for external clock output (when set to 50%) 45 50 55 % tFCOMP External feedback clock compensation time — — 10 ns tCONFIGPLL Time required to reconfigure scan chain — 3.5 — scanclk cycles tCONFIGPHASE Time required to reconfigure phase shift — 1 — scanclk cycles fSCANCLK scanclk frequency — — 100 MHz tLOCK Time required to lock from end-of-device configuration or de-assertion of areset —— 1 m s

1–56 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) —— 1 m s fCLBW PLL closed-loop low bandwidth — 0.3 — MHz PLL closed-loop medium bandwidth — 1.5 — MHz PLL closed-loop high bandwidth (7) —4 — M H z t PLL_PSERR Accuracy of PLL phase shift — — ±50 ps tARESET Minimum pulse width on the areset signal 10 — — ns tINCCJ (3), (4) Input clock cycle to cycle jitter (FREF ≥ 100 MHz) — — 0.15 UI (p-p) Input clock cycle to cycle jitter (FREF < 100 MHz) — — ±750 ps (p-p) tOUTPJ_DC (5) Period Jitter for dedicated clock output (FOUT ≥ 100 MHz) — — 175 ps (p-p) Period Jitter for dedicated clock output (FOUT < 100 MHz) — — 17.5 mUI (p-p) tOUTCCJ_DC (5) Cycle to Cycle Jitter for dedicated clock output (FOUT ≥ 100 MHz) — — 175 ps (p-p) Cycle to Cycle Jitter for dedicated clock output (FOUT < 100 MHz) — — 17.5 mUI (p-p) tOUTPJ_IO (5), (8) Period Jitter for clock output on regular I/O (FOUT ≥ 100 MHz) — — 600 ps (p-p) Period Jitter for clock output on regular I/O (FOUT < 100 MHz) — — 60 mUI (p-p) tOUTCCJ_IO (5), (8) Cycle to Cycle Jitter for clock output on regular I/O (FOUT ≥ 100 MHz) — — 600 ps (p-p) Cycle to Cycle Jitter for clock output on regular I/O (FOUT < 100 MHz) — — 60 mUI (p-p) tCASC_OUTPJ_DC (5), (6) Period Jitter for dedicated clock output in cascaded PLLs (FOUT ≥100MHz) — — 250 ps (p-p) Period Jitter for dedicated clock output in cascaded PLLs (FOUT < 100MHz) — — 25 mUI (p-p) fDRIFT Frequency drift after PFDENA is disabled for duration of 100 us — — ±10 % Notes to Table 1–45: (1) This specification is limited in the Qu artus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard. (2) This specification is limited by the lower of the two: I/O FMAX or FOUT of the PLL. (3) A high input jitter directly affects th e PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less than 120 ps. (4) F REF is fIN/N when N = 1. (5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps is applied. The external memory interface clock output jitter specifications use a different measurement method and are available in Table 1–64 on page 1–71. (6) The cascaded PLL specification is only applicable with the following condition: a. Upstream PLL: 0.59 Mhz  Upstream PLL BW < 1 MHz b. Downstream PLL: Downstream PLL BW > 2 MHz (7) High bandwidth PLL settings are not supported in external feedback mode. (8) External memory interface clock output jitter specifications use a different measurement method, which is available in Table 1–63 on page 1–71. Table 1–45. PLL Specifications for Arria II GZ Devices (Part 2 of 2) Symbol Parameter Min Typ Max Unit

Chapter 1: Device Datasheet for Arria II Devices 1–57 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum DSP Block Specifications Table 1–46 lists the DSP block performance specifications for Arria II GX devices. Table 1–47 lists the DSP block performance specifications for Arria II GZ devices. Table 1–46. DSP Block Performance Specifications for Arria II GX Devices (Note 1) Mode Resources Used Performance Unit Number of Multipliers C4 I3 C5,I5 C6 9 × 9-bit multiplier 1 380 310 300 250 MHz 12 × 12-bit multiplier 1 380 310 300 250 MHz 18 × 18-bit multiplier 1 380 310 300 250 MHz 36 × 36-bit multiplier 1 350 270 270 220 MHz 18 × 36-bit high-precision multiplier adder mode 1 350 270 270 220 MHz 18 × 18-bit multiply accumulator 4 380 310 300 250 MHz 18 × 18-bit multiply adder 4 380 310 300 250 MHz 18 × 18-bit multiply adder-signed full precision 2 380 310 300 250 MHz 18 × 18-bit multiply adder with loopback (2) 2 275 220 220 180 MHz 36-bit shift (32-bit data) 1 350 270 270 220 MHz Double mode 1 350 270 270 220 MHz Notes to Table 1–46: (1) Maximum is for a full y-pipelined block with Round and Saturation disabled. (2) Maximum is for loopback input registers disabled, Round and Saturation disabled, pipeline and output registers enabled. Table 1–47. DSP Block Performance Specifications for Arria II GZ Devices (Note 1) (Part 1 of 2) Mode Resources Used Performance Unit Number of Multipliers –3 –4 9 × 9-bit multiplier 1 460 400 MHz 12 × 12-bit multiplier 1 500 440 MHz 18 × 18-bit multiplier 1 550 480 MHz 36 × 36-bit multiplier 1 440 380 MHz 18 × 18-bit multiply accumulator 4 440 380 MHz 18 × 18-bit multiply adder 4 470 410 MHz 18 × 18-bit multiply adder-signed full precision 2 450 390 MHz 18 × 18-bit multiply adder with loopback (2) 2 350 310 MHz 36-bit shift (32-bit data) 1 440 380 MHz

1–58 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Embedded Memory Block Specifications Table 1–48 lists the embedded memory block specifications for Arria II GX devices. Double mode 1 440 380 MHz Notes to Table 1–47: (1) Maximum is for fully pipelined block with Round and Saturation disabled. (2) Maximum for loopback in put registers disabled, Round and Saturation disabled, and pipeline and output registers enabled. Table 1–47. DSP Block Performance Specifications for Arria II GZ Devices (Note 1) (Part 2 of 2) Mode Resources Used Performance Unit Number of Multipliers –3 –4 Table 1–48. Embedded Memory Block Performance Specifications for Arria II GX Devices Memory Mode Resources Used Performance Unit ALUTs Embedded Memory I3 C4 C5,I5 C6 Memory Logic Array Block (MLAB) Single port 64 × 10 0 1 450 500 450 378 MHz Simple dual-port 32 × 20 single clock 0 1 270 500 450 378 MHz Simple dual-port 64 × 10 single clock 0 1 428 500 450 378 MHz M9K Block Single-port 256 × 36 0 1 360 400 360 310 MHz Single-port 256 × 36, with the read-during-write option set to Old Data 0 1 250 280 250 210 MHz Simple dual-port 256 × 36 single CLK 0 1 360 400 360 310 MHz Single-port 256 × 36 single CLK, with the read-during-write option set to Old Data 0 1 250 280 250 210 MHz True dual port 512 × 18 single CLK 0 1 360 400 360 310 MHz True dual-port 512 × 18 single CLK, with the read-during-write option set to Old Data 0 1 250 280 250 210 MHz Min Pulse Width (clock high time) — — 900 850 950 1130 ps Min Pulse Width (clock low time) — — 730 690 770 920 ps

Chapter 1: Device Datasheet for Arria II Devices 1–59 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Table 1–49 lists the embedded memory block specifications for Arria II GZ devices. Table 1–49. Embedded Memory Block Performance Specifications for Arria II GZ Devices (Note 1) Memory Mode Resources Used Performance Unit ALUTs TriMatrix Memory C3 I3 C4 I4 MLAB (2) Single port 64 × 10 0 1 500 500 450 450 MHz Simple dual-port 32 × 20 0 1 500 500 450 450 MHz Simple dual-port 64 × 10 0 1 500 500 450 450 MHz ROM 64 × 10 0 1 500 500 450 450 MHz ROM 32 × 20 0 1 500 500 450 450 MHz M9K Block (2) Single-port 256 × 36 0 1 540 540 475 475 MHz Simple dual-port 256 × 36 0 1 490 490 420 420 MHz Simple dual-port 256 × 36, with the read-during-write option set to Old Data 0 1 340 340 300 300 MHz True dual port 512 × 18 0 1 430 430 370 370 MHz True dual-port 512 × 18, with the read-during-write option set to Old Data 0 1 335 335 290 290 MHz ROM 1 Port 0 1 540 540 475 475 MHz ROM 2 Port 0 1 540 540 475 475 MHz Min Pulse Width (clock high time) — — 800 800 850 850 ps Min Pulse Width (clock low time) — — 625 625 690 690 ps M144K Block (2) Single-port 2K × 72 0 1 440 400 380 350 MHz Simple dual-port 2K × 72 0 1 435 375 385 325 MHz Simple dual-port 2K × 72, with the read-during-write option set to Old Data 0 1 240 225 205 200 MHz Simple dual-port 2K × 64 (with ECC) 0 1 300 295 255 250 MHz True dual-port 4K × 36 0 1 375 350 330 310 MHz True dual-port 4K × 36, with the read-during-write option set to Old Data 0 1 230 225 205 200 MHz ROM 1 Port 0 1 500 450 435 420 MHz ROM 2 Port 0 1 465 425 400 400 MHz Min Pulse Width (clock high time) — — 755 860 860 950 ps Min Pulse Width (clock low time) — — 625 690 690 690 ps Notes to Table 1–48: (1) To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle. Use the Quartus II software to report timing for this and other memory block clocking schemes. (2) When you use the error detection CRC f eature, there is no degradation in FMAX.

1–60 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Configuration Table 1–50 lists the configuration mode specifications for Arria II GX and GZ devices. JTAG Specifications Table 1–51 lists the JTAG timing parameters and values for Arria II GX and GZ devices. Chip-Wide Reset (Dev_CLRn) Specifications Table 1–52 lists the specifications for the chip-wide reset (Dev_CLRn) for Arria II GX and GZ devices. Table 1–50. Configuration Mode Specifications for Arria II Devices Programming Mode DCLK Frequency Unit Min Typ Max Passive serial — — 125 MHz Fast passive parallel — — 125 MHz Fast active serial (fast clock) 17 26 40 MHz Fast active serial (slow clock) 8.5 13 20 MHz Remote update only in fast AS mode — — 10 MHz Table 1–51. JTAG Timing Parameters and Values for Arria II Devices Symbol Description Min Max Unit t JCP TCK clock period 30 — ns tJCH TCK clock high time 14 — ns tJCL TCK clock low time 14 — ns tJPSU (TDI) TDI JTAG port setup time 1 — ns tJPSU (TMS) TMS JTAG port setup time 3 — ns tJPH JTAG port hold time 5 — ns tJPCO JTAG port clock to output — 11 ns tJPZX JTAG port high impedance to valid output — 14 ns tJPXZ JTAG port valid output to high impedance — 14 ns Table 1–52. Chip-Wide Reset (Dev_CLRn) Specifications for Arria II Devices Description Min Typ Max Unit Dev_CLRn 500 — — s

Chapter 1: Device Datasheet for Arria II Devices 1–61 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Periphery Performance This section describes periphery performance, including high-speed I/O, external memory interface, and IOE programmable delay. I/O performance supports several system interfaces, for example the high-speed I/O interface, external memory interface, and the PCI/PCI-X bus interface. I/O using SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM interfacing speed with typical DDR2 SDRAM memory interface setup. I/O using general purpose I/O (GPIO) standards such as 3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 200 MHz interfacing frequency with 10pF load. 1 Actual achievable frequency depends on design- and system-specific factors. You should perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system. High-Speed I/O Specification Table 1–53 lists the high-speed I/O timing for Arria II GX devices. Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 1 of 4) Symbol Conditions I3 C4 C5,I5 C6 Unit Min Max Min Max Min Max Min Max Clock fHSCLK_IN (input clock frequency)–Row I/O Clock boost factor, W = 1 to 40 (1) 5 670 5 670 5 622 5 500 MHz fHSCLK_IN (input clock frequency)– Column I/O Clock boost factor, W = 1 to 40 (1) 5 500 5 500 5 472.5 5 472.5 MHz fHSCLK_OUT (output clock frequency)–Row I/O — 5 670 5 670 5 622 5 500 MHz f HSCLK_OUT (output clock frequency)– Column I/O — 5 500 5 500 5 472.5 5 472.5 MHz

1–62 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Transmitter fHSDR_TX (true LVDS output data rate) SERDES factor, J = 3 to 10 (using dedicated SERDES) 150 1250 (2) 150 1250 (2) 150 1050 (2) 150 840 Mbps SERDES factor, J = 4 to 10 (using logic elements as SERDES) (3) 945 (3) 945 (3) 840 (3) 740 Mbps SERDES factor, J = 2 (using DDR registers) and J = 1 (using SDR register) f HSDR_TX_E3R (emulated LVDS_E_3R output data rate) (7) SERDES factor, J = 4 to 10 (3) 945 (3) 945 (3) 840 (3) 740 Mbps Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 2 of 4) Symbol Conditions I3 C4 C5,I5 C6 Unit Min Max Min Max Min Max Min Max

Chapter 1: Device Datasheet for Arria II Devices 1–63 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum tTX_JITTER (4) True LVDS with dedicated SERDES (data rate 600–1,250 Mbps) — 175 — 175 — 225 — 300 ps True LVDS with dedicated SERDES (data rate < 600 Mbps) — 0.105 — 0.105 — 0.135 — 0.18 UI True LVDS and emulated LVDS_E_3R with logic elements as SERDES (data rate 600 – 945 Mbps) — 260 — 260 — 300 — 350 ps True LVDS and emulated LVDS_E_3R with logic elements as SERDES (data rate < 600 Mbps) tTX_DCD True LVDS and emulated LVDS_E_3R 45 55 45 55 45 55 45 55 % tRISE and tFALL True LVDS and emulated LVDS_E_3R — 200 — 200 — 225 — 250 ps TCCS True LVDS (5) — 150 — 150 — 175 — 200 ps Emulated LVDS_E_3R — 200 — 200 — 250 — 300 ps Receiver (6) True differential I/O standards - fHSDRDPA (data rate) SERDES factor J = 3 to 10 150 1250 150 1250 150 1050 150 840 Mbps Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 3 of 4) Symbol Conditions I3 C4 C5,I5 C6 Unit Min Max Min Max Min Max Min Max

1–64 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–54 lists the high-speed I/O timing for Arria II GZ devices. fHSDR (data rate) SERDES factor J = 3 to 10 (3) 945 (7) (3) 945 (7) (3) 740 (7) (3) 640 (7) Mbps SERDES factor J = 2 (using DDR registers) SERDES factor J = 1 (using SDR registers) Soft-CDR PPM tolerance Soft-CDR mode — 300 — 300 — 300 — 300 PPM DPA run length DPA mode — 10,000 — 10,000 — 10,000 — 10,000 UI Sampling window (SW) Non-DPA mode (5) — 300 — 300 — 350 — 400 ps Notes to Table 1–53: (1) f HSCLK_IN = fHSDR / W. Use W to determine the supported selection of input reference clock frequencies for the desired data rate. (2) Applicable for interfacing wi th DPA receivers only. For interfacing with non-DPA receivers, you must calculate the leftover timing margin in the receiver by performing link timing closure analysis. For Arria II GX transmitter to Arria II GX non-DPA receiver, the maximum supported data rate is 945 Mbps. For data rates above 840 Mbps, perform PCB trace compensation by adjusting the PCB trace length for LVDS channels to improve channel-to-channel skews. (3) The minimum and maximum specif ication depends on the clock source (for example, PLL and clock pin) and the clock routing resource you use (global, regional, or local). The I/O differential buffer and input register do not have a minimum toggle rate. (4) The specification is only applicab le under the influence of core noise. (5) Applicable for true LVDS using dedicated SERDES only. (6) Dedicated SERDES and DPA features are only available on the right banks. (7) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and the receiver sampling margin to determine the leftover timing margin. Table 1–53. High-Speed I/O Specifications for Arria II GX Devices (Part 4 of 4) Symbol Conditions I3 C4 C5,I5 C6 Unit Min Max Min Max Min Max Min Max Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 1 of 3) Symbol Conditions C3, I3 C4, I4 Unit Min Typ Max Min Typ Max Clock fHSCLK_in (input clock frequency) true differential I/O standards Clock boost factor W = 1 to 40 (3) 5 — 717 5 — 717 MHz f HSCLK_in (input clock frequency) single ended I/O standards (9) Clock boost factor W = 1 to 40 (3) 5 — 717 5 — 717 MHz fHSCLK_in (input clock frequency) single ended I/O standards (10) Clock boost factor W = 1 to 40 (3) 5 — 420 5 — 420 MHz

Chapter 1: Device Datasheet for Arria II Devices 1–65 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum fHSCLK_OUT (output clock frequency) — 5 — 717 (7) 5 — 717 (7) MHz Transmitter fHSDR (true LVDS output data rate) SERDES factor, J = 3 to 10 (using dedicated SERDES) (8) (4) — 1250 (4) — 1250 Mbps SERDES factor J = 2, (using DDR registers) (4) — (5) (4) — (5) Mbps SERDES factor J = 1, (uses an SDR register) fHSDR (emulated LVDS_E_3R output data rate) (5) SERDES factor J = 4 to 10 (4) — 1152 (4) — 800 Mbps fHSDR (emulated LVDS_E_1R output data rate) (4) —2 0 0 (4) — 200 Mbps tx Jitter Total jitter for data rate, 600 Mbps to

1.6 Gbps

— —1 6 0— —1 6 0 p s Total jitter for data rate, < 600 Mbps — —0 . 1— —0 . 1U I tx Jitter - emulated differential I/O standards with three external output resistor network Total jitter for data rate, 600 Mbps to

1.25 Gbps

— —3 0 0— —3 2 5 p s Total jitter for data rate < 600 Mbps — — 0.2 — — 0.25 UI tx Jitter - emulated differential I/O standards with one external output resistor network tDUTY TX output clock duty cycle for both True and emulated differential I/O standards 45 50 55 45 50 55 % Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 2 of 3) Symbol Conditions C3, I3 C4, I4 Unit Min Typ Max Min Typ Max

1–66 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–55 lists DPA lock time specifications for Arria II GX and GZ devices. tRISE & tFALL True differential I/O standards — —2 0 0— —2 0 0 p s Emulated differential I/O standards with three external output resistor networks — —2 5 0— —3 0 0 p s Emulated differential I/O standards with one external output resistor — —5 0 0— —5 0 0 p s TCCS True LVDS — — 100 — — 100 ps Emulated LVDS_E_3R — —2 5 0— —2 5 0 p s Receiver True differential I/O standards - fHSDRDPA (data rate) SERDES factor J = 3 to 10 150 — 1250 150 — 1250 Mbps fHSDR (data rate) SERDES factor SERDES factor J = 2, uses DDR registers (4) — (5) (4) — (5) Mbps SERDES factor J = 1, uses an SDR register (4) — (5) (4) — (5) Mbps DPA run length DPA mode — — 10000 — — 10000 UI Soft-CDR PPM tolerance Soft-CDR mode — — 300 — — 300 ± PPM Sampling Window (SW) Non-DPA mode — — 300 — — 300 ps Notes to Table 1–54: (1) When J = 3 to 10, use the SERDES block. (2) When J = 1 or 2, bypass the SERDES block. (3) Clock Boost Factor (W) is the ratio between input data rate to the input clock rate. (4) The minimum specification depends on th e clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or local) that you use. The I/O differential buffer and input register do not have a minimum toggle rate. (5) You must calculate the leftover timing margin in the receiver by performing link timing closure analysis. You must consider the board skew margin, transmitter channel-to-channel skew, and receiver sampling margin to determine leftover timing margin. (6) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. You must consider the board skew margin, transmitter delay margin, and the receiver sampling margin to determine the maximum data rate supported. (7) This is achieved by using th e LVDS and DPA clock network. (8) If the receiver with DPA enabled an d transmitter are using shared PLLs, the minimum data rate is 150 Mbps. (9) This only applies to DPA and soft-CDR modes. (10) This only applies to LVDS source synchronous mode. Table 1–54. High-Speed I/O Specifications for Arria II GZ Devices (Note 1), (2), (10) (Part 3 of 3) Symbol Conditions C3, I3 C4, I4 Unit Min Typ Max Min Typ Max

Chapter 1: Device Datasheet for Arria II Devices 1–67 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Figure 1–5 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for Arria II GZ devices at a data rate less than 1.25 Gbps and all the Arria II GX devices. Table 1–55. DPA Lock Time Specifications for Arria II Devices (Note 1), (2), (3) Standard Training Pattern Number of Data Transitions in One Repetition of the Training Pattern Number of Repetitions per

256 Data

Transitions (4) Maximum SPI-4 00000000001111111111 2 128 640 data transitions Parallel Rapid I/O 00001111 2 128 640 data transitions 10010000 4 64 640 data transitions Miscellaneous 10101010 8 32 640 data transitions 01010101 8 32 640 data transitions Notes to Table 1–55: (1) The DPA lock time is for one channel. (2) One data transition is defined as a 0-to-1 or 1-to-0 transition. (3) The DPA lock time stated in the table applie s to both commercial and industrial grade. (4) This is the number of repetition s for the stated training pattern to achieve the 256 data transitions. Figure 1–5. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for All Arria II GX Devices and for Arria II GZ Devices at a Data Rate less than 1.25 Gbps 0.1 P-P baud/1667 20,000,000 Jitter Frequency (Hz) Sinusoidal Jitter Amplitude (UI) 20db/dec

1–68 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Figure 1–6 shows the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for Arria II GZ devices at 1.25 Gbps data rate. Table 1–56 lists the LVDS soft-CDR/DPA sinusoidal jitter tolerance specification for Arria II GZ devices at 1.25 Gbps data rate. External Memory Interface Specifications f For the maximum clock rate supported for Arria II GX and GZ device family, refer to the External Memory Interface Spec Estimator page on the Altera website. Table 1–57 lists the external memory interface specifications for Arria II GX devices. Figure 1–6. LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specification for Arria II GZ Devices at a 1.25 Gbps Data Rate Jitter Frequency (Hz) Sinusoidal Jitter Amplitude (UI) 8.5 0.35 0.1 Table 1–56. LVDS Soft-CDR/DPA Sinusoidal Jitter Mask Values for Arria II GZ Devices at

1.25 Gbps Data Rate

Jitter Frequency (Hz) Sinusoidal Jitter (UI) F1 10,000 25.000 F2 17,565 25.000 F3 1,493,000 0.350 F4 50,000,000 0.350 Table 1–57. External Memory Interface Specifications for Arria II GX Devices (Part 1 of 2) Frequency Mode Frequency Range (MHz) Resolution (°) DQS Delay Buffer Mode (1) Number of Delay ChainsC4 I3, C5, I5 C6 0 90-140 90-130 90-110 22.5 Low 16 1 110-180 110-170 110-150 30 Low 12 2 140-220 140-210 140-180 36 Low 10 3 170-270 170-260 170-220 45 Low 8 4 220-340 220-310 220-270 30 High 12

Chapter 1: Device Datasheet for Arria II Devices 1–69 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Table 1–58 lists the DLL frequency range specifications for Arria II GZ devices. Table 1–59 lists the DQS phase offset delay per stage for Arria II GX devices. 5 270-410 270-380 270-320 36 High 10 6 320-450 320-410 320-370 45 High 8 Note to Table 1–57: (1) Low indicates a 6-bit DQS delay setting; high indicates a 5-bit DQS delay setting. Table 1–57. External Memory Interface Specifications for Arria II GX Devices (Part 2 of 2) Frequency Mode Frequency Range (MHz) Resolution (°) DQS Delay Buffer Mode (1) Number of Delay ChainsC4 I3, C5, I5 C6 Table 1–58. DLL Frequency Range Specifications for Arria II GZ Devices Frequency Mode Frequency Range (MHz) Available Phase Shift DQS Delay Buffer Mode (1) Number of Delay Chains–3 –4 0 90-130 90-120 22.5°, 45°, 67.5°, 90° Low 16 1 120-170 120-160 30°, 60°, 90°, 120° Low 12 2 150-210 150-200 36°, 72°, 108°, 144° Low 10 3 180-260 180-240 45°, 90°,135°, 180° Low 8 4 240-320 240-290 30°, 60°, 90°, 120° High 12 5 290-380 290-360 36°, 72°, 108°, 144° High 10 6 360-450 360-450 45°, 90°, 135°, 180° High 8 7 470-630 470-590 60°, 120°, 180°, 240° High 6 Note to Table 1–58: (1) Low indicates a 6-bit DQS delay setting; high indicates a 5-bit DQS delay setting. Table 1–59. DQS Phase Offset Delay Per Setting for Arria II GX Devices (Note 1), (2), (3) Speed Grade Min Max Unit C4 7.0 13.0 ps I3, C5, I5 7.0 15.0 ps C6 8.5 18.0 ps Notes to Table 1–59: (1) The valid settings for phase offset ar e -64 to +63 for frequency modes 0 to 3 and -32 to +31 for frequency modes 4 to 5. (2) The typical value equals the averag e of the minimum and maximum values. (3) The delay settings are linear.

1–70 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Table 1–60 lists the DQS phase shift error for Arria II GX devices. Table 1–61 lists the DQS phase shift error for Arria II GZ devices. Table 1–62 lists the memory output clock jitter specifications for Arria II GX devices. Table 1–60. DQS Phase Shift Error Specification for DLL-Delayed Clock (t DQS_PSERR) for Arria II GX Devices (Note 1) Number of DQS Delay Buffer C4 I3, C5, I5 C6 Unit 1 2 63 03 6 p s 2 5 26 07 2 p s 3 78 90 108 ps 4 104 120 144 ps Note to Table 1–60: (1) This error specificat ion is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a C4 speed grade is ± 78 ps or ± 39 ps. Table 1–61. DQS Phase Shift Error Specification for DLL-Delayed Clock (t DQS_PSERR) for Arria II GZ Devices (Note 1) Number of DQS Delay Buffer –3 –4 Unit 12 8 3 0 p s 25 6 6 0 p s 38 4 9 0 p s 4 112 120 ps Note to Table 1–61: (1) This error specificat ion is the absolute maximum and minimum error. For example, skew on three DQS delay buffers in a 3 speed grade is ± 84 ps or ± 42 ps. Table 1–62. Memory Output Clock Jitter Specification for Arria II GX Devices (Note 1), (2), (3) Parameter Clock Network Symbol –4 –5 –6 Unit Min Max Min Max Min Max Clock period jitter Global t JIT(per) -100 100 -125 125 -125 125 ps Cycle-to-cycle period jitter Global t JIT(cc) -200 200 -250 250 -250 250 ps Duty cycle jitter Global t JIT(duty) -100 100 -125 125 -125 125 ps Notes to Table 1–62: (1) The memory output clock jitt er measurements are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard. (2) The clock jitter specification ap plies to memory output clock pins generated using DDIO circuits clocked by a PLL output routed on a global clock network. (3) The memory output clock jitter stated in Table 1–62 is applicable when an input jitter of 30 ps is applied.

Chapter 1: Device Datasheet for Arria II Devices 1–71 Switching Characteristics December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Table 1–63 lists the memory output clock jitter specifications for Arria II GZ devices. Duty Cycle Distortion (DCD) Specifications Table 1–64 lists the worst-case DCD specifications for Arria II GX devices. Table 1–65 lists the worst-case DCD specifications for Arria II GZ devices. Table 1–63. Memory Output Clock Jitter Specification for Arria II GZ Devices (Note 1), (2), (3) Parameter Clock Network Symbol –3 –4 Unit Min Max Min Max Clock period jitter Regional t JIT(per) -55 55 -55 55 ps Cycle-to-cycle period jitter Regional t JIT(cc) -110 110 -110 110 ps Duty cycle jitter Regional t JIT(duty) -82.5 82.5 -82.5 82.5 ps Clock period jitter Global t JIT(per) -82.5 82.5 -82.5 82.5 ps Cycle-to-cycle period jitter Global t JIT(cc) -165 165 -165 165 ps Duty cycle jitter Global t JIT(duty) -90 90 -90 90 ps Notes to Table 1–63: (1) The memory output clock jitter measure ments are for 200 consecutive clock cycles, as specified in the JEDEC DDR2/DDR3 SDRAM standard. (2) The clock jitter specification ap plies to memory output clock pins generated using differential signal-splitter and DDIO circuits clocked by a PLL output routed on a regional or global clock network as specified. Altera recommends using regional clock networks whenever possible. (3) The memory output clock jitter stated in Table 1–63 is applicable when an input jitter of 30 ps is applied. Table 1–64. Duty Cycle Distortion on I/O Pins for Arria II GX Devices (Note 1) Symbol C4 I3, C5, I5 C6 Unit Min Max Min Max Min Max Output Duty Cycle 45 55 45 55 45 55 % Note to Table 1–64: (1) The DCD specification ap plies to clock outputs from the PLL, global clock tree, IOE driving dedicated, and general purpose I/O pins. Table 1–65. Duty Cycle Distortion on I/O Pins for Arria II GZ Devices (Note 1) Symbol C3, I3 C4, I4 Unit Min Max Min Max Output Duty Cycle 45 55 45 55 % Note to Table 1–65: (1) The DCD specification applies to clo ck outputs from the PLL, global clock tree, IOE driving dedicated, and general purpose I/O pins.

1–72 Chapter 1: Device Datasheet for Arria II Devices Switching Characteristics Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation IOE Programmable Delay Table 1–66 lists the delay associated with each supported IOE programmable delay chain for Arria II GX devices. Table 1–67 lists the IOE programmable delay settings for Arria II GZ devices. Table 1–66. IOE Programmable Delay for Arria II GX Devices Parameter Available Settings (1) Minimum Offset (2) Maximum Offset UnitFast Model Slow Model I3 C4 I5 I3 C4 C5 I5 C6 Output enable pin delay Delay from output register to output pin Input delay from pin to internal cell Input delay from pin to input register DQS bus to input register delay Notes to Table 1–66: (1) The available setting for every delay chai n starts with zero and ends with the specified maximum number of settings. (2) The minimum offset represented in th e table does not include intrinsic delay. Table 1–67. IOE Programmable Delay for Arria II GZ Devices Parameter Available Settings (1) Minimum Offset (2) Maximum Offset UnitFast Model Slow Model Industrial Commercial C3 I3 C4 I4 Notes to Table 1–67: (1) You can set this value in th e Quartus II software by selecting D1, D2, D3, D4, D5, and D6 in the Assignment Name column. (2) Minimum offset does not include the intrinsic delay.

Chapter 1: Device Datasheet for Arria II Devices 1–73 I/O Timing December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum I/O Timing Altera offers two ways to determine I/O timing: ■ Using the Microsoft Excel-based I/O Timing. ■ Using the Quartus II Timing Analyzer. The Microsoft Excel-based I/O Timing provides pin timing performance for each device density and speed grade. The data is typically used prior to designing the FPGA to get an estimate of the timing budget as part of the link timing analysis. The Quartus II timing analyzer provides a more accurate and precise I/O timing data based on the specifics of the design after place-and-route is complete. f The Microsoft Excel-based I/O Timing spreadsheet is downloadable from the Literature: Arria II Devices web page.

1–74 Chapter 1: Device Datasheet for Arria II Devices Glossary Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation Glossary Table 1–68 lists the glossary for this chapter. Table 1–68. Glossary (Part 1 of 4) Letter Subject Definitions D Differential I/O Standards Receiver Input Waveforms Transmitter Output Waveforms F fHSCLK Left/Right PLL input clock frequency. fHSDR High-speed I/O block: Maximum/minimum LVDS data transfer rate (fHSDR = 1/TUI), non-DPA. fHSDRDPA High-speed I/O block: Maximum/minimum LVDS data transfer rate (fHSDRDPA = 1/TUI), DPA. Single-Ended Waveform Differential Waveform Positive Channel (p) = VIH Negative Channel (n) = VIL Ground VID VID VID p − n = 0 V VCM Single-Ended Waveform Differential Waveform Positive Channel (p) = VOH Negative Channel (n) = VOL Ground VOD VOD VOD p − n = 0 V VCM

Chapter 1: Device Datasheet for Arria II Devices 1–75 Glossary December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum J J High-speed I/O block: Deserialization factor (width of parallel data bus). JTAG Timing Specifications JTAG Timing Specifications: P PLL Specifications PLL Specification parameters: Diagram of PLL Specifications (1) Notes: (1) CoreClock can only be fed by dedica ted clock input pins or PLL outputs. (2) This is the VCO post-scale counter K. R RL Receiver differential input discrete resistor (external to the Arria II device). Table 1–68. Glossary (Part 2 of 4) Letter Subject Definitions TDO TCK tJPZX tJPCO tJPH tJPXZ tJCP tJPSU t JCL tJCH TDI TMS Core Clock External FeedbackReconfigurable in User Mode Key CLK N M /KPFD Switchover VCOCP LF CLKOUT Pins GCLK RCLK fINPFDfIN fVCO fOUT fOUT_EXT K (2) Counters C0..C9

1–76 Chapter 1: Device Datasheet for Arria II Devices Glossary Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation S SW (sampling window) The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window: Timing Diagram Single-ended Voltage Referenced I/O Standard The JEDEC standard for SSTL and HSTL I/O standards define both the AC and DC input signal values. The AC values indicate the voltage levels at which the receiver must meet its timing specifications. The DC values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. After the receiver input has crossed the AC value, the receiver changes to the new logic state. The new logic state is then maintained as long as the input stays beyond the AC threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform ringing: Single-Ended Voltage Referenced I/O Standard T t C High-speed receiver and transmitter input and output clock period. TCCS (channel-to- channel- skew) The timing difference between the fastest and slowest output edges, including t CO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement (refer to the Timing Diagram figure under S in this table). tDUTY High-speed I/O block: Duty cycle on the high-speed transmitter output clock. Timing Unit Interval (TUI) The timing budget allowed for skew, propagation delays, and data sampling window. (TUI = 1/(Receiver Input Clock Frequency Multiplication Factor) = tC/w) tFALL Signal high-to-low transition time (80-20%) tINCCJ Cycle-to-cycle jitter tolerance on the PLL clock input. tOUTPJ_IO Period jitter on the general purpose I/O driven by a PLL. tOUTPJ_DC Period jitter on the dedicated clock output driven by a PLL. tRISE Signal low-to-high transition time (20-80%). Table 1–68. Glossary (Part 3 of 4) Letter Subject Definitions Bit Time 0.5 x TCCS RSKM Sampling Window (SW) RSKM 0.5 x TCCS VIH(AC) VIH(DC) VREF VIL(DC) VIL(AC) VOH VOL VCCIO VSS

Chapter 1: Device Datasheet for Arria II Devices 1–77 Document Revision History December 2013 Altera Corporation Arria II Device Ha ndbook Volume 3: Device Datasheet and Addendum Document Revision History Table 1–69 lists the revision history for this chapter. V VCM(DC) DC common mode input voltage. VICM Input common mode voltage: The common mode of the differential signal at the receiver. VID Input differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the receiver. VDIF(AC) AC differential input voltage: Minimum AC input differential voltage required for switching. VDIF(DC) DC differential input voltage: Minimum DC input differential voltage required for switching. VIH Voltage input high: The minimum positive voltage applied to the input which is accepted by the device as a logic high. VIH(AC) High-level AC input voltage. VIH(DC) High-level DC input voltage. VIL Voltage input low: The maximum positive voltage applied to the input which is accepted by the device as a logic low. VIL(AC) Low-level AC input voltage. VIL(DC) Low-level DC input voltage. VOCM Output common mode voltage: The common mode of the differential signal at the transmitter. VOD Output differential voltage swing: The difference in voltage between the positive and complementary conductors of a differential transmission at the transmitter. Z W High-speed I/O block: The clock boost factor. Table 1–68. Glossary (Part 4 of 4) Letter Subject Definitions Table 1–69. Document Revision History (Part 1 of 2) Date Version Changes December 2013 4.4 Updated Table 1–34 and Table 1–35. July 2012 4.3 ■ Updated the VCCH_GXBL/R operating conditions in Table 1–6. ■ Finalized Arria II GZ information in Table 1–20. ■ Added BLVDS specification in Table 1–32 and Table 1–33. ■ Updated input and output waveforms in Table 1–68. December 2011 4.2 ■ Updated Table 1–32, Table 1–33, Table 1–34, Table 1–35, Table 1–40, Table 1–41, Table 1–54, and Table 1–67. ■ Minor text edits. June 2011 4.1 ■ Added Table 1–60. ■ Updated Table 1–32, Table 1–33, Table 1–38, Table 1–41, and Table 1–61. ■ Updated the “Switching Characteristics” section introduction. ■ Minor text edits.

1–78 Chapter 1: Device Datasheet for Arria II Devices Document Revision History Arria II Device Handbook Volume 3: Device Datasheet and Addendum December 2013 Altera Corporation December 2010 4.0 ■ Added Arria II GZ information. ■ Added Table 1–61 with Arria II GX information. ■ Updated Table 1–1, Table 1–2, Table 1–5, Table 1–6, Table 1–7, Table 1–11, Table 1–35, Table 1–37, Table 1–40, Table 1–42, Table 1–44, Table 1–45, Table 1–57, Table 1–61, and Table 1–63. ■ Updated Figure 1–5. ■ Updated for the Quartus II version 10.0 release. ■ Updated the first paragraph for searchability. ■ Minor text edits. July 2010 3.0 ■ Updated Table 1–1, Table 1–4, Table1–16, Table 1–19, Table 1–21, Table 1–23, Table 1–25, Table 1–26, Table 1–30, and Table 1–35 ■ Added Table 1–27 and Table 1–29. ■ Added I3 speed grade information to Table 1–19, Table 1–21, Table 1–22, Table 1–24, Table 1–25, Table 1–30, Table 1–32, Table 1–33, Table 1–34, and Table 1–35. ■ Updated the “Operating Conditions” section. ■ Removed “Preliminary” from Table 1–19, Table 1–21, Table 1–22, Table 1–23, Table 1–24, Table 1–25, Table 1–26, Table 1–28, Table 1–30, Table 1–32, Table 1–33, Table 1–34, and Figure 1–4. ■ Minor text edits. March 2010 2.3 Updated for the Quartus II version 9.1 SP2 release: ■ Updated Table 1–3, Table 1–7, Table1–19, Table 1–21, Table 1–22, Table 1–24, Table 1–25 and Table 1–33. ■ Updated “Recommended Operating Conditions” section. ■ Minor text edits. February 2010 2.2 Updated Table 1–19. February 2010 2.1 Updated for Arria II GX v9.1 SP1 release: ■ Updated Table 1–19, Table 1–23, Table 1–28, Table 1–30, and Table 1–33. ■ Added Figure 1–5. ■ Minor text edits. November 2009 2.0 Updated for Arria II GX v9.1 release: ■ Updated Table 1–1, Table 1–4, Table1–13, Table 1–14, Table 1–19, Table 1–15, Table 1–22, Table 1–24, and Table 1–28. ■ Added Table 1–6 and Table 1–33. ■ Added “Bus Hold” on page 1–5. ■ Added “IOE Programmable Delay” section. ■ Minor text edit. June 2009 1.2 ■ Updated Table 1–1, Table 1–3, Table 1–7, Table 1–8, Table 1–18, Table 1–23, Table 1–25, Table 1–26, Table 1–29, Table 1–30, Table 1–31, Table 1–32, and Table 1–33. ■ Added Table 1–32. ■ Updated Equation 1–1. March 2009 1.1 Added “I/O Timing” section. February 2009 1.0 Initial release. Table 1–69. Document Revision History (Part 2 of 2) Date Version Changes