HSDL-7002 LITEON | Alldatasheet
Document overview
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- PDF pages: 11
Technical content
Features
- Fully Compliant to IrDA Physical Layer Specification 1.4 from 9.6 kbit/s to 115.2 kbit/s (SIR)
- Interfaces with IrDA Compliant IR Transceiver
- Miniature Module Size with 16-pin Quad-Flat-No Lead (QFN) Package Height : 0.8 mm Length : 4.0 mm Depth : 4.0 mm Used in Conjunction with Standard 16550 UART
- Transmits/Receives either 1.63 µs or 3/16 Pulse Mode
- Internal or External Clock Mode
- Programmable Baud Rate 2.7 – 5.5 V Operation
- Lead Free and Green Product
Applications
- Interfaces with IrDA Transceiver in:
- Telecom Applications: Mobile Phones Modems Pagers Fax Machines Computer Applications: Notebook Computers Desktop PCs Dongles or other RS-232 adapters PDAs Printers Handheld Data Collection: Industrial Medical Transportation
Figure 1. Block Diagram of HSDL-7002
Figure 2. HSDL-7002 Pin Configuration The unit is marked with A7002 and ‘yyww’ on the chip. select) the oscillator is automatically put in powerdown mode, or whenever the POWERDN pin asserted high.
1 TXD Digital In Negative edge triggered input signal that is normally tied to the SOUT signal
2 RXD Digital Out Output signal normally tied to SIN signal of a UART (received serial data). RXD is the demodulated output of IR_RXD.
3 A0 Digital In Clock Multiplex Signal
4 A1 Digital In Clock Multiplex Signal
5 A2 Digital In Clock Multiplex Signal
activated the external clock (16XCLK) and a low activates the internal clock.
7 GND Chip Ground
8 NRST Digital In Activate low signal used to reset the IrDA SIR Encode & Decode state ma-
chine. This signal can be tied to POR (Power-On-Reset) or Vcc. demodulated to generate RXD output signal. 10 IR_TXD Digital Out This is the modulated TXD signal.
11 PULSEMOD Digital In
12 POWERDN Digital In
A high on this input put only the internal oscillator cell in POWERDN mode. The cell is normally not powered down.
13 OSCOUT Analog Out Oscillator Output
14 OSCIN Analog In Oscillator Input
15 Vcc Power
the internal clock is not used.
(Vcc = 2.7 to 5.5 V, TA = -20 to +85°C) Notes: 1. Propagation Delay Time in the output buffer is the time taken from the input passing Vcc/2 to the time of the output reaching Vcc/2 with 50 pF as the output load. 2. The Ouput Rise Time is the time taken for the outputs (RXD, IR_TXD) to rise from 10% of the original value to 90% of the final value. 3. The Output Fall Time is the time taken for the outputs (RXD, IR_TXD) to fall from 90% of the original value to 10% of the final value. Parameter Symbol Min. Max. Units Storage Temperature TS -65 +150 °C Operating Temperature TA -40 +85 °C Output Current IO -20 15 mA Power Dissipation [1] PMAX 0.46 W Input/Output Voltage [2] VI /VO -0.5 Vcc+0.5 V Power Supply Voltage VCC -0.5 7.0 V Electrostatic Protection VESD 4000 V Note: 1. All pins are protected from damage to static discharge by internal diode clamps to Vcc and GND. Parameter Symbol Min. Typ. Max. Units Conditions Propagation Delay Time [1] tpd 45 ns Output Rise Time [2] trise 13 ns VCC = 2.7 V, CL = 50 pF VCC = 5.5 V, CL = 50 pF Output Fall Time [3] tfall 12 ns VCC = 2.7 V, CL = 50 pF VCC = 5.5 V, CL = 50 pF Output Capacitance on Output Pads Used for Simulation COUT 50 pF
Recommended Operating Conditions (Vcc = 2.7 to 5.5 V, TA = -20 to +85 °C) Notes: 1. IrDA Parameter. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7002’s internal state machine. Under normal circumstances, the clock input should not exceed 16*115.2 kbit/s or 1.8432 MHz. This product can operate at higher clock rates, but the above is the recommended rate. 2. The Maximum Pulse Width (tmpw) represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RXD pulse). As per the IrDA Physical Layer Specification 1.4, the minimum pulse of the IR_TXD and IR_RXD pulses should be 3*(1/1.8432 MHz) or 1.63 µs. Parameter Symbol Min. Typ. Max. Units Conditions Supply Voltage VCC 2.7 5.0 5.5 V Input Voltage VI 0 VCC V Ambient Temperature TA -20 +85 °C High Level Input Voltage VIH 0.7 VCC VCC V Low Level Input Voltage VIL 0 0.3 VCC V Output High Voltage VOH 2.6 V VCC = 2.7 V IOH = 2 mA Output Low Voltage VOL 0.1 V VCC = 2.7 V IOL = 2 mA Output High Voltage VOH 5.1 V VCC = 5.5 V IOH = 2 mA Output Low Voltage VOL 0.1 V VCC = 2.7 V IOL = 2 mA Static Power Dissipation PSTAT 0.61 mW Dynamic Power Dissipation PDYN 16.5 mW Static Current Consumption ISTAT 50 100 mA VCC = 2.7 V VCC = 5.5 V Dynamic Current Consumption IDYN 1.08 2.45 mA VCC = 2.7 V VCC = 5.5 V Max Clk Frequency (16XCLK) [1] f16XCLK 2 MHz Minimum Pulse Width (IR_TXD) [2] tmpw 1628 ns Pulse Width on Monoshot (IR_TXD and IR_RXD) tmpw 1628 ns Value of Pulldown Resistor used on POW- ERDN & PULSEMOD input pins RDWN 400 213 460 237 510 260 kW VCC = 2.7 V VCC = 5.5 V Trigger Low Level Input Voltage (For NRST input pin) VIL_TRIG 0.93 2.11 0.96 2.14 0.98 2.15 V VCC = 2.7 V VCC = 5.5 V Trigger High Level Input Voltage (For NRST input pin) VIH_TRIG 1.68 3.22 1.69 3.23 1.70 3.25 V VCC = 2.7 V VCC = 5.5 V
Figure 3. HSDL-7002 Package Dimensions
Unit: mm LA BEL Detail A "B" 330 80 Quantity 2500 "C" ∅13.0 ± 0.5 2.0 ± 0.5 21 ± 0.8 R1.0 Detail A 2.0 ± 0.5 16.4 +2 B C
age. Once opened, moisture absorption begins. baked before reflow to prevent damage to the parts. the parts must be stored in a dry box. Baking should only be done once. Figure 4. Baking Conditions Chart
The reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow sol- der process. The temperature profile is divided into four process zones, each with different DT/Dtime temperature change rates. TheDT/Dtime rates are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1, the PC board and HSDL-7002 castella- tion pins are heated to a temperature of 160°C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 4°C per second to allow for even heating of both the PC board and HSDL-7002 castellations. Process zone P2 should be of sufficient time duration (60 to 120 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder, usually 200°C (392°F). Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 255°C (491°F) for optimum results. The dwell time above the liquidus point of solder should be between 20 and 60 seconds. It usually takes about 20 seconds to as - sure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. Beyond a dwell time of 60 seconds, the intermetallic growth within the solder connections becomes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200°C (392°F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25°C (77°F) should not exceed 6°C per second maximum. This limitation is necessary to allow the PC board and HSDL-7002 castellations to change dimen- sions evenly, putting minimal stresses on the HSDL- 7002 endec. 50 100 150 200 250 300 t-TIME (SECONDS) 120 160 180 200 230 255 T - TEMPERATURE (˚C) R3 R4 220 MAX 260C 60 sec MAX Above 220 C HEAT UP SOLDER PASTE DRY SOLDER REFLOW COOL DOWN Recommended Reflow Profile Process Zone Symbol DT Maximum DT/Dtime Heat Up P1, R1 25°C to 160°C 4°C/s Solder Paste Dry P2, R2 160°C to 200°C 0.5°C/s Solder Reflow P3, R3P3, R4 200°C to 255°C (260°C at 10 seconds max) 255°C to 200°C 4°C/s-6°C/s Cool Down P4, R5 200°C to 25°C -6°C/s
sent then the encoder does not generate a pulse. Figure 7. HSDL-7002 Encoding Scheme Figure 8. HSDL-7002 Decoding Scheme
- The stretched pulse must be at least ¾ of a bit time in duration to be correctly interpreted by a UART.
- It is recommended that the TXD remains high when not transmitting. This ensures the LED is off and will not interfere with signal
16 CYCLES 16 CYCLES 16 CYCLES 16 CYCLES
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 CRYSTAL CLK INT CLK (DIV BY 2) TXD INTERNAL IRTXD OUTPUT IRTXD (MONOSHOT)
6 CRYSTAL CYCLES
The figure above illustrates the operation of the monoshot when the internal clock is set to divide by 2 mode, i.e., when A2=0, A1=0, and A0=0. A rising edge on the internal modulation state machine (IR_TXD output), will cause the output on the IR_TXD to go up for 6 crystal clock cycles. With a 3.6864 MHz clock, this corresponds to a pulse of 1.63 µs. The duration of this pulse is independent of the code A2, A1, A0 and is always 6 clock cycles of the crystal, corresponding to the monoshot operation. Monoshot Operation For company and product information, please go to our web site: WWW.liteon.com or http://optodatabook.liteon.com/databook/databook.aspx Data subject to change. Copyright © 2007 Lite-On Technology Corporation. All rights reserved.