HSDL-3220-021

HSDL-3220-021 LITEON | Alldatasheet

Document overview

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Technical content

Part Number Packaging Type Package Quantity HSDL-3220-021 Tape and Reel Front View 2500 I/O Pins Configuration Table Pin Symbol Description I/O Type Notes

1 LED A LED Anode I 1

2 LED C LED Cathode 2

3 TXD Transmit Data. Active High. I 3 4 RXD Receive Data. Active Low. O 4 5 SD Shutdown. Active High. I 5

6 Vcc Supply Voltage 6

7 IOVcc Input/Output ASIC Vcc 7

8 GND Ground 8

• Shield EMI Shield 9 Marking Information The unit is marked with ‘yyww’ on the shield: yy = year ww = work week Recommended Application Circuit Components Component Recommended Value Notes R1 5.6Ω ± 5%, 0.25 watt for 2.7 ≤ Vled< 3.3V 10Ω ± 5%, 0.25 watt for 3.3 ≤ Vled<4.2V 15Ω ± 5%, 0.25 watt for 4.2 ≤Vled< 5.5V CX1, CX4 0.47 µF ± 20%, X7R Ceramic 10 CX2, CX3 6.8 µF ± 20%, Tantalum 11 Notes: 2. Internally connected to LED driver. Leave this pin unconnected. 3. This pin is used to transmit serial data when SD pin is low. If this pin is held high for longer than 50 µs, the LED is turned off. Do NOT float this pin. 4. This pin is capable of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. The pin is in tri-state when the transceiver is in shutdown mode. The receiver output echoes transmitted signal. 5. The transceiver is in shutdown mode if this pin is high for more than 400 µs. On falling edge of this signal, the state of the TXD pin sampled and used to set receiver low bandwidth (TXD=low) or high bandwidth (TXD=high) mode. Refer to the section ”Bandwidth selection timing” for programming information. Do NOT float this pin. 6. Regulated, 2.7 to 3.6 Volts. 7. Connect to ASIC logic controller Vcc voltage or supply voltage. The voltage at this pin must be equal to or less than supply voltage. 8. Connect to system ground. 9. Connect to system ground via a low inductance trace. For best performance, do not connect directly to the transceiver pin GND. 10. CX1 must be placed within 0.7 cm of the HSDL-3220 to obtain optimum noise immunity. 11. In environments with noisy power supplies, including CX2, as shown in Figure 1, can enhance supply ripple rejection performance. Application Support Information The Application Engineering Group is available to as - sist you with the application design associated with the HSDL-3220 infrared transceiver module. You can con - tact them through your local sales representatives for additional details.

able the transceiver to operate at FIR mode.

1.152 Mbit/s)

1. Set SD/Mode input to logic HIGH
2. TXD input should remain at logic LOW
3. Ensure that TXD input remains low for tH ≥ 100 ns, the
4. SD input pulse width for mode selection should be >
5. Set SD/Mode input to logic HIGH
6. After SD/Mode input remains HIGH at > 25 ns, set TXD
7. Then set SD/Mode to logic LOW, the HIGH to LOW
8. After waiting for tH ≥ 100 ns, set the TXD input to logic
9. SD input pulse width mode selection should be >

Figure 3. Bandwidth selection timing at SIR/MIR mode. Figure 4. Bandwidth selection timing at FIR mode.

1. In-band IrDA signals and data rates ≤ 4.0 Mbit/s
2. RXD logic low is a pulsed response. The condition is maintained for a duration dependent on pattern and

strength of the incident intensity. assembly of this component to prevent damage and/or degradation which may be induced by ESD.

For implementations where case to ambient thermal resistance is ≤50°C/W. Parameter S ymbol Min. Max. Units Conditions Storage Temperature TS -40 +100 °C Operating Temperature TA -25 +70 °C LED Anode Voltage VLEDA 0 6.5 V Supply Voltage VCC 0 6.5 V Input Voltage: TXD, SD/Mode VI 0 6.5 V Output Voltage: RXD VO 0 6.5 V DC LED Transmit Current ILED (DC) 50 mA Average Transmit Current ILED (PK) 200 mA ≤ 90µs pulse width ≤25% duty cycle Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Units Conditions Supply Voltage VCC 2.7 3.6 V Input/Output Voltage IOVcc 1.8 Vcc V Logic Input Voltage Logic High VIH IOVcc – 0.5 IOVcc V for TXD, SD/Mode Logic Low VIL 0 0.4 V Logic High EIH, min 0.0081 mW/cm2 9.6kbit/s ≤ in-band signals ≤1.152 Mbit/s[14] Receiver Input Irradiance 0.020 mW/cm2 1.152 Mbit/s < in-band signals ≤ 4.0 Mbit/s[14] EIH, max 500 mW/cm2 9.6 kbit/s ≤ in-band signals ≤ 4.0 Mbit/s[14] Logic Low EIL 0.3 µW/cm2 For in-band signals[14] LED (Logic High) Current ILEDA 150 mA Pulse Amplitude Receiver Data Rate 0.0096 4.0 Mbit/s Note : 14. An in-band optical signal is a pulse/sequence where the peak wavelength, λp, is defined as 850 ≤ λp ≤ 900 nm, and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification v1.4.

Electrical and Optical Specifications Specifications (Min. and Max. values) hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be anywhere in their operating range. All typical values (Typ.) are at 25°C, Vcc set to 3.0V and IOVcc set to 1.8V unless otherwise noted. Parameter Symbol Min. Typ. Max. Units Conditions Receiver Viewing Angle 2θ 30 ° Peak Sensitivity Wavelength λp 880 nm RXD Output Voltage Logic High VOH IOVCC – 0.2 IOVCC V IOH = -200 µA, EI ≤ 0.3 µW/cm2 Logic Low VOL 0 0.4 V IOL = 200 µA, EI ≥ 8.1 µW/cm2 RXD Pulse Width (SIR)[15] tPW (SIR) 1 4.0 µs θ ≤ 15°, CL = 9 pF RXD Pulse Width (MIR)[16] tPW(MIR) 100 500 ns θ ≤ 15°, CL = 9 pF RXD Pulse Width (FIR) [16] tPW(FIR) 80 175 ns θ ≤ 15°, CL = 9 pF RXD Rise and Fall Times tr, tf 60 ns CL = 9 pF Receiver Latency Time[17] tL 25 50 µs Receiver Wake Up Time[18] tW 50 100 µs Transmitter Radiant Intensity IEH 10 45 mW/sr ILEDA= 150 mA, θ ≤ 15°, VTXD ≥ VIH, VSD ≤ VIL, Ta=25°C Viewing Angle 2θ 30 60 ° Peak Wavelength λp 875 nm Spectral Line Half Width ∆λ 35 nm TXD Input Current High IH 10 µA VTXD ≥ VIH Low IL 10 µA 0 ≤ VTXD ≤ VIL LED ON Current ILEDA 150 mA VTXD ≥ VIH, R1=5.6ohm, Vled=3.0V TXD Pulse Width (MIR) tPW(MIR) 148 217 260 ns tPW (TXD) = 217 ns at 1.152 Mbit/s TXD Pulse Width (FIR) tPW(FIR) 115 125 135 ns tPW(TXD)=125 ns at 4.0 Mbit/s Maximum Optical PW[19] tPW(max.) 50 100 µs TXD Rise and fall Time (Optical) tr, tf 600 ns tPW(TXD) = 1.4 µs at 115.2 kbit/s 40 ns tPW (TXD) = 125 ns at 4.0 Mbit/s LED Anode On-State Voltage VON(LEDA) 1.6 2.1 V ILEDA=150 mA, VTXD≥VIH Transceiver Supply Current Shutdown ICC1 0.1 1 µA VSD ≥ VIH, Ta= 25°C Idle ICC2 1.8 3.0 mA VSD ≤ VIL, VTXD ≤ VIL, EI=0 Notes: 15. For in-band signals from 9.6 kbit/s to 115.2 kbit/s, where 9 µW/cm2 ≤ EI ≤ 500 mW/cm2. 17. Latency time is defined as the time from the last TxD light output pulse until the receiver has recovered full sensitivity. 18. Receiver wake up time is measured from Vcc power on or SD pin high to low transition to a valid RXD output. 19. The maximum optical PW is the maximum time the LED remains on when the TXD is constantly high. This is to prevent long turn on time of the LED for eye safety protection.

HSDL-3220 Tape and Reel Dimensions Note: The carrier tape is compliant to the packaging materials standards for ESD sensitive device, EIA-541 Unit: mm 1.75 ± 0.1 7.5 ± 0.1 16.0 ± 0.2 8.0 ± 0.1 8.4 ± 0.1 4.0 ± 0.1 1.5 ± 0.1 3.4 ± 0.1 Progressive Direction 2.8 ± 0.1 0.4 ± 0.05 POLARITY Ø1.5+0.1 Pin 8: VLED Pin 1: GND Empty (40 mm min) Parts Mounted Leader (400 mm min) Empty (40 mm min) Unit: mm LABEL Detail A Option # "B" 178 60 Quantity 500001 330 80 2500021 "C" 13.0 ± 0.5 2.0 ± 0.5 21 ± 0.8 R1.0 Detail A 2.0 ± 0.5 16.4 +2 B C

package. Once opened, moisture absorption begins. This part is compliant to JEDEC Level 4. Figure 11. Baking conditions chart. be baked before reflow to prevent damage to the parts. Baking should only be done once. needed, the parts must be stored in a dry box.

Recommended Reflow Profile Process Zone Symbol ∆T Maximum ∆T/∆time Heat Up P1, R1 25°C to 160°C 4°C/s Solder Paste Dry P2, R2 160°C to 200°C 0.5°C/s Solder Reflow P3, R3 200°C to 255°C (260°C at 10 seconds max) 4°C/s P3, R4 255°C to 200°C -6°C/s Cool Down P4, R5 200°C to 25°C -6°C/s The reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow sol- der process. The temperature profile is divided into four process zones, each with different ∆T/∆time temperature change rates. The ∆T/∆time rates are detailed in the above table. The temperatures are measured at the com - ponent to printed circuit board connections. In process zone P1, the PC board and HSDL-3220 cas - tellation pins are heated to a temperature of 160°C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 4°C per second to allow for even heating of both the PC board and HSDL-3220 castellations. Process zone P2 should be of sufficient time duration (60 to 120 seconds) to dry the solder paste. The tem - perature is raised to a level just below the liquidus point of the solder, usually 200°C (392°F). Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 255°C (491°F) for optimum results. The dwell time above the liquidus point of solder should be between 20 and 60 seconds. It usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. Beyond a dwell time of 60 seconds, the intermetallic growth within the solder connections be - comes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200°C (392°F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25°C (77°F) should not exceed 6°C per second maximum. This limitation is necessary to allow the PC board and HSDL-3220 castellations to change dimen - sions evenly, putting minimal stresses on the HSDL-3220 transceiver. t-TIME (SECONDS) T – TEMPERATURE – ( C) 230 200 160 120 50 150100 200 250 300 180 220 255 HEAT UP SOLDER PASTE DRY SOLDER REFLOW COOL DOWN R3 R4 60 sec. MAX. ABOVE 220 C MAX. 260 C

1. The ground plane should be continuous under the

part, but should not extend under the shield trace.

1. The shield trace is a wide, low inductance trace back

if a clean power supply is used.

1. Vled can be connected to either unfiltered or un -

Figure 16. PCB layout suggestion. tor, similar to CX1, for the IOVcc line.

1. Preferably a multi-layered board should be used to

GROUND PIN TO BOTTOM GROUND LAYER.

Description

The HSDL-3220, a low-cost and small form factor infrared transceiver, is designed to address the mobile computing market such as PDAs, as well as small-embedded mobile products such as digital cameras and cellular phones. It is fully compliant to IrDA 1.4 low power specification from 9.6 kbit/s to 4.0 Mbit/s, and supports HP -SIR and TV Re - mote modes. The design of the HSDL-3220 also includes the following unique features:

• Low passive component count.
• Shutdown mode for low power consumption re - quirement.
• Interface to input/output logic circuits as low as 1.8V Selection of Resistor R1 Resistor R1 should be selected to provide the appropri - ate peak pulse LED current over different ranges of Vcc as shown in the table below. Interface to Recommended I/O chips The HSDL-3220’s TXD data input is buffered to allow for CMOS drive levels. No peaking circuit or capacitor is required. Data rate from 9.6 kbit/s up to 4.0 Mbit/s is available at the RXD pin. The block diagram below shows how the IR port fits into a mobile phone and PDA platform. TRANSCEIVER MOD/ DE-MODULATOR SPEAKER RF INTERFACE AUDIO INTERFACE USER INTERFACE MICROCONTROLLER DSP CORE ASIC CONTROLLER IR MICROPHONE HSDL-3220

Figure 17. Mobile phone platform.

Figure 18. PDA platform. was demonstrated for SIR and FIR speeds.

Figure 19. Window design diagram. sponds to a cone angle of 60°. fractive index of the window material.

should be 10% or less for best optical performance. are available from General Electric Plastics. Note: 920A and 940A are more flame retardant than 141.

From an optics standpoint, the window should be flat. transceiver to the back surface of the window is 3 mm. Figure 22. Shape of windows. Data subject to change. Copyright © 2007 Lite-On Technology Corporation. All rights reserved.