HSDL-3210-021

HSDL-3210 AVAGO | Alldatasheet

Document overview

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• PDF pages: 24

Technical content

Features

• Fully Compliant to IrDA 1.4 low power specification from 9.6 kbit/s to 1.15 Mbit/s
• Ultra small surface mount package
• Minimal height: 2.5 mm CC from 2.7 to 3.6 volts
• Interface to 1.5 volts input/output logic circuits
• Withstands 100 mV p-p power supply ripple typically
• Adjustable optical power for link distance from 5 to 20 cm
• Low shutdown current – 10 nA typical
• Complete shutdown – TxD, RxD, PIN diode
• Three optional external components
• Temperature performance guaranteed, -25 °C to 85°C
• Integrated EMI shield
• IEC60825-1 class 1 eye safe
• Edge detection input – Prevents the LED from long turn on time

Applications

• Mobile telecom – Cellular phones – Pagers – Smart phones
• Data communication – PDAs – Portable printers
• Digital imaging – Digital cameras – Photo-imaging printers HSDL-3210 IrDA® Compliant Low Power

1.15 Mbit/s Infrared Transceiver

Table 1. Serial Interface for Transceiver Control – Write Data Format Commands are shown in Table 1. Figure 3. General command format.

1. C1, which is optional, must be placed within 0.7 cm of the HSDL-3210 to obtain optimum noise immunity.

Table 2. Serial Interface for Transceiver Control – Read Data Format

1. If TXD is stuck in the high state, the LED will turn off after about 14 µs.
2. RXD will echo the TXD signal while TXD is transmitting data.
3. In-Band IrDA signals and data rates ≤ 1.152 Mbps.
4. RXD Logic Low is pulsed response.
5. RXD Logic High during shutdown is a weak pull up (equivalent to an approximately 300 kΩ resistor).

For implementations where case to ambient thermal resistance is ≤50°C/W. Parameter Symbol Min. Max. Units Storage Temperature T S -40 100 °C Operating Temperature T A -25 85 °C LED Supply Voltage V LED 0 6.5 V Supply Voltage V CC 0 6.5 V Input/Output Voltage IOV CC 0V CC V Input Voltage: TXD, SCLK, SD V I 0V CC+ 0.5 V Output Voltage: RXD V O -0.5 V CC+ 0.5 V Caution: The BiCMOS inherent to this design of this component increases the component’s susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Recommended Operating Conditions Parameter Symbol Min. Max. Units Conditions Notes Operating Temperature T A -25 85 °C Supply Voltage V CC 2.7 3.6 V Logic Input Voltage Logic High V IH 2/3 IOVCC IOVCC V 1.5 V ≤IOVCC ≤3.6 V for TXD ,SCLK, SD Logic Low V IL 0 1/3 IOV CC V 1.5 V ≤IOVCC ≤3.6 V Logic High Receiver EI H 0.0081 500 mW/cm 2 For in-band signals 7 Input Irradiance EIH ≤115.2kb/s (SIR) 0.0225 500 mW/cm 2 0.576 Mb/s ≤ in-band 7 signals ≤ 1.15 Mb/s (MIR) Logic Low Receiver Input EI L 0.3 µW/cm2 For in-band signals. Input/Output Voltage IOV CC 1.5 V CC V Receiver Data Rate 0.0024 1.152 Mb/s

Electrical and Optical Specifications Specifications hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be anywhere in their operating range. All typical values are at 25°C and 3.0 V unless otherwise noted. Parameter Symbol Min. Typ. Max. Units Conditions Notes Receiver RXD Output Voltage Logic High V OH IOVCC -0.2 IOV CC VI OH=-200 µA, EI ≤0.3 µW/cm2 Logic Low V OL 0 0.4 V I OL=200 µA8 Viewing Angle 2 φ1/2 30 ° Peak Sensitivity Wavelength λp 880 nm RXD Pulse Width (SIR) t PW (SIR) 1 7.5 µsC L =10 pF 8,9 RXD Pulse Width (MIR) t PW(MIR) 200 750 ns C L =10 pF 9 RXD Rise and Fall Times t R, tF 25 100 ns C L =10 pF Receiver Latency Time t L 25 50 µs1 0 Receiver Wake Up Time t RW 30 100 µs1 1 Transmitter Radiant Intensity (SIR) IE H 4 15 28.8 mW/Sr T A=25°C, θ1/2 ≤15°, TXD ≥ VIH Radiant Intensity (MIR) IE H 9 30 72 mW/Sr T A=25°C, θ1/2 ≤15°, TXD ≥ VIH Peak Wavelength λp 875 nm Spectral Line Half Width ∆λ 1/2 35 nm Viewing Angle 2 φ1/2 30 60 ° Optical Pulse Width (SIR) tpw 1.41 1.6 2.23 µs tpw(TXD) = 1.6 µs Optical Pulse Width (MIR, IOVCC ≥1.5 V) tpw 148 217 260 ns tpw(TXD) = 217 ns Optical Rise and Fall Times (SIR) tr (EI) 50 600 ns tpw(TXD) = 1.6 µs tf (EI) Optical Rise and Fall Times (MIR) tr (EI) 30 40 ns tpw(TXD) = 1.6 µs tf (EI) LED Current On (SIR) I VLED 60 72 mA V VLED=VCC=3.6 V , VI(TXD) ≥ VIH On (MIR) I VLED 150 180 mA V VLED=VCC=3.6 V , VI(TXD) ≥ VIH Current Off I VLED 0.005 1 µsV VLED=VCC=3.6 V , VI(TXD) ≤ VIL Transceiver TXD Input Current High I H 10 200 nA V I ≥ VIH Low I L -10 -200 nA 0 ≤ VI ≤ VIL Supply Current Shutdown I CC1 0.01 µAV CC=3.6 V, VSD ≥ VCC - 0.5, TA=25°C Idle I CC2 300 450 µAV CC=3.6 V, VI(TXD) ≤ VIL,EI=0 Active, I CC3 0.8 3.0 mA V CC=3.6 V, VI(TXD) ≤ VIL 12,13 Receive Notes: 7. An in-band optical signal is a pulse/sequence where the peak wavelength, λp, is defined as 850 nm ≤ λp ≤ 900 nm, and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification. 8. For in band signals ≤ 1.152 Mbps where 9 µW/cm2 ≤ EI ≤ 500 mW/cm2. 10. Latency is defined as the time from the last TXD light output pulse until the receiver has recovered full sensitivity. 11. Receiver wake up time is measured from the SD pin high to low transition or VCC power on, to valid RXD output. 12. Typical values are at EI = 10 mW/cm2. 13. Maximum value is at EI = 500 mW/cm2.

Figure 8. Package outline dimensions.

Figure 9. Tape and reel dimensions.

Figure 10. Baking conditions chart. Baking should only be done once. All HSDL-3210 options are shipped in moisture-proof packaging. Once opened, moisture absorption begins. This product is compliant to JEDEC level 4.

Figure 11. Reflow graph. printed circuit board connections. HSDL-3210 castellation I/O pins. seconds) to dry the solder paste. on the HSDL-3210 transceiver.

Figure 12. Stencil and PCBA.

1.1 Recommended Land Pattern

1.0 Solder Pad, Mask and Metal Solder Stencil Aperture

Figure 13. Land pattern.

Figure 15. Adjacent land keep-out and solder mask areas. Figure 14. Solder stencil aperture.

1.2 Recommended Metal Solder

1.3 Adjacent Land Keepout and

1. The ground plane should be
2. The shield trace is a wide, low
3. V LED can be connected to

Figure 16. PCB layout suggestions.

Appendix C: General Application Guide for the HSDL-3210 Infrared IrDA Compliant 1.15 Mb/s Transceiver

Description

The HSDL-3210, a low-cost and small form factor infrared transceiver, is designed to address the mobile computing market such as PDAs, as well as small embedded mobile products such as digital cameras and cellular phones. It is fully compliant to IrDA 1.3 low power specification from 9.6 kb/s to

1.152 Mb/s, and supports HP-SIR

and TV Remote modes. The design of the HSDL-3210 also includes the following unique features:

• Supports the serial interface for transceiver control (STC) specification.
• Low passive component count.
• Shutdown mode for low power consumption requirement.
• Interface to input/output logic circuits as low as 1.5 V.
• Adjustable optical power management Interface to Recommended I/O chips The HSDL-3210’s TXD data input is buffered to allow for CMOS drive levels. No peaking circuit or capacitor is required. Data rate from 9.6 kb/s up to 1.152 Mbp/s is available at the RXD pin. The block diagram below shows how the IR port fits into a mobile phone and PDA platform. PCMCIA CONTROLLER CPU FOR EMBEDDED APPLICATION IR RAM ROM TOUCH PANEL RS232C DRIVER COM PORT PDA PLATFORM LCD PANEL TRANSCEIVER MOD/ DE-MODULATOR SPEAKER RF INTERFACE AUDIO INTERFACE USER INTERFACE MICROCONTROLLER DSP CORE ASIC CONTROLLER IR MICROPHONE MOBILE PHONE PLATFORM

Figure 17. Mobile phone and PDA platform diagrams.

from the transceiver respectively. Figure 18. STC block diagram.

The bus timings are designed to be simple and to minimize the effects of timing skew. This sec- tion discusses some key points with regard to bus timings and illustrates typical STC transac- tions with the use of waveforms. Bus Timing Notes 1. Data is transferred in Little Endian order, that is, the LSB on the first byte is transmitted first and the MSB of the second or third byte is transmitted last. 2. There are no gaps between bytes in the command or response phases. 3. Each byte in the command and response phase is preceded by a start bit on the SCLK line. 4. For data sampling and clocking, 4.1. Input data is sampled on the rising edge of SCLK. 4.2. Output data from the con- troller is clocked out on the falling edge of SCLK. 4.3. Output data from the slave is clocked out on the rising edge of SCLK. 5. The first low-to-high transition of SCLK indicates that an STC transition is pending. On re- ceipt of his rising edge, the slave will disable the LED. The next SCLK low-to-high transition indicates the start cycle, fol- lowed by the command phase (which the controller puts out on the SWDAT line). The LED needs to be disabled since TXD and SWDAT are multiplexed. If the LED is not disabled, then the LED will pulse according to the SWDAT bit stream. 6. The LED is re-enabled (by the slave) on the last SCLK of the STC transaction bit stream. Normal infrared transmission can resume. No SCLK transi- tions should take place until the next STC transaction else the LED will be disabled. 7. The response from the slave is carried on the SRDAT line, which is multiplexed with RXD. The detector is (internally) dis- abled by the slave during the response phase. This is to pre- vent stray IR transitions from corrupting the SRDAT bit stream. 8. During a READ transaction, the controller holds the SWDAT line low for 1 clock after sending the ADDRESS and INDEX byte. It then holds it high and low for 3 clocks before the end of the transaction. This is to allow the transceiver to monitor the im- pending end of a transaction rather than by counting pulses. 9. When powered up, the trans- ceiver is not ready to perform IR transmissions. The controller has to initialize the transceiver. The brief powered up sequences are: 9.1. On power up, an inter- nally generated signal in the transceiver sets the 3 con- trol registers: a) Control Register 0:

• Bit 0: shutdown mode
• Bit 1: RXD disabled
• Bit 2: LED disabled b) Control Register 1:
• Bit 0-7: SIR mode c) Control Register 2:
• Bit 0-7: Power at 100% level 9.2. The controller has to initial- ize the transceiver by: a) Hold SWDAT low b) Toggle SCLK for at least 30 cycles The transceiver is in STC mode and ready to accept STC transactions.

sponds to a cone angle of 60˚. index of the window material. the following tables and graphs. Figure 26. Window design diagram.

effect of the front surface curve. should be measured at 875 nm. Note: 920A and 940A are more flame retardant than 141L. Recommended Dye: Violet #21051 (IR transmissant above 625 nm). Figure 29. Shape of windows.

For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countrie s. Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved. Obsoletes 5988-8480EN 5989-4390EN May 28, 2006