HSDL-3209-021

HSDL-3209-021 LITEON | Alldatasheet

Document overview

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• PDF pages: 16

Technical content

Features

• Fully Compliant to IrDA 1.4 Low Power Specification from 9.6 kbit/s to 115.2 kbit/s
• Miniature Package - Height : 1.60 mm - Width : 7.00 mm - Depth : 2.80 mm Guaranteed Temperature Performance, -25 to +70 °C - Critical parameters are guaranteed over tempera- ture & supply voltage Low Power Consumption - Complete shutdown of TXD, RXD, and PIN diode
• Vcc Supply 2.4 to 3.6 Volts
• Interface to Input/Output Logic Circuits as Low as 1.5V
• LED Stuck-High Protection
• Designed to Accommodate Light Loss with Cosmetic Windows
• IEC 825-Class 1 Eye Safe
• Lead-free and RoHS Compliant

Applications

• Mobile Telecom - Mobile Phones - Pagers - Smart Phone Data Communication - PDAs - Portable Printers Digital Imaging - Digital Cameras - Photo-Imaging Printers Electronic Wallet Functional Block Diagram

Figure 1. Functional Block Diagram

Notes: 1. CX1, CX2, CX3 and CX4 must be placed within 0.7 cm of the HSDL-3209 to obtain optimum noise immunity. Recommended Application Circuit Components I/O Pins Configuration Table Order Information Part Number Packaging Type Package Quantity HSDL-3209-021 Tape and Reel Front View 2500 Pin Symbol Description I/O Type Function 1 LED A LED Anode Input Tied through external resistor, R1, to VLED from 2.4V to 4.5V. Please refer to Table 1 for VLED versus Series Resistor, R1.

2 RXD Receive Data Output,

This pin is capable of driving a standard CMOS or TTL load. No external pull-up or pull down resistor is required. It is in tri-state mode when the transceiver is in shutdown mode.

3 TXD Transmit Data Input,

This pin is used to transmit serial data when SD pin is low. If held high longer than ~ 50ms, the LED will be turned off.

4 SD Shutdown Input,

The transceiver is in shutdown mode if this pin is high

5 IOVcc Input/Output

Connect to ASIC logic controller Vcc Voltage as low as 1.5V.

6 Vcc Supply

Regulated, 2.4 to 3.6 Volts. 7 GND Ground Ground Connect to system ground. Component Recommended Value Note R1 15W±5%, 0.0625 Watt for 2.4 ≤ Vled ≤ 2.7V 27W±5%, 0.0625 Watt for 2.7 < Vled ≤ 3.6V 36W±5%, 0.0625 Watt for 3.6 < Vled ≤ 4.5V CX1, CX4 0.47 µF ± 20%, X7R Ceramic 1 CX2, CX3 6.8 µF ± 20%, X7R Ceramic or Tantalum 1 CAUTIONS: The CMOS inherent to the design of this component increases the component’s susceptibility to damage from the electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD

Notes: 3. An in-band optical signal is a pulse/sequence where the peak wavelength, λp, is defined as 850 ≤ λp ≤ 900 nm, and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification v1.4. Recommended Operating Conditions Notes: 2. ≤ 20% duty cycle, ≤ 90 ms pulse width. Absolute Maximum Ratings For implementations where case to ambient thermal resistance is ≤ 50°C/W. Parameter Symbol Min. Max. Units Notes Storage Temperature TS -40 +100 °C Operating Temperature TA -25 85 °C LED Anode Voltage VLEDA 0 6.5 V Supply Voltage VCC 0 6.5 V Input/Output Voltage IOVCC 0 VCC V Input Voltage : SD VI(SD) 0 IOVCC V Input Voltage : TXD VI(TXD) 0 IOVCC V DC LED Transmit Current ILED (DC) 50 mA Peak LED Transmit Current ILED (PK) 250 mA 2 Parameter Symbol Min. Typ. Max. Units Conditions Operating Temperature TA -25 70 °C Supply Voltage VCC 2.4 3.6 V Input/Output Voltage IOVCC 1.5 VCC V Logic Input Voltage for TXD/SD Logic High V IH IOVcc-0.2 IOVcc V The minimum input logic voltage should not be lower than 1.5V Logic Low V IL 0 0.4 V Receiver Input Irradiance Logic High EI H 0.0081 500 mW/cm2 For in-band signals ≤ 115.2kbit/s [3] Logic Low EI L 1.0 mW/cm2 For in-band signals [3] LED (Logic High) Current Pulse Amplitude I LEDA 50 mA Receiver Data Rate 9.6 115.2 kbit/s Ambient Light See IrDA Serial Infrared Physical Layer Link Specification, Appendix A for ambient levels

Electrical & Optical Specifications Specifications (Min. & Max. values) hold over the recommended operating conditions unless otherwise noted. Un - specified test conditions may be anywhere in their operating range. All typical values (Typ.) are at 25°C with Vcc set to 3.0V and IOVcc set to 1.8V unless otherwise noted. Notes: 4. For in-band signals from 9.6kbit/s to 115.2 kbit/s, where 9µW/cm2 ≤ EI ≤ 500mW/cm2. 5. Latency time is defined as the time from the last TxD light output pulse until the receiver has recovered full sensitivity 6. Receiver wake up time is measured from Vcc power on or SD pin high to low transition to a valid RXD output. 7. The maximum optical PW is the maximum time the LED remains on when the TXD is constantly high. This is to prevent long turn on time of the LED for eye safety protection. 8. For Vcc > 3V and IOVcc < 1.8V, ICC1 can exceed 15uA. Parameter Symbol Min. Typ. Max. Units Conditions Receiver Viewing Angle 2q½ 30 ° Peak Sensitivity Wavelength lp 880 nm RXD Output Voltage Logic High VOH IOVcc- 0.2 IOVcc V IOH = -200 mA, EI ≤ 1.0 mW/cm2 Logic Low VOL 0 0.4 V IOL = 200 mA, EI ≥ 8.1 mW/cm2 RXD Pulse Width (SIR) [4] tPW (SIR) 1 4.0 ms q½ ≤ 15°, CL =9 pF RXD Rise and Fall Times tr, tf 60 ns CL =9 pF Receiver Latency Time [5] tL 50 ms Receiver Wake Up Time [6] tW 100 ms Transmitter Radiant Intensity IEH 4 14 mW/ sr ILEDA= 50 mA, q½ ≤ 15°, VTXD ≥ VIH TA=25 °C, IOVcc = 1.8V Viewing Angle 2q½ 30 60 ° Peak Wavelength lp 875 nm Spectral Line Half Width Dl½ 35 nm TXD Input Current High IH 0.02 10 mA VI ≥ VIH Low IL -10 -0.02 10 mA 0 ≤ VI ≤ VIL LED Current On IVLED 50 mA VI(TXD) ≥ VIH Shutdown IVLED 200 nA VI(SD) ≥ VIH Optical Pulse Width (SIR) tPW (SIR) 1.4 1.6 1.8 ms tPW (TXD) = 1.6 ms at 115.2 kbit/s Maximum Optical PW [7] tPW(max.) 100 ms TXD Rise and fall Time (Optical) tr, tf 600 ns tpw(TXD) = 1.6 ms LED Anode On State Voltage VON(LEDA) 1.55 1.8 V ILEDA=50mA, VI(TXD) ≥ VIH Transceiver Supply Current Shutdown [8] ICC1 0.18 1 mA VSD ≥ VIH, TA=25°C Idle ICC2 100 mA VI(TXD) ≤ VIL, EI = 0

0.80 PCB solder pad length 1.60 0.80 2.80 0.80 0.34 (5x) 0.40 (2x) Mounting Centre 7.00 3.50 0.950.95 5.10 R1.10 R1.10 PCB 0.80 1.60 LEDA RXD TXD SD IOVcc Vcc GND Notes : 1. ALL DIMENSIONS IN MILLIMETERS (mm). 2. DIMENSION TOLERANCE IS 0.2mm UNLESS OTHERWISE SPECIFIED.

HSDL-3209 Tape and Reel Dimensions Unit: mm 1.75 ± 0.1 7.5 ± 0.1 16.0 ± 0.2 4.0 ± 0.1 7.35 ± 0.1 4.0 ± 0.1 2.0 ± 0.1 2.93 ± 0.1 Progressive Direction 1.78 ± 0.1 0.3 ± 0.05 POLARITY ∅1.5 +0.1 Pin 7: GND Pin 1: LEDA Empty (40mm min) Parts Mounted Leader (400mm min) Empty (40mm min) Unit: mm LABEL Detail A Option # "B" 330 80 Quantity 2500021 "C" ∅13.0 ± 0.5 2.0 ± 0.5 21 ± 0.8 R1.0 Detail A 2.0 ± 0.5 16.4 +2 B C

All HSDL-3209 options are shipped in moisture proof package. Once opened, moisture absorption begins. This part is compliant to JEDEC Level 3. Units in A Sealed Mositure-Proof Package Package Is Opened (Unsealed) Environment less than 30 deg C, and less than 60% RH ? Package Is Opened less than 168 hours ? Perform Recommended Baking Conditions No Baking Is Necessary No Yes No Yes Baking Conditions: If the parts are not stored in dry conditions, they must be baked before reflow to prevent damage to the parts. Baking should only be done once. Recommended Storage Conditions: Before MBB Unsealed PACKAGE Temperature Time In Reel 60°C ≥ 48 hours In Bulk 100°C ≥ 4 hours Storage temperatureStorage temperature Storage Temperature 10°C to 30°C Relative Humidity below 60% RH Time from unsealing to soldering: After removal from the bag, the parts should be soldered within 168 hours if stored at the recommended storage conditions.

Recommended Reflow Profile point of solder to 255°C (491°F) for optimum results. The dwell time above the liquidus point of solder should be between 20 and 60 seconds. It usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. Beyond a dwell time of 60 seconds, the intermetallic growth within the solder connections be - comes excessive, resulting in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200°C (392°F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25°C (77°F) should not exceed 6°C per second maximum. This limitation is necessary to allow the PC board and HSDL-3209 castellations to change dimen- sions evenly, putting minimal stresses on the HSDL-3209 transceiver. The reflow profile is a straight-line representation of a nominal temperature profile for a convective reflow sol - der process. The temperature profile is divided into four process zones, each with different DT/Dtime temperature change rates. The DT/Dtime rates are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1, the PC board and HSDL-3209 castella- tion pins are heated to a temperature of 160°C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 4°C per second to allow for even heating of both the PC board and HSDL-3209 castellations. Process zone P2 should be of sufficient time duration (60 to 120 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder, usually 200°C (392°F). Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus Process Zone Symbol DT Maximum DT/Dtime Heat Up P1, R1 25°C to 160°C 4°C/s Solder Paste Dry P2, R2 160°C to 200°C 0.5°C/s Solder Reflow P3, R3 P3, R4 200°C to 255°C (260°C at 10 seconds max) 255°C to 200°C 4°C/s -6°C/s Cool Down P4, R5 200°C to 25°C -6°C/s 50 100 150 200 250 300 t-TIME (SECONDS) 120 160 180 200 230 255 T - TEMPERATURE (˚C) R3 R4 220 MAX 260C 60 sec MAX Above 220 C HEAT UP SOLDER PASTE DRY SOLDER REFLOW COOL DOWN

Appendix A: SMT Assembly Application Note

1.0 Solder Pad, Mask and Metal Stencil Aperture

1.1 Recommended Land Pattern

1.75 0.775 fiducial 0.60 0.95 1.9 2.85 0.10 Mounting Center Unit: mm CL

1.2 Recommended Metal Solder Stencil Aperture

It is recommended that only a 0.152 mm (0.006 inches) or a 0.127 mm (0.005 inches) thick stencil be used for solder paste printing. This is to ensure adequate printed solder paste volume and no shorting. See the table below the drawing for combinations of metal stencil aperture and metal stencil thickness that should be used. Aperture opening for shield pad is 2.7 mm x 1.25 mm as per land pattern. 7.2 3.0 2.6 0.2 Units: mm Solder mask

1.3 Adjacent Land Keepout and Solder Mask Areas

Adjacent land keep-out is the maximum space occupied by the unit relative to the land pattern. There should be no other SMD components within this area. The minimum solder resist strip width required to avoid solder bridging adjacent pads is 0.2 mm. It is recommended that two fiducial crosses be place at midlength of the pads for unit alignment. Note: Wet/Liquid Photo- Imageable solder resist/mask is recommended. Stencil Thickness, t (mm) Aperture size (mm) Length, l (mm) Width, w (mm) w l Apertures as per land Dimensions t

Appendix B: PCB Layout Suggestion The HSDL 3209 is a shieldless part and hence does not contain a shield trace unlike the other transceivers. The following PCB layout guidelines should be followed to obtain a good PSRR and EM immunity resulting in good electrical performance. Things to note: 1. The ground plane should be continuous under the part. 2. VLED can be connected to either unfiltered or unreg - ulated power supply. If VLED and Vcc share the same power supply, CX3 need not be used and the connec- tions for CX1 and CX2 should be before the current limiting resistor R1. CX1 is generally a ceramic capaci - Top View The area underneath the module at the second layer, and 3cm in all direction around the module is defined as the critical ground plane zone. The ground plane should be maximized in this zone. Refer to application note AN1114 or the Lite-On Technology IrDA Data Link Design Guide for details. The layout below is based on a 2-layer PCB. Bottom View Top layer Connect the metal shield & module ground pin to bottom ground layer Layer 2 Critical ground plane zone. Do not connect directly to the module ground pin Layer 3 Keep data bus away from critical ground plane zone Bottom layer (GND) tor of low inductance providing a wide frequency response while CX2 and CX3 are tantalum capacitors of big volume and fast frequency response. The use of a tantalum capacitor is more critical on the VLED line, which carries a high current. CX4 is an optional ceramic capacitor, similar to CX1, for the IOVcc line. 3. Preferably a multi-layered board should be used to provide sufficient ground plane. Use the layer un - derneath and near the transceiver module as Vcc, and sandwich that layer between ground connected board layers. Refer to the diagram below for an ex - ample of a 4 layer board,

Appendix D: Window Designs for HSDL-3209 Optical Port Dimensions for HSDL-3209 To ensure IrDA compliance, some constraints on the height and width of the window exist. The minimum dimensions ensure that the IrDA cone angles are met without vignetting. The maximum dimensions minimize the effects of stray light. The minimum size corresponds to a cone angle of 30° and the maximum size corresponds to a cone angle of 60°. In the figure above, X is the width of the window, Y is the height of the window and Z is the distance from the HSDL-3208 to the back of the window. The distance from the center of the LED lens to the center of the photodiode lens, K, is 5.1mm. The equations for computing the win - dow dimensions are as follows: X = K + 2*(Z+D)*tanA Y = 2*(Z+D)*tanA K Z X Y D IR Transparent WindowOPAQUE MATERIAL IR Transparent Window OPAQUE MATERIAL A Module Depth (z) mm Aperture Width (x, mm) Aperture height (y, mm) Max min Max Min 8.76 6.80 3.66 1.70 1 9.92 7.33 4.82 2.33 2 11.07 7.87 5.97 2.77 3 12.22 8.41 7.12 3.31 4 13.38 8.94 8.28 3.84 5 14.53 9.48 9.43 4.38 6 15.69 10.01 10.59 4.91 7 16.84 10.55 11.74 5.45 8 18.00 11.09 12.90 5.99 9 19.15 11.62 14.05 6.52 The above equations assume that the thickness of the window is negligible compared to the distance of the module from the back of the window (Z). If they are comparable, Z’ replaces Z in the above equation. Z’ is defined as Z’=Z+t/n where ‘t’ is the thickness of the window and ‘n’ is the re - fractive index of the window material. The depth of the LED image inside the HSDL-3208, D, is 3.17mm. ‘A’ is the required half angle for viewing. For IrDA compliance, the minimum is 15° and the maximum is 30°. Assuming the thickness of the window to be negligible, the equations result in the following tables and graphs:

Aperture Width (X) vs Module Depth Module Depth (z) mm Aperture Width (x) mm 0 1 2 3 4 5 6 7 8 9 Aperture Height(Y) vs Module Depth Module Depth (z) mm Aperture Height (Y) mm Xmax Xmin Ymax Ymin Window Material Almost any plastic material will work as a window mate - rial. Polycarbonate is recommended. The surface finish of the plastic should be smooth, without any texture. An IR filter dye may be used in the window to make it look black to the eye, but the total optical loss of the window should be 10% or less for best optical performance. Light loss should be measured at 875 nm. Note: 920A and 940A are more flame retardant than 141. Recommended Dye: Violet #21051 (IR transmissant above 625 nm) material # Light Transmission Haze Refractive Index Lexan 141 88% 1% 1.586 Lexan 920A 85% 1% 1.586 Lexan 940A 85% 1% 1.586 The recommended plastic materials for use as a cosmetic window are available from General Electric Plastics. Recommended Plastic Materials:

From an optics standpoint, the window should be flat. This ensures that the window will not alter either the radiation pattern of the LED, or the receive pattern of the photodiode. If the window must be curved for mechanical or industrial design reasons, place the same curve on the back side of the window that has an identical radius as the front side. While this will not completely eliminate the lens effect of the front curved surface, it will significantly reduce the effects. The amount of change in the radiation pattern is dependent upon the material chosen for the window, the Flat Window (First choice) Curved Front and Back (Second choice) Curved Front, Flat Back (Do not use) radius of the front and back curves, and the distance from the back surface to the transceiver. Once these items are known, a lens design can be made which will eliminate the effect of the front surface curve. The following drawings show the effects of a curved window on the radiation pattern. In all cases, the center thickness of the window is 1.5 mm, the window is made of polycarbonate plastic, and the distance from the trans- ceiver to the back surface of the window is 3 mm. For company and product information, please go to our web site: WWW.liteon.com or http://optodatabook.liteon.com/databook/databook.aspx Data subject to change. Copyright © 2007 Lite-On Technology Corporation. All rights reserved.