HS7541AKN

HS7541A SIPEX | Alldatasheet

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HS7541A 12-Bit CMOS Multiplying DAC © Copyright 2000 Sipex Corporation DESCRIPTION… The HS7541A is a low–cost, high stability monolithic 12–bit CMOS 4–quadrant multiplying DAC. It is constructed using a proprietary low–TCR thin–film process that requires no laser–trimming to achieve 12–bit performance. The HS7541A is a superior pin–compatible replacement for the industry standard 7541 and AD7541A. It is available in both commercial and industrial temperature ranges. It operates with +5V to +15V power supply voltages. It is available in 18– pin plastic DIP and SOIC, and 20–pin PLCC packages. n ±0.5 LSB DNL and INL n High Stability, Segmented Architecture (3 MSB’s) n Proprietary, Low TCR Thin–Film Resistor Technology n Low Sensitivity to Output Amplifier Offset n 2KV ESD Protection on All Digital Inputs n Operates With +5V to +15V Power Supplies n AD7541/7541A Replacement n Low Cost D 11 (MSB) [4] D 10 [5] D 9 [6] D 8 [7] D 7 [8] D 6 [9] D 5 [10] D 4 [11] D 3 [12] D 2 [13] D 1 [14] D 0 (LSB) [15] R FB [18] VDD [16]GND [3] VREF [17] 20K Ω 10K Ω20K Ω 10K Ω20K Ω 10K Ω20K Ω 10K Ω20K Ω 10K Ω20K Ω 10K Ω20K Ω 10K Ω20K Ω 10K Ω20K Ω 10K Ω20K Ω 10K Ω20K Ω 10K Ω20K Ω 20K Ω IO2 [2] IO1 [1] 10K Ω HS7541A 12–Bit CMOS Multiplying DAC

HS7541A 12-Bit CMOS Multiplying DAC © Copyright 2000 Sipex Corporation SPECIFICATIONS (TA=25°C; VDD =+15V, VREF = +10V; IO1 = IO2 = GND = 0V; unipolar unless otherwise noted.) PARAMETER MIN. TYP. MAX. UNIT CONDITIONS STATIC PERFORMANCE Resolution 12 Bits Integral Non-Linearity Note 6 -AJ, -AA ±1.0 LSB Note 5; 11-bit relative accuracy -AK, -AB ±0.5 LSB Note 5; 12-bit relative accuracy Differential Non-Linearity Note 7 -AJ, -AA ±1.0 LSB Note 5; Monotonic to 12-bits -AK, -AB ±0.5 LSB Note 5; Monotonic to 12-bits Gain Error Note 17 -AJ, -AA ±6 LSB ±8 LSB Note 5 -AK, -AB ±3 LSB ±5 LSB Note 5 Output Leakage Current ±5 nA At I O1 (Pin 1); Note 18 ±10 nA Note 5 AC PERFORMANCE CHARACTERISTICS Output Amplifier HOS-050; Note 8 Propagation Delay 100 ns Note 9 Current Settling Time 0.6 µs Full scale transition; Note 10 Output Capacitance CI O1 (Pin 16) 200 pF Note 5; data inputs V IH CIO2 (Pin 15) 70 pF Note 5; data inputs V IH CIO1 (Pin 16) 70 pF Note 5; data inputs V IL CIO2 (Pin 15) 200 pF Note 5; data inputs V IL Glitch Energy 1,000 nVs Note 11 Multiplying Feedthrough Error 1.0 mV P-P Measured at output IO1 ; Note 12 0.1 mV P-P Measured at output IO1 ; Note 13 STABILITY Gain Error TC ±1.0 ppm/ °C INL TC ±0.1 ppm/ °C DNL TC ±0.1 ppm/ °C Power Supply Rejection Ratio ±0.02 %/% V DD = 14 to 16V REFERENCE INPUT Input Resistance 7 10 15 K Ω Pin 19 to GND Input Resistance TC ±150 ppm/ °C Voltage Range ±25 Volts Note 5 and 14 CAUTION: ESD (ElectroStatic Discharge) sensitive device. Permanent damage may occur on unconnected devices subject to high energy electrostatic fields. Unused devices must be stored in conductive foam or shunts. Personnel should be properly grounded prior to handling this device. The protective foam should be discharged to the destination socket before devices are removed. ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted.) These are stress ratings only and functional operation of the device at these or any other above those indicated in the operation sections of the specifications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. V

HS7541A 12-Bit CMOS Multiplying DAC © Copyright 2000 Sipex Corporation SPECIFICATIONS (continued) (TA=25°C; VDD =+15V, VREF = +10V; IO1 = IO2 = GND = 0V; unipolar unless otherwise noted.) PARAMETER MIN. TYP. MAX. UNIT CONDITIONS DIGITAL INPUTS Logic Levels VIH 2.4 V DD Volts

2.4 Volts Note 5

VIL -0.3 0.8 Volts

0.8 Volts Note 5

Input Current ±1.0 µAV IN = 0V or VDD ±10 µA Note 5 and 15 Input Capacitance V IN = 0; Note 5 and 14 Bits 1—12 8 pF Note 5 Coding Unipolar Binary Bipolar Offset Binary POWER REQUIREMENTS Voltage Range +5 +15 Volts Note 16 +16 Volts Note 5 Supply Current 2.0 2.5 mA All digital inputs V IL or VIH 2.5 mA Note 5; all digital inputs V IL or VIH 0.2 0.5 mA All digital inputs 0V or 5V to VDD 1.0 mA Note 5; all digital inputs 0V or 5V to VDD ENVIRONMENTAL AND MECHANICAL Operating Temperature -AK, -AJ 0 +70 °C -AB, -AA -40 +85 °C Storage Temperature -65 +150 °C Package -AK, -AJ 18-pin plastic DIP, 20-pin PLCC, 18–pin SOIC Notes and Cautions: 1. Do not apply voltages higher than VDD or less than GND potential on any terminal other than VREF or VRFB . 2. The digital inputs are diode-clamp protected against ESD damage. However, permanent damage may occur on unprotected units from high-energy electrostatic fields. Keep units in conductive foam at all times until ready to use. 3. Use proper anti-static handling procedures. 4. Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation at or above these specifications is not implied. Exposure to the above maximum rated conditions for extended periods may affect device reliability. 5. From T MIN to TMAX . 6. Integral Non-linearity is measured as the arithmetic mean value of the magnitudes of the greatest positive deviation and the greatest negative deviation from the theoretical value of any given input combination. 7. Differential Non-linearity is the deviation of an output step from the theoretical value of 1 LSB for any two adjacent digital input codes. 8. AC performance characteristics are included for design guidance only and are subject to sample testing only. 9. R L = 100Ω , CEXT = 13pF; all data inputs 0V to VDD or VDD to 0V; from 50% digital input change to 90% of final analog output. 10. Settling to ±0.01% FSR (strobed); all data inputs 0V to VDD or VDD to 0V. 11. V REF = 0V, DAC register alternatively loaded with all 0’s and all 1’s. 12. V REF = 20VP-P; F = 10kHz sinewave. 13. V REF = 20VP-P; F = 1kHz sinewave. 14. Guaranteed by design, but not production tested. 15. Logic inputs are MOS gates. I IN typically is less than 1nA @ 25°C. 16. Accuracy is guaranteed at VDD = +15V only. 17. Measured using internal feedback resistor with DAC loaded with all 1’s. 18. All digital inputs = 0V.

Pin 1 — IO1 — Inverted Current Output. Pin 2 — IO2 — Current Output. Pin 3 — GND — Analog Ground. Pin 16 — VDD — +5V to +15V Power Supply. Pin 17 — VREF — Voltage Reference Input. Pin 18 — RFB — Feedback Resistor. Pin 1 — IO1 — Inverted Current Output. Pin 2 — IO2 — Current Output. Pin 3 — GND — Analog Ground. Pin 4 — N.C. — No Connection. Pin 17 — N.C. — No Connection. Pin 18 — VDD — +5V to +15V Power Supply. Pin 19 — VREF — Voltage Reference Input. Pin 20 — RFB — Feedback Resistor. which contributes to the stability of the DAC. op amp is matched to the R–2R ladder. Figure 1. The R-2R inverted ladder binarily each ladder leg independent of the input code.

HS7541A 12-Bit CMOS Multiplying DAC © Copyright 2000 Sipex Corporation

ORDERING INFORMATION

0°C to +70°C Operating Temperature: –40°C to +85°C Operating Temperature: Corporation SIGNAL PROCESSING EXCELLENCE Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others. Sipex Corporation Headquarters and Sales Office

22 Linnell Circle

Billerica, MA 01821 TEL: (978) 667-8700 FAX: (978) 670-9001 e-mail: sales@sipex.com Sales Office

233 South Hillview Drive

Milpitas, CA 95035 TEL: (408) 934-7500 FAX: (408) 935-7600