HS3120C-2N

HS7512 SIPEX | Alldatasheet

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SIGNAL PROCESSING EXCELLENCE 113 DESCRIPTION… The SP7512 and HS3120 are precision 12-bit multiplying DACs, double–buffered for easy interfacing with microprocessor busses. Both unipolar and bipolar operation can be accommo- dated with a minimum of external components. The SP7512 is available for use in commercial and industrial temperature ranges, packaged in a 28-pin SOIC. The HS3120 is available in commercial and military temperature ranges, packaged in a 28–pin side–brazed DIP. I Monolithic Construction I 12–Bit Resolution I 0.01% Non-Linearity I Four–Quadrant Multiplication I Latch-up Protected I Low Power – 30mW I Single +15V Power Supply (MSB) Bit 1 (LSB) BIT 12 LDTR V DD1 VDD2 GND GND SP7512, HS3120 VREF CE HBE MBE LBE LDAC FB1 I01 I02 FB4 FB3 R/2 R/2 R DAC REGISTER

12 BIT MDAC

Double–Buffered 12-Bit Multiplying DAC Corporation SIGNAL PROCESSING EXCELLENCE

SIGNAL PROCESSING EXCELLENCE 114 SPECIFICATIONS (Typical @ 25°C, nominal power supply, VREF = +10V, unipolar, unless otherwise noted) PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DIGITAL INPUT Resolution Bits 2–Quad, Unipolar Coding Binary & Comp. Binary The input coding is comple- mentary binary if I02 is used. 4–Quad, Bipolar Coding Offset Binary Logic Compatibility CMOS, TTL Digital input voltage must not exceed supply voltage or go below –0.5V ; “0” <0.8V; 2.4V < “1” ≤VDD Input Current µA Data Set-up Time 250 ns All strobes are level triggered. See Timing Diagram; GBD* Strobe Width 250 ns All strobes are level triggered. See Timing Diagram; GBD* Data Hold Time ns All strobes are level triggered. See Timing Diagram; GBD* REFERENCE INPUT Voltage Range ±25 V Input Impedance KOhms ANALOG OUTPUT Scale Factor 62.5 187.5 µA/VREF Scale Factor Accuracy ±0.4 Using the internal feedback resistor and an external op amp. Output Leakage nA At 25°C; the output leakage current will create an offset voltage at the external op amps output. It doubles every 10°C temperature increase. Output Capacitance COUT 1, all inputs high pF COUT 1, all inputs low pF COUT 2, all inputs high pF COUT 2, all inputs low pF STATIC PERFORMANCE Integral Linearity SP7512BN/KN, HS3120–2 ±0.015 % FSR Differential Linearity SP7512BN/KN, HS3120–2 ±0.024 %FSR Monotonicity SP7512BN/KN, HS3120–2 Guaranteed to 12 bits STABILITY (TMIN to TMAX) Scale Factor ppm FSR/°C Note 1 Integral Linearity 0.2 ppm FSR/°C Differential Linearity 0.2 ppm FSR/°C STABILITY (TMIN to TMAX) Monotonicity Temp. Range SP7512KN, HS3120C–_ +70 SP7512BN –40 +85 HS3120B–_ –55 +125

SIGNAL PROCESSING EXCELLENCE 115 SPECIFICATIONS (continued) (Typical @ 25°C, nominal power supply, VREF = +10V, unipolar unless otherwise noted) PARAMETER MIN. TYP. MAX. UNITS CONDITIONS DYNAMIC PERFORMANCE Digital Small Signal Settling 1.0 µS Full Scale Transition Settling 2.0 µS to 0.01% (strobed) Reference Feedthrough Error (VREF = 20Vpp) @ 1kHz mV @ 10kHz mV Delay to output from Bits input 100 ns Delay times are twice the from LDAC 200 ns amount shown at TA = +125° C from CE 120 ns POWER SUPPLY (VDD) Operating Voltage +15 ±5% V specifications guaranteed Voltage Range +16 V Current 2.5 mA Rejection Ratio 0.002 %/% ENVIRONMENTAL AND MECHANICAL Operating Temperature SP7512K +70 SP7512B –40 +85 HS3120–C +70 HS3120–B –55 +125 HS3120–B/883 –55 +125 Storage Temperature –65 +150 Package SP7512_N 28-pin SOIC HS3120–C 28–pin Plastic DIP HS3120–B 28–pin Side–Brazed DIP Notes: Using the internal feedback resistor, output leakage current creates an offset, which doubles every 10°C rise in temperature.

Figure 1. Unipolar Operation resistor for the 1 LSB offset in bipolar mode.

SIGNAL PROCESSING EXCELLENCE 118 TIMING INPUT DATA CE LBE MBE HBE LDAC OUTPUT TIME AXIS NOT TO SCALE. ALL STROBES ARE LEVEL TRIGGERED. t1: Data Setup Time, Time data must be stable before strobe (byte enable/ LDAC) goes to “0”, t1 (min) = 250ns. t2: Strobe Width. t2 (min) = 250ns. (CE, LBE, MBE, HBE, LDAC). t3: Hold Time. Time data must be stable after strobe goes to “0”, t3 = 0ns. t4: Delay from LDAC to Output, t4 = 200ns. NOTE: Minimum common active time for CE and any byte enable is 250ns.

ORDERING INFORMATION

Double–Buffered 12–Bit Multiplying DAC