HS3120 SIPEX | Alldatasheet

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‘* Monolithic Construction = 12 Bit Resolution ‘= 0,01% Non-Linearity ~ = UP Compatible N 34 = 4.Quadrant Multiplication ‘ = Latch-up Protected if The HS 3120 is a precision monolithic 12-bit multiplying DAC with internal two-stage input storage registers for easy interfacing with microprocessor busses. It is packaged in a 28-pin DIP to give high 1/O design flexibility, DOUBLE BUFFERED ~ The input registers are sectioned controls are level-triggered to allow static or dynamic into 3 segments of 4 bits each, all individually addressable. operation. The DAC-register, following the input registers, is a parallel VERSATILE OUTPUTS — A total of 5 output lines are pro- 12-bit register for holding the DAC data while the input vided by the HS 3120 to allow unipolar and bipolar output registers are updated. Only the data held in the DAC register connection with a minimum of external components. The determines the analog output value of the converter. feedback resistor is internal. The resistor ladder network rminati nally available, thus eliminating an MICRO PROCESSOR COMPATIBLE — The HS 3120 has termination is external i . been designed for great flexibility in connecting to bus- external resistor for the 1 LSB offset in bipolar mode. oriented systems, The 12 data inputs are organized into 3 MONOLITHIC CMOS CONSTRUCTION — The HS 3120 is independent addressable 4-bit input registers such that the a one-chip CMOS circuit with a resistor ladder network de- HS 3120 can be connected to either a 4, 8 or 16-bit data signed for 0.01% linearity without laser trimming, Smal! bus. The control logic of the HS 3120 includes chip enable chip size and high manufacturing yields result in greatly and latch enable inputs for flexible memory mapping. All reduced cost. mss (se) Birt 2 3 4 § 6 7 8 9 1 MBIT? Vaep °5656 9 99908 89 600 8 of sol ss) 12] ta] sal ss] to] v7] se) sol 20] Hae CONTROL zal_| “tours meeo 8

2 So 101

© 102 Sores ee J 7 6 6 6 64 6 Voor Yooz GND GND. LotR 143

(Typical @ 25°C, nominal power supply, VEE ~ +10V, unipolar uniess otherwise noted). MODEL HS 3120-2 HS3120-0 TYPE MULTIPLYING DOUBLE BUFFEREDINPUTS DIGITAL INPUT Resolution 12.8, * 2-Quad, Unipolar Coding Binary!, Comp. Binary! : 4-Quad. Bipolar Coding Offset Binary : Logic Compatibility GMOS, TTL : Input Current £1 WA (onan) ‘ Data Set-up Time 250nS (min) . Strobe Width? 250nS (min) ‘ Data Hold Time? {nS (min) . REFERENCE INPUT Voltage Range _ =28V (max) . Input Impedance Bkg #50% . ANALOG OUTPUT ee Scale Factor T2EWAN pet 50% > Scale Factor Acguracy4 20.4% , Output Leakage @ 25°C <10nA (max) : @ 125°C £200nA (max) : Output Capacitance Cour 1. all inputs high B00F : COUT 1. all inputs low 4006 : COUT 2. all inputs high 400F : COUT 2: all inputs tow 800F . STATIC PERFORMANCE Monotonicity Guaranteed to 12 bits Gueranteed to 10 bits Monotonicity Temp. Range C-Models O° to +70°C : B-Models =85°C to +126°C . DYNAMIC PERFORMANCE Digital Small Signal Settling TOusec . Full Scale Transition Settling 10 0.01% {strobed) 2.0usee : Reference Feedthrough Error (Vet = 20Vpp) @ kHz <imv : @ 10kHe amv : Delay to output from Bits input s00ns6 : from LOAC 200ns8 : trom CE Y20nsé : STABILITY (Over Specified Temp. Range) Scale Factor4 2 ppm FSAIPG (nan) . Integral Linearity 0.2 ppm ESC (max) : Differential Linearity 0.2 ppm FSAY/*C (max) . Monatonieity Temp, Range -Option 0°6 10 +70°C : B.Option “85°C 10 1128°C . POWER SUPPLY (Vpn) ‘Operating Voltage (specifications guaranteod) +15V = 6% > Maximum Voitage Range 45V to 16V : Current 2.5mA (max) : Rejection Ratio 0.002% /% (max) : TEMPERATURE RANGE ‘Operating C-Option Tew 0 a Operating B-Option “55°C to #125°C : Storage 85°C 10 +150°C . Case Style 2epin double DIP > C-Option pase or cerame . B-Option ceramic : Nores: * Same as HS3120-2 1. The input coding is complementary binary if To is used 2. Digital input voltage must not exceed supply voltage or go below -0.5V 3. Ali strobes are level triggered: See TIMING DIAGRAM 44, Using the internal feecback resistor ond an external opamp 5. The output leakage current will create an offset voltage at the external opamps output. It doubles every 10°C temperature increase 6. Delay times are tvice the amount shown at Ta = *125°C 144

SSIENMENTS APPLICATIONS INFORMATION [Pin | FUNCTION Connection Diagram, Unipolar Operation [1 | __ FB, Feedback Bipolar Operation , 402 nee vv [2 | __LOTR, Ladder Termination [rove [voos [3 [__ Fag, Feedback Bipolar Operation [4 _|___Vrer. Reference Voltage Input Fey Fos [5] Fy, Feedback, Unipotar/Bipoler ' ‘or 4 [6] —~To1. Current out into virwal ground pita = 5 Toz, Current outeomplement of [oy INPUTS Your [8 | ___Vss, Ground, Analog and DAC Register H [rae | 1 [9 [it 1, MSE i [Fes | - t [70 [ sez j co to sss [13 | HBEO [4 ttt ¥ Fe :

16 LoAco

[a7 Bigg ]__enneetion Diagram, Bipolar Operation [48] Bie 10 Vaer: SA-+ 15 [19 | eitt1 [voor ]voo+ [20 siet2 [21 |__LOAG, Transfers data from input to DAC register 9 [22] EE, Chip Enable, active tow ! el [23], Bit 12 to Bit 9 Enable > o ITAL [24 | ___MBE, Bit 8 to Bit 5 Enable eats o vour [25 | ___HBE, Bit 4 to Bit 1 Enable H 5 + [26 | Vpz, Supply Anaiog and DAC Register ! Vssi, Ground input latches 4 lez _| [28] Wop. Supply input latches a NOTE: Pins and 27 and pins 26 and 28 must be connected Go set externally m0 oy MECHANICAL wee 0 > 0 tor view vec L vour! 91 toaco = Ay, a. brat sai Aa. Lrastacn Connection Diagram, Bipolar Operation (for applications where bipolar offset temperature drift (~ 10 ppm/°C) is not critical)

7 NOTE: To maintain specified linearity, external amplifiers must be

th A zeroed. This is best done with Ver set to 2e°0 ond, won mse Unipolar: load the DAC register with all bits et zero and adjust Rog for Vout ~ OV Bipolar: foad the DAC register with 10. ..0 (MSB =1) and set Rosa for Vour 1 = OV. Then set Rost for

005 TRANSFER FUNCTION (N=12)

™ BINARY INPUT | UNIPOLAR OUTPUT] BIPOLAR OUTPUT — = L. -Vaee 72728) [-Vrer (2-101) o17 0.05 0.610 F [ot | -Vaee 2-28) | Var 2) t 0.006 909.900 [vnc 08s. {o82) ats 201 yp io.25)"¥" CONNECTIONS Unipolar Operation: Connect 1p and FB} os shown in diagram, Tie log (Pia 7), FBg (Pin 3), FBa, (Pin 1) all to Ground (Pin BI Bipolar Operation: Connect 193, To2, FB1, FB3, FBg as shown in diagram Tie LOTR 0 Lo Grounding Connect all GRO to system analog ground and tie this to digital ground Note Al unused input pins must be grounded. 145

BIPOLAR OFFSET ADJUST (external) ORDERING INFORMATION as asv “coe on HS 31200-0 ‘Double Buffered 12.Bit HDAC, Commercial Mg 31202 Double Butlred 128 MDAC. Commercial 18312080 Double Buttered 12 MOAC. MILSTD-88C HS 312082 Double Butored 12.64 MDAC. MIL STO S83C m ADJUSTMENT CAUTION: ESD (Electro-Static Discharge) sensitive de- RAMGE 02% vice. Permanent damage may occur when unconnected qOi01 devices are subjected to high energy electrostatic fields. Unused devices must be stored in conductive foam or NOTE: Excel onomps have fo be eresbatre ne igler oft ys, Protective foam should be discharged to the destin " ation socket before devices are removed. Devices should CONTROL LOGIC be handled at static safe workstations only. Unused dig- e ital inputs must be grounded or tied to the logic supply voltage. Unless otherwise noted, the supply voltage at any digital input should never exceed the supply voltage by MBE TO INPUT REGISTER BIT 1. BIT 6 more than 0.5 volts or go below ~0.5 volts. If this condition cannot be maintained, limit input current on digital in- woe TOMPUTAEGISTER BITS BIT 8 puts by using series resistors or contact Hybrid Systems for technical assistance. bse oINPUT REGISTER BIT 9- BIT 12 ‘Specifications subject to change without notice. NOTE: The transfer trom input register to OAC register can be performed without Enabling Chip. STROBE LOGIC ‘data latched (held) data changing (transfer) TIMING DIAGRAM neur SY RY RR RR aes = 42-017 io i ty ne Lee ri || ela ie wee te m1 noe toac rs ourrut iS ro TIME AXIS NOT TOSCALE. ALL STROBES ARE LEVEL TRIGGERED, ty: Dat Setup Time Time data must be sae bare strobe toyte enable LDAC! goe 00" y(n) = 250 mec tg Strobe Width, tp min) = 280 ge. (CE, LOE, MBF, MBE, LOACI. {gr Hold Tie, Tie dta must be stable aftr stvabe goes 19 "0 ty = Oni tq: Delay om LDAC t Output tg = 200 nee. NOTE: Minimum common actie time for CE and any byte enables 250 me. 146