HDM-R1 ZORAN | Alldatasheet

Document overview

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Technical content

Features

  • LCD Display Processors
  • Digital TVs
  • Set-top boxes
  • DVD recorders
  • A/V Receivers
  • Any IC requiring the HDMI receive function Integrated Circuit Applications Digital Link
  • Synthesizable RTL code (Verilog)
  • Bit accurate C model
  • Synopsis synthesis scripts
  • Test bench with suite of test cases Analog Phy
  • GDS2
  • CDL Netlist for LVS/DRC
  • Verilog behavioural model (without timing)
  • Synopsys .lib model
  • Cadence .lef file (for integration and top level Place and Route).
  • Cadence .tlf file (timing information for top level place and route)
  • Layout recommendations/guidelines
  • Package/PCB design recommendations Deliverables The HDM-R1 IP Core includes reference software which facilitates the implementation, verification and validation of the core. It can also be used as an example for further software system development. Provided as source code, the reference software is highly portable and can easily be adapted to any specific system. The reference software consists of the following functions:
  • Hardware configuration and system interface
  • Authentication Reference Software DVD Mobile Digital TV Imaging IP Cores Driving the Digital LifestyleDriving the Digital Lifestyle 02/06 -IN HDMR1 HDM-R1 HDMI Receiver IP Core

Driving the Digital LifestyleDriving the Digital Lifestyle For more information, contact Zoran's Sunnyvale office or the office nearest you: HDM-R1 HDMI Receiver IP Core 02/06 - IN HDMR1 © Copyright 2006 Zoran Corporation. All rights reserved. Zoran, the Zoran logo and HDM-R1 are trademarks of Zoran Corporation. All other brand product names and company names are trademarks of their respective owners. The information in this document is believed to be reliable. However, Zoran Corporation makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. Zoran Corporation does not guarantee that the use of any information contained herein will not infringe upon patent, trademark, copyright, or rights of third parties. Zoran Corporation reserves the right to make changes in the product and/or specifications, or both, presented in this publication at any time without notice. HDM-R1 Block Diagram Audio Output Interface PHY TMDS Decoder Differential Recievers x4 and PLL LINK Re giste r File HDCP RAM INFO - PAGE_A RAM INFO - PAGE_B RA M RAM Interface Configur ation and Cont rol Exte rn al Ra m Host Contr oll er Data/Addr/Ctrl and Clk/Reset rst video clk ch0 ch1 ch2 clk LINK and PHY C or e TERC4 Decoder Double Bu ffe rs packets HDCP Audio Frame Test Generator Da ta Islan d De cod er Au di o Buffer Audio Mute Video Path Video Convert Video Timing Co ntr o l FSM Au di o Clo ck Generator Infoframe Decoder Video Output Interface audio video Shanghai, China Zoran China Office Tel: 86-21-6469-9799 Fax: 86-21-6427-0545 Shenzhen, China Zoran China Office Tel: 86-755-8281-5777 Fax: 86-755-8322-0889 Hong Kong Zoran Asia Pacific Ltd. Tel: +852-2620-5838 Fax: +852-2620-5238 Israel Zoran Microelectronics Ltd. Tel: +972-4-8545-777 Fax: +972-4-8551-550 Japan Zoran Japan Office Tel: +81-3-5475-1051 Fax: +81-3-5475-1053 Korea Zoran Korea Office Taiwan Zoran Taiwan Office Te l : +886-2-2659-9797 Fax: +886-2-2659-9595