FRAME-IT-1 ZORAN | Alldatasheet
Document overview
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- PDF pages: 2
Technical content
Features
- LCD controllers
- LCD-TV
- PDP-TV
- Projector TV Systems
- Progressive output CRT-TV
- Any IC requiring progressive video output Integrated Circuit Applications
- Compilable Verilog source code
- Bit-accurate, cycle-accurate C++ model
- Synopsis synthesis scripts
- Test input files
- Documentation
- VIP-II FPGA demonstration system available Deliverables Frame-It-1 Video Deinterlacer Block Diagram DVD Digital Camera Digital TV Imaging IP Cores Driving the Digital Lifestyle Driving the Digital Lifestyle Interlaced Video Input Line Buffers Optional Line Buffers Field Buffer Control Field Buffers Input Control Motion Detector Gradient Detector Adaptive Bob- Weave Output Control Deinterlaced Video Output Frame-It-1 Video Deinterlacer
Frame-It-1-PB-1.0 For more information, contact Zoran's Sunnyvale office or the office nearest you: Canada Zoran Toronto Lab Tel: (416) 690-3356 Fax: (416) 690-3363 China Zoran China Office Tel: 86-755-83993777 Fax: 86-755-83220889 Hong Kong Zoran Asia Pacific Ltd. Tel: +852-2-620-5838 Fax: +852-2-620-5238 Israel Zoran Microelectronics Ltd. Tel: +972-4-8545-777 Fax: +972-4-8551-551 Japan Zoran Japan Office Tel: +81-03-5475-1051 Fax: +81-03-5475-1053 Korea Zoran Korea Office Taiwan Zoran Taiwan Office Tel: +886-2-2659-9797 Fax: +886-2-2659-9595 Product Brief Driving the Digital Lifestyle Driving the Digital Lifestyle Frame-It-1 Video Deinterlacer Logical Pinout Frame-It-1 Video Deinterlacer ext_clk ext_reset_1 reg_addr[7:0] reg_rd_wtn reg_rdy reg_wt_data[7:0] clk clk_x2 (optional)* reset_1 enable (optional) hactive_in vactive_in field proscan240 repeat_first_field no_time_advanceà y_prev_in[7:0] c_prev_in[7:0] y_curr_in[7:0] c_curr_in[7:0] y_next_in[7:0] c_next_in[7:0] c_curr_lbuf_A_rdata[7:0] c_curr_lbuf_B_rdata[7:0] c_miss_lbuf_rdata[7:0] k_prev_lbuf_rdata[7:0] m_top_lbuf_rdata[7:0] k_prev_fbuf_rdata[7:0] y_prev_lbuf_A_rdata[7:0] y_prev_lbuf_B-rdata[7:0] y_curr_lbuf_A_rdata[7:0] y_curr_lbuf_B_rdata[7:0] y_next_lbuf_A_rdata[7:0] y_next_lbuf_rdata[7:0] Frame-It-1 Video Deinterlacer Pinout *Required for Double-Rate Outputs Required for Enabled Flops àReserved for Future Use reg_ack reg_rd_rdy reg_rd_data[7:0] hactive_out vactive_out y_top_out[7:0] c_top_out[7:0] y_bot_out[7:0] c_bot_out[7:0] yc_lbuf_rrst yc_lbuf_wrst y_prev_lbuf_A_ren y_prev_lbuf_A_wen y_prev_lbuf_B_ren y_prev_lbuf_B_wen y_prev_lbuf_wdata[7:0] y_curr_lbufA_ren y_curr_lbuf_A_wen y_curr_lbuf_B_ren y_curr_lbuf_B_wen y_curr_lbuf_wdata[7:0] y_next_lbuf_A_ren y_next_lbuf_A_wen y_next_lbuf_B_ren y_next_lbuf_B_wen y_next_lbuf_wdata[7:0] c_curr_lbuf_A_ren c_curr_lbuf_A_wen c_curr_lbuf_B_ren c_curr_lbuf_B_wen c_curr_lbuf_wdata[7:0] c_miss_lbuf_ren c_miss_lbuf_wen c_miss_lbuf_wdata[7:0] k_prev_lbuf_rrst k_prev_lbuf_ren k_prev_lbuf_wrst k_prev_lbuf_wen k_prev_lbuf_wdata[7:0] m_top_lbuf_rrst m_top_lbuf_ren m_top_lbuf_wrst m_top_lbuf_wen m_top_lbuf_wdata[7:0] k_prev_fbuf_rrst k_prev_fbuf_ren k_prev_fbuf_wrst k_prev_fbuf_wen k_prev_fbuf_wdata[7:0] dbg_dmux[7:0]