HDJD-J822-SCR00

HDJD-J822-SCR00 AVAGO | Alldatasheet

Document overview

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Technical content

Features

• –40 to 85°C operation
• I2C serial interface
• Robust CMOS-Schmitt input
• CMOS/TTL compatible output
• Multiple color input formats – CIE XYZ, Yxy, Yu’v’ and RGB
• 3-channel analog interface to color sensor – X, Y and Z channels
• 3-channel 12-bit PWM output – Red, Green, and Blue LED channels
• Internal computation of calibration data
• Internal clock generator
• Internal reference voltage generator
• Error flag output
• External push-button interface
• Only passive components required externally

Applications

• Backlighting
• General illumination
• Mood/accent lighting
• Color context sensitive appliances AVAGO TECHNOLOGIES’ PRODUCTS AND SOFTWARE ARE NOT SPECIFICALL Y DESIGNED, MANUFACTURED OR AUTHORIZED FOR SALE AS PARTS, COMPONENTS OR ASSEMBLIES FOR THE PLANNING, CONSTRUCTION, MAINTENANCE OR DIRECT OPERATION OF A NUCLEAR FACILITY OR FOR USE IN MEDICAL DEVICES OR APPLICATIONS. CUSTOMER IS SOLEL Y RESPONSIBLE, AND WAIVES ALL RIGHTS TO MAKE CLAIMS AGAINST AVAGO TECHNOLOGIES OR ITS SUPPLIERS, FOR ALL LOSS, DAMAGE, EXPENSE OR LIABILITY IN CONNECTION WITH SUCH USE. ESD WARNING: Standard CMOS handling precautions should be observed to avoid static discharge.

SYMBOL MIN. NOM. MAX. A 0.093 0.099 0.104 A1 0.004 0.008 0.012 A2 0.088 0.094 0.100 B 0.013 0.016 0.020 C 0.0090 0.0100 0.0125 D 0.599 0.606 0.613 E 0.292 0.296 0.299 e 0.050 BSC. H 0.394 0.402 0.419 h 0.010 0.015 0.019 L 0.016 0.033 0.050 alpha 0° 5° 8° Part Numbering System H D J D - J 8 2 2 - X X X X X Option 00: Default Packaging Type R: Tape and Reel Standard Pack Product Packaging SC: SOIC E H PIN 1 INDICATOR D Be A SEATING PLANE C h x 45° 0° MIN. SEE DETAIL A DETAIL A 7° TYP. alpha° L PARTING LINE Package Dimensions

DIO Digital bi-directional pin Pinout of HDJD-J822 Color Management System Feedback Controller Top View 24-Pin SOIC XRST P1 P24 AVDD SLEEP P2 P23 SENSE_X CLK_SEL P3 P22 SENSE_Y A1 P4 P21 SENSE_Z A0 P5 P20 VREF_EXT SDA P6 P19 ROSC SCL P7 P18 AVSS TEST P8 P17 ERR_FLAG COLOR P9 P16 PWM_R BRIGHT P10 P15 PWM_G CLK_EXT P11 P14 PWM_B DVDD P12 P13 DVSS Pin Descriptions XRST (Pin 1) Global, asynchronous, active-low system reset. When as- serted low, XRST resets all registers. Minimum reset pulse low is 10 µs and must be provided by external circuitry. SLEEP (Pin 2) When asserted high, SLEEP puts the device into sleep mode. In sleep mode, all analog circuits are powered down and the clock signal is gated away from the core logic. CLK_SEL (Pin 3) CLK_SEL is used to select between internal and exter - nal clock modes. Internal clock mode is selected when CLK_SEL=0 and external clock mode is selected when CLK_SEL=1. A1, A0 (Pin 4, Pin 5) A1 (MSB) and A0 (LSB) define the lower two bits of the I2C slave address. SDA (Pin 6) The SDA pin is the I2C data I/O pin. SDA is a bi-directional pin. The I/O direction is defined by an internal signal generated by the I2C interface block. SCL (Pin 7) The SCL pin is the I2C clock pin. TEST (Pin 8) Connect to digital ground (DVSS). Pin Name Type Pin Name Type

1 XRST DI 13 DVSS DP

2 SLEEP DI 14 PWM_B DO

3 CLK_SEL DI 15 PWM_G DO

4 A1 DI 16 PWM_R DO

5 A0 DI 17 ERR_FLAG DO

6 SDA DIO 18 AVSS AP

7 SCL DI 19 ROSC ANA

8 TEST DI 20 VREF_EXT ANA

9 COLOR DI 21 SENSE_Z ANA

10 BRIGHT DI 22 SENSE_Y ANA

11 CLK_EXT DI 23 SENSE_X ANA

12 DVDD DP 24 AVDD AP

DP Digital supply/ground pin ANA Analog interface pin AP Analog supply/ground pin COLOR, BRIGHT (Pin 9, Pin 10) COLOR and BRIGHT are button interface pins. Asserting COLOR high with BRIGHT low makes the output color go up a color selection ‘slider. ’ To effect a direction change, COLOR and BRIGHT must be asserted simultaneously for at least 0.1 second. Now, asserting COLOR with BRIGHT low makes the output color go down the color selection slider. Button brightness control follows a similar procedure. Asserting BRIGHT high with COLOR low increases or de - creases brightness depending on the direction. To effect a direction change, COLOR and BRIGHT must be asserted simultaneously for at least 0.1 second. (Refer to Applica- tion Note 5070 for color selection ‘slider. ’) CLK_EXT (Pin 11) CLK_EXT is the external clock input pin. Users can choose to use an external clock instead of the internal clock gen- erator by setting CLK_SEL to high. PWM_R, PWM_G, PWM_B (Pin 16, Pin 15, Pin 14) The PWM_R, PWM_G, and PWM_B output pins drive the external LED drivers that drive the LED arrays. Typically PWM_R drives only the red LEDs, PWM_G drives only the green LEDs and PWM_B drives only the blue LEDs. They are the output enable signals of the red, green and blue LED drivers. So, they control the on-time duration of the LEDs. The assertion level of the PWM* signals can be toggled by the user to support both active-low and active-high enable input pins at the LED driver side. This is done by configuring the PWML bit of register CONFIG1.

Input Color Format CIE XYZ, Yxy, Yu’v’ and RGB (illuminant E) Input Sensor Signal 0 to 2.5 V (typical configuration) Minimum Dynamic Range Sensor output > 500 (ADC output code, each channel) during calibration Output PWM Frequency 610 Hz nominal (typical configuration) Output PWM Resolution 12 bits Error Flag Assertion on ERR_FLAG pin indicates an error condition Device Address Control Upper 5 bits 10101 binary, lower 2 bits defined by A1:A0 pins in that order Supply 5 V digital, 5 V analog (nominal) I/O Schmitt-CMOS input and CMOS/TTL compatible output ERR_FLAG (Pin 17) The ERR_FLAG pin is asserted high when an error condi- tion is detected. The user can determine the type of error by reading the ERROR register. The error conditions are described in the ‘High Level Description’ section. SENSE_X, SENSE_Y, SENSE_Z (Pin 23, Pin 22, Pin 21) The SENSE_X, SENSE_Y and SENSE_Z pins are analog input pins which are tied to the X-channel, Y-channel and Z-channel of the photosensor output respec - tively. An averaging filter is placed in between the sensor output and the SENSE_X, SENSE_Y and SENSE_Z pins. The filter is typically a 68 kΩ -1 µF single-pole low-pass filter. VREF_EXT (Pin 20) The VREF_EXT pin is an analog input pin, which provides an external reference voltage for the ADC. Typically, users will use the internal reference generator to operate the ADC. However, in specific application conditions, an ex - ternal reference may be required. The external reference is enabled by setting the VREFS bit of register CONFIG1 high. ROSC (Pin 19) A 68 kΩ precision 1% resistor is connected from the ROSC to AVSS pin for use by the internal oscillator. In external clock mode, ROSC can be left floating. (Refer to Applica- tion Note 5070 for resistor selection.) DVDD, DVSS, AVDD, AVSS (Pin 12, Pin 13, Pin 24, Pin 18) HDJD-J822 has separate power ground nets for the ana- log and digital section. A star connection from a central power source is recommended when designing the wir- ing to these supply pins. DVDD = Digital positive supply DVSS = Digital ground AVDD = Analog positive supply AVSS = Analog ground

SENSE_X CLK_SEL SENSE_Y SENSE_Z VREF_EXT MODE SELECT VREF SENSOR PROGRAMMABLE AMPLIFIER REFERENCE VOLTAGE ADC MUXCLOCK SDA ROSC SCL AVSS TEST ERR_FLAG COLOR PWM_R BRIGHT PWM_G CLK_EXT PUSH_BUTTON DUTY FACTOR SYSTEM CONTROLLER CONTROL SIGNALS PWM_B PWM GENERATOR DVDD DVSS INTERNAL OSCILLATOR COLOR CONTROLLER INTERNAL REGISTERS CONTROL CONFIG DATA: SETPOINT CALIBRATION I2C INTERFACE CONTROL Block Diagram HDJD-J822 Block Diagram Description Function Description Programmable If the sensor output is not within the required dynamic range, the amplifier’s gain can be Amplifier changed from unity to 2 to boost the sensor signal. ADC Analog-to-digital converter. Converts the sensor signal from analog to digital. VREF Reference voltage generator. Provides a stable voltage level to the ADC. Can be bypassed with an external reference generator. Internal Oscillator Generates a clock signal for the logic circuits. Can be bypassed with an external clock signal. Mode Select The device operation mode (normal, sleep, internal/external clock) is determined by the status of the SLEEP and CLK_SEL pins. I2C Interface Control Serial interface controller. Manages the I2C communications protocol. Internal Registers The primary method in which the device is configured. Contains a bank of registers. Each bit is mapped to a specification, function or mode of operation. The internal registers also contain a range of calibration registers. (Refer to the ‘High Level Description’ section and the Application Note 5070 for calibration procedures). Color Controller Contains the color processing algorithms that operate on the sensor data. The algorithms correct the PWM output duty factors if there is a mismatch between the desired color and actual color produced. Converts the input color coordinates into an internally understood format. Default input format is CIE RGB (illuminant E). PWM Generator Receives the duty factor values from the Color Controller and generates 3 PWM signals. System Controller Performs internal functions – housekeeping, interfacing between blocks, generating control signals, etc.

A hardware reset (by asserting XRST) should be per - formed before starting any operation. It is assumed that factory calibration was performed prior to deployment of HDJD-J822. Calibration is discussed at the end of this section. The user controls and configures HDJD-J822 by pro - gramming a set of internal registers. The registers are programmed through the I2C protocol – a standard, syn- chronous, serial interface. The registers define operation modes such as sensor slope, reference voltage selection, color space format, PWM assertion level, etc. Selection between internal and external clock can only be made through pin setup. A typical set-up would be:

• Positive sensor slope
• Internal reference voltage
• 100 Hz (nominal) sensor sample rate
• 610 Hz PWM (nominal)
• Active-high PWM output
• 2.5 MHz (nominal) internal oscillator HDJD-J822 resets into an “idle” mode and the PWM out- puts are held low. If the PWM assertion level bit (PWML) of register CONFIG1 is changed to high, the PWM outputs will then be held high. However, since the reset condition for that register bit is low, HDJD-J822 always resets with the PWM outputs held low. The next step after setting up the device is to write the calibration data to the calibration registers (address 0x8A to 0xA8). The calibration data is typically stored in an exter- nal non-volatile memory. After writing the data, the user can set the PWM enable bit (PWME) of register CTRL1 to begin normal operation. The operation begins with the processor taking in the tri- color sensor’s digitized readings from the internal ADC. That data is compared to the desired color/brightness setting. The PWM duty factor is adjusted in response to any error signal generated by that comparison operation. The user can change the color/brightness setting at any time by writing to the appropriate device registers (ad - dress 0xE8 to 0xED during normal operation). The feedback and processing operation is repeated at a rate of 100 Hz (nominal). The PWM signal is applied to the LED drivers and controls the on-time duration of the red, green and blue LEDs. The user can input the desired color/brightness in a va - riety of color formats such as CIE XYZ, Yxy, Yu’v’ and RGB (illuminant E). There are three indicators in register ERROR that monitor the status of the color management system. Refer to Ap- plication Note 5070. Factory calibration is needed at a system level to create a ‘snapshot’ of the initial conditions of the system. The color management algorithm references the snapshot data. In effect, the calibration data trims out variation in the en - tire signal chain from LEDs to sensor to filter to ADC. The calibration discussion below is brief. Refer to Application Note 5070 for detailed calibration procedures. First, the device is put into “open loop” mode by setting the OPMD bit of register CONFIG1 to high. In open loop mode, the color management algorithm is turned off. Second, all LEDs are switched on to maximum PWM. Dur- ing this, the ADC output is read out to check if the sensor output is within the dynamic range of the system i.e., 400 < pass < 800. An optional internal 2x gain (1) can be se - lected if the ADC reading is less than 400. This procedure is performed for each sensor channel. Next, only the RED LEDs are switched on. An external camera must be set up to capture the CIE co-ordinates (preferably XYZ) of the RED LEDs. The scaled XYZ readings are then sent to the RED LED camera calibration registers (address 0xE8 to 0xED during calibration mode). Next, the GSSR bit of register CTRL2 is set to capture the sensor readings of the RED LEDs. The readings are stored in the ADC reading registers (SENSOR_ADCZ, SENSOR_ADCY, SENSOR_ADCX registers). The user must read those reg- isters and transfer them to the RED LED sensor calibration registers (address 0xFA to 0xFF). This is repeated for GREEN and BLUE LEDs. The RCAL bit of register CTRL2 is then set, after which HDJD-J822 will compute the 31 bytes of calibration data CAL_DATA0 to CAL_DATA30 (2) The 2 pieces of calibration data is noted as (1), and (2) above. The user will need to read them from the device registers via I2C and store them in an external non-vola - tile memory. They will have to be written to the appropri- ate registers prior to the start of normal operation, and should be part of the system boot-up sequence.

Absolute Maximum Ratings (Note 1 & 2) Parameter Symbol Minimum Maximum Units Notes Storage Temperature TSTG_ABS -65 150 °C Digital Supply Voltage, DVDD to DVSS VDDD_ABS -0.3 6.0 V Analog Supply Voltage, AVDD to AVSS VDDA_ABS -0.3 6.0 V Input Voltage VIN_ABS -0.3 VDDD + 0.3 V All I/O pins Solder Reflow Peak Temperature TL_ABS 260 °C Latch-Up Current IL_ABS -100 100 mA Human Body Model ESD Rating ESDHBM_ABS 2 kV All pins, human body model MIL883 Method 3015 Machine Model ESD Rating ESDMM_ABS 200 V Recommended Operating Conditions Parameter Symbol Minimum Typical Maximum Units Notes Free Air Operating Temperature TA -40 25 85 °C Digital Supply Voltage, DVDD to DVSS VDDD 4.5 5 5.5 V Analog Supply Voltage, AVDD to AVSS VDDA 4.5 5 5.5 V HIGH Level Output Current IOH 3 mA LOW Level Output Current IOL 3 mA External Clock Frequency fCLK_EXT 1.8 2.5 3.3 MHz ROSC Resistor Rosc 68 kΩ (Note 3) VREF_EXT Analog Input Pin Input Voltage VREF_EXT 2.5 4.0 V SENSE_* Input Pins Input Voltage VSENSE 0.0 VREF V (Note 4) VDDD or VDDA Minus SENSE_* VDIFF_SENSE 1.0 V (Note 5) Internal Reference Nominal Voltage VREF_INT 2.45 2.5 2.55 V (Note 6) Internal Oscillator Nominal Frequency fCLK_INT 1.8 2.5 3.3 MHz (Note 6) with Rosc = 68 kΩ Internal Oscillator Frequency Variation -5 5 % over Temperature with Rosc = 68 kΩ

Over Recommended free air Operating Temperature Range, and V DDD = V DDA = 4.5 V/5 V/5.5 V (unless otherwise specified). Parameter Symbol Conditions Minimum Typical Maximum Units Minimum HIGH Level Input Voltage VIH 0.7 VDDD VDDD V (Note 7) Maximum LOW Level Input Voltage VIL 0 0.3 VDDD V (Note 7) Digital Input Pin Schmitt +ve Threshold VIPOS 0.8 VDDD V (Note 7) Digital Input Pin Schmitt -ve Threshold VINEG 0.2 VDDD V (Note 7) Digital Input Pin Schmitt Hysteresis VIHYS 1.0 V (Note 7) (Note 8) Minimum HIGH Level Output Voltage VOH VIN = VIH or VIL 0.9 VDDD VDDD V (Note 9) IOH = 3 mA Maximum LOW Level Output Voltage VOL VIN = VIH or VIL 0 0.4 V (Note 10) IOL = 3 mA Dynamic Digital Supply Current IDDD_DYN CLK_SEL=1 4 mA (Note 11) fCLK_EXT = 3.3 MHz Sleep-Mode Digital Supply Current IDDD_SLP 15 µA Standby Digital Supply Current IDDD_STNBY CLK_SEL=1 15 µA Dynamic Analog Supply Current IDDA_DYN CLK_SEL=1 3 mA (Note 11) fCLK_EXT = 3.3 MHz Sleep-mode Analog Supply Current IDDA_SLP 15 µA Standby Analog Supply Current IDDA_STNBY CLK_SEL=1 15 µA

1. The “Absolute Maximum Ratings” are those values beyond which damage to the device may occur. The device should not be operated at these

mended Operating Conditions” table will define the conditions for actual device operation.

1. Unless otherwise specified, all voltages are referenced to ground.
2. A 1% precision resistor is recommended. This resistor is tied from the ROSC pin to ground.
3. VREF = VREF_INT in internal reference configuration. VREF = VREF_EXT in external reference configuration.
4. The voltage level at any of the SENSE_* pins must be lower than VDDD or VDDA (whichever is lower) by at least VDIFF_SENSE volts.
5. TA = 25°C. Room temperature.
6. Applies to all DO pins. SDA is an open-drain NMOS. Minimum VOH depends on the pull-up resistor value.
7. Applies to all DO and DIO pins.
8. Dynamic testing is performed when the IC is operating in a mode representative of typical operation.
9. A hold time of at least 300ns must be provided internally by a device for the SDA signal ( with reference to the minimum VIH of SCL) to bridge

the undefined region of the falling edge of SCL. Figure 1. I2C bus timing waveforms.

START CONDITION STOP CONDITION SDA SCL Notes on Sampling Frequency and PWM Output Fre- quency The sampling frequency, f SAMP, which is the frequency at which HDJD-J822 samples the tricolor photosensor, is related to the system clock frequency, f CLK. The output PWM frequency, fPWM, is also related to fCLK. The system clock is sourced from either the internal oscillator or an external clock. Calculation example: fCLK = 2.5 MHz (nominal) fSAMP = fCLK/25087 = 100 Hz (nominal) fPWM = fCLK/4095 = 610 Hz (nominal) The internal oscillator frequency varies from part-to-part but it will not vary significantly during operation. Register Description The user controls and configures HDJD-J822 by program- ming a set of internal registers, through the I2C protocol. Refer to Application Note 5070 for programming guide and register description. I2C Interface

Description

The programming interface to HDJD-J822 is a standard 2-wire serial bus, which follows the I2C data transmission protocol. This protocol defines a transmitter as a device that sends data to the bus and a receiver as a device that receives data from the bus. A master is a device that initiates a data transfer on the bus, generates the clock signal and terminates the data transfer. A device addressed by the master is called a slave. Both master and slave can act as a transmitter or a receiver but the master controls the direction for data transfer. The bus consists of a serial clock (SCL) and a serial data (SDA) line. Both lines are bi-directional and connected to the positive power supply through a pull-up resistor. When the bus is free, both lines are HIGH. HDJD-J822’s I2C bus interface always operates as a slave transceiver in standard mode. Standard mode has a data transfer rate of up to 100 kbit/s. START/STOP Condition To begin an I 2C data transfer, the master must send a unique signal to the bus called a START condition. This is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH. The master terminates the transfer by sending another unique signal to the bus called a STOP condition. This is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH. The bus is considered to be busy after a START (S) condi- tion. It will be considered free a certain time after the STOP (P) condition. The bus stays busy if a repeated START (Sr) is sent instead of a STOP condition. The START and repeated START conditions are function- ally identical. Figure 2. START/STOP condition.

CH_X CH_Y CH_Z SENSOR AVDD EN_RED EN_GREEN EN_BLUE LED DRIVER DVDD CONTROL BUS 0 V 2.5 V SENSE_* vref = internal = 2.5 V XRST CLK_EXT CLK_SEL SDA SCL TEST COLOR BRIGHT PWM_R PWM_B ERR_FLAG SENSE_X SENSE_Y SENSE_Z VREF_EXT ROSC DVDD PWM_G DVSS AVDD AVSS SLEEP DVDD LPF LPF LPF LPF 68 KΩ, 1 µF PASSIVE LOW PASS FILTER 68 KΩ CH_X CH_Y CH_Z SENSOR AVDD EN_RED EN_GREEN EN_BLUE LED DRIVER DVDD CONTROL BUS 0 V 2.5 V SENSE_* vref = internal = 2.5 V DVDD XRST CLK_EXT CLK_SEL SDA SCL TEST COLOR BRIGHT PWM_R PWM_B ERR_FLAG SENSE_X SENSE_Y SENSE_Z VREF_EXT ROSC DVDD PWM_G DVSS AVDD AVSS SLEEP DVDD LPF LPF LPF LPF 68 KΩ, 1 µF PASSIVE LOW PASS FILTER 68 KΩ Application Diagrams Typical Operation* Refer to Application Note 5070 for implementation de - tails. *The SDA pull-up is only required at system level. It is shown in the diagram for reference only. Button Mode Operation*

0.3 ± 0.1 4 ± 0.1 *SEE NOTE 1 2 ± 0.1 *SEE NOTE 6 12 ± 0.1 R0.3 MAX. SECTION A-A R0.5 TYP. ∅1.5 ± 0.1 A0A0 = 10.9 mm ± 0.1 B0 = 16.0 mm ± 0.1 K0 = 3.0 mm ± 0.1 11.5 ± 0.1 *SEE NOTE 6 1.75 ± 0.1 A A 24 ± 0.3 Notes: 1. 10 sprocket hole pitch cumulative tolerance is ± 0.2mm. 2. Camber not to exceed 1 mm in 100 mm. 3. Material: Black Conductive Advantek Polystyrene. 4. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket. 5. K0 measured from a plane on the inside bottom of the pocket to the top surface of the carrier. 6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole. 7. Dimensions are in millimeters. Package Tape and Reel Dimensions

24 Pin Wide Body Carrier Tape

For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0211EN AV02-0494EN - June 14, 2007 W A B C D E F LEGEND W – Width A – Shaft Diameter B – Hub Diameter C – Window Size D – Total Reel Diameter E – Shaft Key Hole F – Reel Thickness Notes: 1. Material: Polystyrene (Blue). 2. Antistatic coated. 3. Flange warpage: 3 mm maximum. 4. All dimensions are in millimeters. 5. ESD – Surface resistivity: 105 to 1011 ý/sq. D330 P5045 W24/4 PEAK W F E PART NO. (VARIABLE) SIZE (VARIABLE) A B C D Peak Fixed Reels AVAGO TECHNOLOGIES’ PRODUCTS AND SOFTWARE ARE NOT SPECIFICALL Y DESIGNED, MANUFACTURED OR AUTHORIZED FOR SALE AS PARTS, COMPONENTS OR ASSEMBLIES FOR THE PLANNING, CONSTRUCTION, MAINTENANCE OR DIRECT OPERATION OF A NUCLEAR FACILITY OR FOR USE IN MEDICAL DEVICES OR APPLICATIONS. CUSTOMER IS SOLEL Y RESPONSIBLE, AND WAIVES ALL RIGHTS TO MAKE CLAIMS AGAINST AVAGO TECHNOLOGIES OR ITS SUPPLIERS, FOR ALL LOSS, DAMAGE, EXPENSE OR LIABILITY IN CONNECTION WITH SUCH USE. ESD WARNING: Standard CMOS handling precautions should be observed to avoid static discharge.