HD63701X0

HD63701X0 HITACHI-METALS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 40

Technical content

H D63 7 BOo1 xo (Limiting Supplies. For Development Only.) The HD63701X0 is a high performance 8-bit CMOS single chip micro- ‘computer unit (MCU) which, including 4k bytes of EPROM, is object co compatible i te HDODOIXO HOBaTONxOG, HOBSTAGIXOC, ‘The HD63701X0 contains 4k bytes of EPROM, 192 bytes of RAM, LO ‘serial communication interface and 53 parallel 1/0 pins in addition to KO CPU. It includes functions of halt, memory ready, iow speed access and ee hi releasing external bus for system expansion. r @ at ‘The HD 63701 XO is available in a hermetically scaled 64-pin shrunk a At ‘ceramic package which includes a glass window that allows for program- ee ull ming and EPROM crasure in the same way as 2732 type EPROM. <i nt © Instruction Set Compatible with the HD6301X0 and 6801 1 © 4k Bytes of EPROM icompatibie with 2732A type! © 1928ytes of RAM (00-848) © 53 Paraliel /O Pins

24 V0 Common Pins (Port 2, 2, 61

21 Output Pins (Port 1, 4, 7)

8 Input Pins (Port 5) © PIN ARRANGEMENT

© Driving Darlington Tansistor (Port 2, 6) : © 16-bit Programmable Timer xe gs Fae, Input Capture Register x 1 Rolla ee Free Running Counter x 1 MP, Gl Ps Output Compare Register x 2 MP Gl Bars, © B-bit Reloadabie Timer Fe Gy ar, External Event Count STBY Oy APs, Spare Wave Generation mac Ps © Serial Communication Interface (SCI) "a ite Asynchronous Mode/Clock Synchronous Mode a Be

3 Tiansfor Formats (Asynchronous Mode) 3G Ps,

6 Clock Sources ro Ps

Memory Rey for Low Speed Memory Access te yoes701x0 fhm * Error-Detection (Address Error, Op-code Etrorb ae: | Bp © intorrupts—3 External, 7 Internal Ba | Be © Operation Mode a Br Mode 1~ Expanded a: api, {internal ROM Inhibited) atc Ear. MCU Mode [nee 2— Expanded (internal ROM Valid) Pa EP, Mode 3 Single-chip Mode ana Ev OE EPROM Mode Po ed Ear? © Up to 65k Bytes of Address Space ra Fae * Low Power Dissipation Mode a Bap? Sleep Dal bar. Standby Pe bars '& Minimum Instruction Execution Time — 0.5us ({=2.0MHz) | BaP. * Wide Operation Range Pe pari, 1=0.5 to 1.0MHz; HD63701X0 Par B P3Vce Vec=5V+10%|f=05 to 1.5MHz; HD637A01X0 $=0.5 to 2.0MHz; HD637B01X0 (op View) {Precautions on using EPROM On-chip Single-chip Micro- computer] (1) If the MCU is exposed to strong light especially a fluorescent lamp or the sunlight, EPROM data may be erased or the 8 NT ta coitarg ty Ibe PCs and MCU may malfunction by photocurrent. Therefore, after . oration nbler and C compiler software Brogramming is Suge that aptcaons whkh expos 2am we wh 6M PCs nd compan thevndg ent 'y require an opaqu ‘© Programming socket adapter for programming the . EPROM-on-chip device, (2) Do not rub the window with materials like plastics, or do not touch a charged body on the window. Electro static charge may adversely affect the functionality of the LSI. A conduc- tive opaque label, suggested above, is effective on distribut- ing charge equally @HITACHI 678 Hitachi America, Ltd. « Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 » (415) 589-8300

a _____HD63701.X0, HD637A01X0, HD637B01X0 ® BLOCK DIAGRAM i SEE 226 voce. |Ea) [Bales TH ree aT LT EHP inte patents aged Pot eorex) ag tT] lt [Fay tena i= mee . Pya'De BOs moles Le pao LE men te Par/Aro/EAro @uHITACHI Hitachi America, Ltd, « Hitachi Plaza © 2000 Sierra Point Pkwy. © Brisbane, CA 94006-1819 « (415) 589-8300 679

HD63701X0, HD637A01X0, HD637B01X0 = ABSOLUTE MAXIMUM RATINGS Hem Unit Supply Voltage 203~ 47.0 v Program Vortage [Vp v Input Voltege [Vin =0.3~Voot03 v Operating Temperature [Tow 0 c ‘Storage Temperature ~B5~ 1125 *c (ote) This product has protection circuits in input terminal from high static electricity voltage and high elec itd. Gut be caret not to apply Cvervotape more than mann rtingt fo thew high input impedance protection eects, To astae the normal operation, we recommend Vins Vout! Vss€ (Vin OF Vout! Voc- = ELECTRICAL CHARACTERISTICS ‘© DC CHARACTERISTICS (Vcc = SV + 10%, 1=0.1 to 2.0 MHz, Vgg = Vp = OV, Ta =-20~ +70°C, unless otherwise noted). RES, STBY.MPo,MPi| [Vec-05 | — | [Vecx0.7 [=| tnpar “Hi” Volume | [Yert3 |v Input“‘Low” Voltage | allinputs [Vn P| 0 = [oe Tv Three State (off-state) tou=-10W8_[Vcc-07 | - [=v output “Low” Voltage EL] vo. |tox=t.6ma ee [AlOurputs | [= [= [ea Tv Darlington Drive Current] | “lon [Vourtsv | to | = [10.0 | ma All Inputs (Except _ |Vr/OE | ee ee ee Standby Current [Non Operation | tse [05.0 Ha Siapre (wae) | [15 | 30 [ma [Sleeping (=i.smHe**) | — [2a [45 [ma [Sleeping (f=2mniz"*) | | 30 [6.0 | ma Current Di ition” eipaon [Operating t=imuz**) [ — [7.0 [| 10.0 [ma Operating f=15mHz"") | — [105 | 15.0 | ma [Operating =2mtz"*) | — [140 [20.0 | ma *ViH min = Vec- 1.0V, Vit max = 0.8V (All output terminals are at no load.) **Currant Dissipation of the operating or seeping condition 's proportional o the operating frequency. So the typ. of max values about Current Dissipations atx Miz operation ae doce according tothe felowing formu typ. value (f= X MHz)= typ. value (f= 1MHz)x X max. value (f= X MHz)= max. value (t= 1MHz) x X (both the sleeping and operating) | @HITACHI ) 680 Hitachi America, Ltd. © Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300

a © AC CHARACTERISTICS (Vcc = 5V + 10%, f= 0.1 to 2.0 MHz, Vgs = Vpp= OV, Te =0~ +70°C, unless otherwise noted). BUS TIMING te Sympo |. Te Unit ™ 'Yymbo! | Condition | min [typ [max | min [ typ [max | min | tye | max | Cycle Tire [tre | [1 | - | 1 fosss|- [to [os | - [10 | Enable Rise Tie [te | ee ee Enable Fall Time [ter | ee ee ee ee Enable Pulse Width “High” Level™ | PWen_| Faso [— | =| a00 f= [= | a0 [P= [os Enable Pulse Width “Low” Level” [PWeu | [450 [ = | = [aw | | — [oof f-fim ‘addres, RAV Delay Time” | two | [= [= aso [= = Piao = = 0 fe Data Delay Time [Write [tow _| [= | = | 200 [= [= [reo [— T= [20 [ow Dat Setup time [Reed [tosn | -., [80] - | - [of [to] = fot ‘Adsiess, AM Hold Time” [aw | pet =a tet ta Talat a [write [tv | [ro [= |= [eo [= T= | fs Dua Hold Time [Read [tun | [ef t- foe f-t—- fo f=] — Jos RD, WA Pulse Width* | Pwaw | aso [ — | - | a0 | - | - | 220[ - | - | ns RD, WE Delay Time | tawo | P-{[-|[#]-]- op - | [of RD, WH Hod Time [enn | a ee Fela Tie [== [200 =F r60 [f= 20 [os CIR Hold Time [ef = fe p= io | = MR Setup Time” [town | [400 | - [ - |ae0 | = | = [200] - | - [ns MA Hold Time" [twa | [— |= pao P= Pao [To Ps E Clock Pulse Width at MR___| PWenn | [t-te [f= fe l= - fete reercowerston [na | Se [me] - |- [=| -| - |e [-[-[ Processor Control Rise Time | trer | [= [= [roo | = [= [00 [= [= | 100 | os Processor Control Fall Time | trer | [== P00 |= =f 100 = [= 100 ns BA Delay Time [ton | Fas | - | - [20] - | [rool - | - | veo] os OrcilatorSabilzation Time [tne | Fat | 70 | - | - [ao [=f = [ao | — TT Reset Puke Width [Pwr t | 3{-1-|3{-]-{3]- T= Ten thee umngh une pour pope ogy Thar hgawe aurea roan tow why paren (a tataghn ped corn) PERIPHERAL PORT TIMING tem Condition Fin [we [ max [min | typ [max | in [to [max | UM CeeTae™ [rowense [vow | Fas [200] - | - [aw] - | - [am] - | - | rape [rasa foew | mee [>| — [me [— [= [aol == To Delay Time (Enable pees feel [ee [-[-[=l- [lel l*l- Peripheral Data Valid) eee @HITACHI Hitachi America, Ltd. © Hitachi Plaza « 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 © (415) 589-8300 681

(Notel {pF is defined when output becomes open because output level can not be refered. Figure 12. EPROM Programming Timing

HD63701X0, HD637A01X0, HD637B01X0 FUNCTIONAL PIN DESCRIPTION address buses keep “High”. If RES turns “High”, the MCU re- © Yoo, Vss start sequence is Vocand Vs provide power tothe MCU with SV 4 10% supply. Vis (1) Latch the value of the mode program pins: MP, and MP, pin should be tid to ground 2) Initialize each internal register (refer to Table 5). G) Set the interrupt mask bit, For the CPU to recognize the © XTAL, EXTAL maskable interrupts TRO, , TRO, and 1RQ,, this bit should be ‘These’ two pins interface a crystal (an AT-cut type). Divide- clcareal in advance. by-four circuit is on chip. When 4MIlz crystal is used, the sysiem (4). ‘Pu the contents (=start address) of the last two addresses clock is IMHz for example (SFEFE, SFFFF) into the program counter and start the EXTAL pin may be driven with an external clock of 45 to Program from this address. (Refer to Table 1) 55% duty, and one fourth frequency of the external clock is pro- _-*_ The MCU is unable to accept a reset input until the clock be- duced in the LSI. The externa! clock frequency should be less COMES normal oscillation after power on (max. 20ms). During this transient time, the MCU and I/O pins are undefined. Pleuse AT Cut Parallel Resonant Crystal Oscitlator be aware of this for system designing, Co=7pF max © Enable (€) Fa=600 max This pin provides a TTL-compatible clock used for bus syn- chronization. Ils frequency is one fourth that of the internal oscil- XTAL lator or external clock. This pin can drive one TTL load and 90pE capacitance oO © Non-Maskable Interrupt (fINAI) Custer When the negative edge of the input signal is detected at this = 10pF . 22pF + 20% pin, the CPU will begin a non-maskable interrupt sequence. But EXTAL (3.2. MHz) the current instruction will be completed before it responds to the request. The interrupt mask bit of the condition code register doesn't affect non-maskable interrupt at al. Cuscu When the interrupt occurs, the contents of the program coun- ter, the index register, the accumulators and the condition code register will be pushed onto the stack. Upon completion of this (a) Crystal Intertace sequence, a vector is fetched from SFFFC and SFFFD, transfer- red their contents to the program counter and the non-maskable interrupt service routine starts. After reset, the stack pointer XTAL Ne. should be initialized on an appropriate memory area before NMT EXTAL External Clock out © Interrupt Request (JR, IRC;) Figure 13 Connection Circuit These are level-sensitive pins which request an internal inter- rupt sequence. At interrupt request, the CPU will complete the current instruction before it responds (o the request. If the inter- than four times of the maximum frequency. When using the €x-__Tupt mask in the condition code register is clear, the CPU will ternal clock, XTAL pin should be open. Fig. 13 shows an exam- _begin an interrupt sequence; if set, the interrupt request will be ple of connection circuit. The crystal and Cy, Cz should be ignored. When the sequence starts, the contents of the program mounted as close as possible to XTAL and EXTAL pins. Any counter, the index register, the accumulators and the condition line must not cross the line between the crystal and XTAL, EX- Code register will be pushed onto the stack, then the interrupt TAL. ‘mask bit will be set and inhibits all maskable interrupt. Finally, a vector is fetched from an address depicted in Table | and trans- ° sTsy ferred to the program counter, and instruction execution is re- ‘This pin is used for standby mode or EPROM mode. sumed. In standby mode, the oscillation may be stopped. To retain ‘The external interrupt pins, IRQ, and IRQ, are also used for the contents of RAM at standby, “0” should be written into Port pins Pie and P,,, $0 it is controlled by Bit 0 and I of the RAM enable bit (RAMW). RAME js the bit 6 of the RAM/port. RAM/port § control register at $0014. Refer to “RAM/PORT 5 5 control register at $0014. RAM is disabled by this operation CONTROL REGISTER" for details. and its contents is sustained. Refer to “LOW POWER DISSIPA- ‘One of the internal interrupts, ICI, OCI, TOI, CMI or SIO TION MODE" for standby mode. can generate an internal interrupt (IRQ,). IRQ, function is just ‘When this pin and Mode Program pins, MP, and MP,, are the same as TRQ, or IRQ, except the vector address. Fig. 14 “Low” level, the MCU is in EPROM mode. Refer to “PRO- shows the block diagram of the interrupt circuit GRAMMING THE EPROM" for details. (© Mode Program (MP,, MP,) © Reset (RES) These two pins decide the operation mode. Refer to “MODE This pin is used to reset the MCU’s internal state and provide SELECTION" for more details. a startup procedure. During power up, RES pin must be held below “Low” level for more than 20 ms. ‘The CPU registers (accumulator, index register, stack pointer, condition code register except for interrupt mask bit), RAM and data registers of ports are not initialized during reset, so their contents are unknown in a startup procedure. To reset the MCU during operation, RES should be held “Low” for at least 3 system-clock cycles. At the 3rd cycle, all the address buses become “High”. When RES remains “Low, the | @HITACHI : 686 Hitachi America, Ltd, « Hitachi Ptaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 + (415) 589-8300

a — —______ #D63701X0, HD637A01X0, HD637B01X0 Table 1 Interrupt Vector Memory Map Proty a tnvewrups Higher RES [free | Fret | Trap [Cerro [reo | WM [TFeFA | _FRFe | _ SWI (Software Interrupt [Free | FrFo | tho. ICI (Timer 1 input Capture) ‘OCI (Timer 1 Output Compare 1, 2) [_FFF2 | FFF3 | TOI (Timer 1 Overtiow) [Frc | FRED | CMI (Timer 2 Counter Match) [Frea [Free [TRO Lowest SIO (RORF+ORFE+TDRED Each Status Resster's Interrupt Enable Flog ST Enable, “0 Disable Condition Cove ocra oo no} poo] Son onre | P pee) ireult Adres Error | TRAP Detective Creu swi Figure 14 Interrupt Circuit Block Diagram @ HITACHI Hitachi America, Lid. « Hitachi Plaza © 2000 Sierra Point Prwy. » Brisbane, CA 94005-1819 « (415) 589-8300 687

HD63701X0, HD637A01X0, HD637B01X0 EN ca et ae The following signal descriptions are applied only for ex- Data from Port 3 (EO, to EO,) can be programmed into the panded mode. EPROM when applying 21V+0.5V to Vpp and holding CE in “Low” jevel. The EPROM address is provided to Port 1 and © Read/Write (R/W: P,,) Port 4 (EA, to EA,,). In verification, the EPROM data is output This signal, usually in read state (“High”), shows whether from Port '3 (EQ, to EO,) when this pin is “Low” level. In the MCU 1s in read (“High”) or write (*Low") state. This can “High” level, Port 3 will be high-impedance. In MCU mode, this drive one TTL load and 30pF capacitance. pin should be connected to Ves. © RD, WAP, P,) = Port ‘These outputs will turn “Low” whea the CPU read/write op- ‘The HD63701X0 has six 8-bit ports and a S-bit port, Table 2 eration is completed. This enables the CPU easy to access the pe- _gives the address of ports and the data direction register and Fig, ripheral LS! with RD and WR input pins. These pins can drive 15 the block diagrams of cach port ‘one TTL toad and 30pF capacitance. © Losd instruction Register (CT: P,,) Table 2 Port and Data Direction Register Address This is output for the instcuction opecode on data bus (active [Pon Adaren | low). This pin can drive one TTL load and 30pF capacitance Port Port Address Data Direction Register Port [$0002] © Memory Ready (MR: P,,) 2 | $0003 | 000 This input is used to strcich the system clock’s “High” period Pot —— in order to access low-speed memories. During this signal being Port3 | $0006 | soo0g in “High", the system clock operates in normal sequence. But in Port 4 = “Low”, the “High” period of the system clock will be streiched Ports $0016 = in integral multiples of the cycle time. This allows the CPU to in- During internal address access or nonvalid memory access, MR is prohibited internally to provent dectease of operation speed. Even in the hall state, MR can also stretch “High” period of system clock to allow peripheral devices to access low-speed —«® ‘Port 1 memories. AS this pin is used also for P.,. an enable bit is pro- In MCU mode, port 1 is used for an 8-bit output port. In Vided at bit 2 of the RAM/port 5 conteol register at SOO14, Refer mode 3, port 1 is high impedance during reset, and keeps the to “RAM/PORT 5 CONTROL REGISTER™ for more details state even afier reset is released. When the CPU writes on the port I data register, the written data will appear at Port 1, Once © Halt (RAT: Ps) Port I gets in the output state, it operates as an output tll reset. This input is used to stop instruction execution or to release The CPU can read the Port 1 data register for the bit manipula. buses free. When this signal turns “Low”, the CPU will be in tion instruction. the halt state after completing the current instruction. During the In mode 1 and 2, port 1 is used for lower address buses. This halt state, BA (P,,) is in “High”, and an address bus, data bus, port can drive one TTL load and 90pF capacitance. RD, WR and R/W are high impedance. When an interrupt is re- In EPROM mode, port I is lower address bus (EA, to EA.) quested in the halt state, the CPU responds to the interrupt re- for the EPROM. Quest after the halt is cancelled. When halted during the sleep sate, the CPU keeps the sleep state, and BA is “High” and the @ Port 2 buses are high impedance. Then the CPU returns to the previous ‘An 8-bit inpulvoutput port. Its 1/0 state depends on the data sleep state when the HALT goes "'High” direction register (DDR) of port 2 which provides two bits: bit 0 (Note) When the CPU is interrupt wait state in WAL instruction decides the 1/0 direction of P., and bit | the 1/0 direction of P., ‘execution, HALT should be held “High”. if HALT turns to P,, (°0" for input, “1” for output), ° “Low”, the CPU may malfunction after releasing the halt Port 2 is also used for the timers and the SCI. When used for state the timers and the SCI, P,, to Pr: ate decided 1/0 regardless of the DDR (except for P.,) © Bus Available (BA; P,.) This output is normally “Low but High" when the CPU accepts FTALT and releases the buses, The 116800 and HD6802 Port 2 Data Direction Register make BA “High" and release the buses at WAI execution, while the HD63701X0 doesn’t make BA “High under the same con- 2 6s 4¢ 3 2 1 0 zs CCELCELRE The following pin functions are applied only ia EPROM mode. Refer to “PROGRAMMING THE EPROM” for details of EPROM mode. The DDR of port 2 is cleared at reset and port 2 is configured as an input, This port can drive one TTL and 30pF. In addition, ‘© Chip Enable (CE: P,,) it is capable of sinking ImA current at Vout=L.SV to drive dix This pin is input for programming and verifying the EPROM. _ rectly the base of Darlington transistors ‘When this pin is “Low” level, EPROM will be enable. ‘The EPROM can not be programmed or verified in “High Port 3 level. An S-bit 1/0 port. 1/0 state depends on the DDR of Port 3 _ which has only one bit (“0" for input and "I" for output). It is © Program Voltage/Output Enable (Vpp/OE) cleared at reset. In mode 1 and 2, port 3 is used for data bus. This pin is used for program voltage and data output control This port can drive one TTL load and 90pF capacitance in verification. Port 3 is used for data bus (EQ, to EO;) of EPROM in @HITACHI 688 Hitachi America, Ltd. + Hitachi Piaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819» (415) 589-8300

a HD63701X0, HD637A01X0, HD637B01X0 Port Wie Signal Pont Wte Signal Mose 3 Mode 3 a aL Mode 1,2 Mose 1,2 ‘Address Bus, X. Address Bus, ~ Conte! Signal Control Sigal EPROM Mode Port 4 (Bit 4 to 7), Port 7 EPROM ec <| Port 1, Port 4 (Bit 0 to 3) Port Read Signal eT] Port Wie Sina a ‘ode Port 5 Aternat Exe aa. | Contr Port Read Signet ‘Kdaress Read dress Resa ana Bus Dy PU Internal Bos EPROM Mode ai EPROM Mode « EPROM Bats Bus Port 3 Port 5 (Bit 7) Port Wrie Sign Port Writ Signat Port Ourput Enabie ry ron eel Oats Bus > al ourput Enable Timer 1, 2, Fal Sor Ouipal tian Ce nf Por Read Sanat q ><] Reset Timer 1,2. imer 1 np) Bertigae J teat <J Port 2 Port 6, Port 2 (Bit 0) Figure 15 Port Block Diagram @HITACHI Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 689

HD63701X0, HD637A01X0, HD637B01X0 EPROM mode. In this case, I/O statc of Port 3 is selected by OF halt function is prohibited regardless of the value of this bit. This but not the DDR. bil is set at reset. (Note) When using P,, and P., for port in mode | and 2, MRE Port 3 Data Direction Register and MLTE must be cleared afer reset. 7 6 5s 4 3 2 1 © Bit 4, Bit 8 Not Used. Por The RAM is controlled by this bit. It is set at reset and the RAM is enabled. This bit is programmable by software. When the RAM is disabled (=logic ““0"), the CPU can access an cx- © Port 4 ternal memory. This bit should be cleared at the beginning of In MCU mode, port 4 is used for an 8-bit output port like standby mode to protect the RAM dala, Port |. In mode | and 2. it is used fos upper address bus. In EPROM mode. P,. to Py, ate used for upper address bus ‘Bit 7_ Standby Power Bit (STBY PWR) (EA, to EA,,) of EPROM. This bit is cleared whenever Vec decreases below Vaay (min). This is a read/write status bit by software. If this bit is set © Port & before standby mode, it indicates that Vec is applied and the ‘An 8-bit input port. The lower 4 bits are used for interrupt, RAM is valid. MR, HALT, and P., is CE for the EPROM control © Port 6 An 8-bit 1/O port. This port is progcammabic as cither input or output under sofiware control of the corresponding the DDR: 0" for input, ““1" for output). This port can drive one TTL Joad and 30pF. The DDR of port 6 is cleared al reset. In addi- tion, it is capable to sinking ImA current at Vout=1.5V to drive. directly the base of Darlington transistors. © Port 7 A 5-bil output port. In mode 3, port 7 is high impedance dur- ing reset and keeps the stale even afler reset is released. When the CPU writes on the port 7 data register, the written data will appear at Port 7. Once port 7 geis in the output state, it operates as an output till reset. The CPU can read the data register for the bit manipulation instruction. in this case b, to b, are ““1". In mode 1 and 2, port 7 is used for control signals (RD, WR, R/W, [IR and BA). This port can drive one TTL load and 30pF = RAM/PORT 5 CONTROL REGISTER The control register located at $0014 controls on-chip RAM and port 5. RAM/Port 5 Control Register 7 6 s « 3 2 1 0 ster nfo] = | = Pref] YT Joo Bit 0, Bit 1 TROL, TRG, Enable Bit (ROE, ROE) When using P., and P,, for interrupt pins, write “1” in these bits. When “0”, the CPU doesn't accept an external interrupt or 2 sleep cancellation by the external interrupt. These bits are cleared at reset Bit 2 Memory Ready Enable Bit (MRE) When using P,, for an input for Memory Ready signal, write “1” in this bit’ When “0”, the memory ready function is prohibited and P,, is for port. In mode 3, the memory rcady function is prohibited regardless of the value of this bit. This bit is set al reset. Bit 3 Halt Enable Bit (HLTE) When using P., for an input for Halt signal, write “1” in this bit. When “‘0", the halt function is prohibited. In mode 3, the | @ HITACHI 690 Hitachi America, Ltd. # Hitachi Plaza # 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

HD63701X0, HD637A01X0, HD637B01X0 = MODE SELECTION © Mode 2 (Expanded Mode} The HD63701X0 provides two fundamental modes, MCU This mode is also expanded mode. But in mode 2, address mode and EPROM mode. MCU mode is grouped into three; two Space is expandable up to 61k bytes and the EPROM is enable expanded modes (mode 1, mode 2) and a single chip mode (refer to Fig. 17). (mode 3). ‘These operating modes are selectable by mode program pins, © Mode 3 (Single-chip Model MP, and MP,, and standby pin, STBY as shown in Table 3. In this mode, all ports are available (refer to Fig. 18). © Mode 1 (Expanded Mode) © EPROM Mode In this mode, Port 3 is data bus, Port J is lower address bus im this mode. the EPROM can be programmed. Refer to and Port 4 is upper address bus to interface with the HMCS6800 “PROGRAMMING THE EPROM” for details. buses. Port 7 is used for control signal such as R/W. In mode 1, the EPROM is disable and external address space are expandable © Mode and Ports up to 65k bytes (refer to Fig. 16). Table 4 shows the MCU signals in each mode. Table 3 Mode Selection wove [wei_[ wo [svav [erro [nam [intrupeveeor | opsaton Nove a woumese [2] ae [oe fo D1 enone ae Tepe fe fo sec “LreLogic "0", “H=Logic 1", 1: Internal, E: External, *; Don't care ote 1) The RAM address area will be external by clearing RAME bit at $0014, Table 4_ MCU Signals in Each Mode eo [tet EPROM Moe Port 1 ‘Address Bus (Ae ~ Ax) | Address Bus (Ao ~ Ar) ‘Address Bus (EAo ~ EA7) Port3 Data Bus (D0 ~07) _| Data Bus (Do ~ D7) 1/0 Port Data Bus (Oo ~ E07} Porta ‘Address Bus (As ~ Ars) | Address Bus (As ~ Ais) Address Bus (EAs ~EAnn) (Note? Port 6 1/0 Port 1/0 Port No use (Note 3) Port7 RO, WA, RAV, LIR, BA | RO, WA, RAW, CIR, BA No use (Note 3) (ote 1) Use only 4 pins Pay 10 Pas. Pas 10 Pay are not used, (Note 2) 7pins Pie to Py ore not used. (Note 3) Unused ports should be connected to Vs, @HITACHI Hitachi America, Ltd. « Hitachi Ptaza » 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8900 691

a HD63701X0, HD637A01X0, HD637B01X0 a MEMORY MAP ing mode is shown in Fig. 20. The first 32 locations of each map The MCU has ability to access a 65k byte memory space de- are reserved for the MCU's internal register arca, as shown in pending on the operating mode. A memory map for cach operat Tabie 5. Table 5 Internal Register nawen [Resins «dC iize at RESET 00 a = on [Pon 2OataDirectionReaater |W SFC of poet Undefined 03 [poz Undefined 04” | Port 3DataDiecton Register |W SFE 95 ee = oer] fons Undefined or | pore Undefined 08 $00 09 [Free Running Counter ("High") [RW $00 oa $00 oB StF oc [_Ouiput Compare Regier 1("towy | RW | SF 00 | Input Capture Register High) || ‘$00 oe [Input Capture Register ("tow) | R_ $00 oF $10 10 $00 n $20 12 [Receive DataReviter | OR $00 43 [Transmit Data Resiter |W $00

14 SIC of SFC

15 ee ee =

16 Port 6 Data Direction Register [ow | $00

7 Port 6 Undefined

we [ror Undefined

19 SFF

18 [Timer Controi/Status Revister 3 | RW $20 ic [Time Constant Register |W SFF 10 [Timer 2UpCounter [RW $00 iE a | = we | tet Reomer = * External Address in Mode 1,2 ++ Test Register. Do not access to this register +85 Read Only Register WW; Write Only Register IW: Read/Write Repster ) @ HITACHI Hitachi America, Ltd. ¢ Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 693

HD63701X0, HD637A01X0, HD637B01X0 HORTON many | Hoearo1xe mons | HosaToTx0 wana Prossvonne Exped Mode _| erie Mose " Single chip Mode san com, | soot LZ, Bre | soosr Aire eee Memorw Lee memory “WZ soe sly7774 ace “Yy tment | torent snacna tj oe Yj), ™ Yi) we soor Lid soors Lid soos LAA | | exw | Memory | External Spoce | | Sonor | soe $1000 77 S000 ‘F000 wy aa Rou est osk + Cachan e folowing arenes | Exclude the folowing adareses Seuhmayeawederteeay;” | wnkch maybe ued enenaly Sor 00,0, 07.8 Son 00 S06 09,318 Figure 20 HD63701X0 Memory Map = PROGRAMMING THE EPROM © Erasure The HD63701X0 docs not operate as the MCU in EPROM. Erasure of EPROM begins to occur when the LSI is exposed to mode, which allows to be programmable as equivalent EPROM ultraviolet light (wavelength. 2537 A. an intensity of at least: 2732A type. When three pins, MP,, MP, and STBY should be 1.5W.sec/cm). Exposing the LSI to an ultraviolet lamp of 1,200 wWrem’ held low, the MCU will be in EPROM mode as shown in Table rating for 20 to 30 minutes, at a distance of about | inch, should be 3. In this mode, P,, to P,, are used for data bus, P,, to P,, and sufficient. P,, to P,, for address bus, and P,, for TE input. (Refer to Fig. 19), (Note) If the glass window is stained, erasure time will be ex- tended. Remove stains from the window with a solvent @ Programming/Verification which has no influence on the package like alcohol. Don’t When CE pin is held low after the program voltage (Vpp) is rub the window hard but wipe out softly. applied to Nap’OE pin, the data byte can be applied to Port 3. When Vpp/OE pin and CE pin are held low after programming, the programmed data is output from Port 3 and user can verify = TIMER the data. 1/0 timing of these signals are referred to Fig. 12. ‘The HD63701X0 has a 16-bit programmable timer which can When CE pin is returned to high, Port 3 will be tri-state and be used to perform input waveform measurements while generat. EPROM programming/verification will be inhibited. ing two independent output waveforms. The pulse widih can vary Table 6 shows the condition of the each pin is EPROM mode. from several microseconds to many seconds. Unused pins should be connected to GND in EPROM mode. Timer 1 is configurated as follows (refer to Fig. 22). Table 6 Pin Condition in EPROM mode » [vee [vs | Ver/OE [ee [mum [peer | MPo, MP1, STBY | Other pins 43 10 50 tse je | |e [a | sess [See Programming | #8 [ono [Vor [| Oateinout [Address input [ vt" eno Verification | +8 [ono [*u" [*u" [Data output | Address input | U" [GND Inhibition of oe ae “HV lve, Ls lel | @ HITACHI 694 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 © (415) 589-8300

a HD63701X0, HD637A01X0, HD637B01X0 ~ Control/Status Register } (8 bil) Timer Control/Status Register 1 + ControV/Status Register 2 (7 bit) > 6 8 @ 3 2 1 0 + Free Running Counter (16 bit) = Output Compare Register 2 (16 bit) = Input Capture Register (16 bit) @ Free-Running Counter (FRC) ($0009 : 000A) BitO OLVL1 Output Level 1 The key timer element is a 16-bit Free-Running Counter When a match is found between the FCR and the which is incremented by system clock (E). The counter value is OCRI1, OLVLI will appear at Port 21 if OE1, bit 0 of the readable by software without affecting the FRC. It is cleared by TCSR2, is set, reset. Bit? IEDG input Edge ‘A write to the high byte of the FRC ($09) will preset the high ‘This bit controls which level transition will trigger the and low byte of the FRC to SFFF8 . A continuous write to the FCR transfer to the ICR. For this function, the DDR high and low byte FRC, however, will sct them to the write dats. corresponding 10 Port 20 should be cleared. The FRC write timing will be as follows when double store in TEDG=0, transferred on a negative edge structions (STD, STX etc.) execute, JEDG=, transferred on a positive edge Bit 2 ETOL Enable Timer Overtlow Interrupt When this bit is set, an internal interrupt (IRQ,) is $09 Write SOA Write enabled for TOI. When cleared, the interrupt is inhibited. sa, Bit EOCH Enable Output Compare interrupt 1 When this bit is set, an internal interrupt (IRQ,) is B enabled for OCH. When cleared, the interrupt. is Counter valve io aFrrs { S5Ara inhibited. : i Bit 4 EIC) Enable Input Capture interrupt In the case of a write [SSAF3) to the FRC. ‘When this bit is set, an internal interrupt (IRQ,) is ‘enabled for ICI. When cleared, the interrupt is inhibited. Figure 21 Counter Write Timing Bi eet ens ence os This read only bit is sct when the FCR contains all © Output Compare Register (OCR) I's. It is cleared by reading the TCSR1 followed by the {$000B, $000C: OCR1) ($0019. $001A; OCR2) FCR's high byte ($0009). The Output Compare Register is a 16-bit read/write register Bit OCF1 Output Compare Flag 1 used to control an output waveform. It is always compared with This read only bit is set when a match is found be- the FRC on each E-cycle. tween the OCR1 and the FRC. It is cleared by writing to ‘When a match is found, Output Compare Flag (OCF) in the the OCRI (S000B or $000C) followed by reading the Timer Control/Status Register (TCSR) is set. If an output enable TCSRI or TCSR2. bit (OE) in the TCSR2 is “1”, an output level bit (OL VL) in the Bit 7 ICF Input Capture Flag TCSR will appear at Port 2! (Tout 1) or Port 25 (Tout 2). This read only bil is sct (0 indicate a level transition ‘The OCR and OLVL can then be changed for the next com- defined by IEDG. It is cleared by reading the high byte parc, The OCR is set to SFFFF at reset. The compare function is ($000D) of the ICR followed by the TCSR1 or TCSR2. inhibited for a cycle afler a write to the OCR or to the high byte of the FRC. This is to set the 16-bit value valid in the register for © Timer Control/Status Register 2 (TCSR2} [$000F) compare. In addition, it is because SFFF8 is set at the next cycle The Timer Control/Status Register 2 is a 7-bit register. All of a write to the high byte of the FRC. bits are readable while the lower 4 bits can be written. The upper + For a write to the FRC or the OCR, 2-byte transfer in- 3 bits indicate the following timer’s status. struction (such as STX etc.) should be used. BitS A match has been found between the FRC and the OCR2 (OCF2). © Input Capture Register (ICR) ($000D ; OOOE) Bit 6 The same flag as the OCFI of the TCSR1 ‘The Input Capture Register is a 16-bit read only register used Bit 7 The same flag as the ICF of the TCSR1 to store the FRC when an external input transition occures de- fined by input edge bit (IEDG) in the TCSRL The followings are each bit descriptions. in order to input the external signal to the edge detective cir- cuit, Port 20 should be configured as an input. ‘When an input capture occures at the next cycle of a read the high-byte of the Timer Control/Status Register 2 TCR, the input capture will delay one cycle. In order to ensure > 6 8 4 39 2 1 0 the input capture, a read to the ICR needs 2-byte transfer in- Struction, and the input pulse width should be al least 2 system [ier Jocrfocra] — Focrfwd ora [os] 'so00r cycles. This register is cleared ($0000) at reset. © Timer Control/Status Register 1 (TCSR1) ($0008) The Timer ControV/Status Register | is an 8-bit register of BitO OE1 Output Enable 1 which all bits are readable while the lower 5 bits can be written. Ir this bis set. the OLVLI will appear at Port 21 ‘The upper 3 bits indicate the following timer’s status. when a maich is found between the FCR and the OCR1. Bit 5 The FCR has overflowed. (TOF). When it is cleared, Port 21 will be 1/0 port. When set, it Bit 6 A match has been found between the FCR and the ocR will be an output of OLVL1 automatically. 1 (OCFI). Bit 1 O£2 Ovtput Enable 2 Bit 7A level transition of the timer input has been detected If this bit is set, the OLVL2 will appear at Port 25 (ICF). when a match between the FCR and the OCR2. When : this bit is cleared, Port 25 will be 1/0 port. When set, it ‘The followings are each bit descriptions. will be an output of OLVL2 automatically. | @HITACHI : Hitachi America, Ltd. * Hitachi Plaza © 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 © (415) 589-8300 695

HD63701X0, HD637A01X0, HD637B01X0 Bit 2 OLVL2 Output Level 2 Bit 6 OCF1 Output Compare Flag 1 OLVL2 is transferred to Port 25 when a match is Bit? ICF Input Capture Flag found between the FCR and the OCR2. If OE2, bit 5 of OCFI and ICF addresses are partially decoded. CPU the TCSR2, is set, OLVL2 will appear at Port 25. read of the TCSRI/TCSR2 makes it possibie to read Bit3 EOCI2 Enable Output Compare Interrupt 2 OCF and ICF into bit 6 and bit 7, When this bit is sct, an internal interrupt (IRQ,) is Both the TCSRI and TCSR2 will be cleared by reset. enabled for OCI2, When cleared, the interrupt is inhibited. (Note) If OE] or OE2 is set before the first output compare Bit4 Not Used match is found after reset, Port 21 and Port 25 will out- Bit 5 OCF2 Output Compare Flag 2 put "0" respectively. ‘This read-only bit is set when a match is found be- (Note) Because the set condition of ICF precedes its reset condi- tween the FCR and the OCR2. It is cleared by writing 10 tion, ICF is not cleared when the set condition and the the OCR2 ($0019 or $O01A) followed by reading the reset condition occur simultancously. The same phenom: TCSR2. enon applies to OCF1, OCF2 or TOF respectively. ie: a [Baer ] Leer] i cI [sown] axe] Com] a | nes Pee tt it = Joor| so [ows fooferofeocben] | Yep EET (-O= ft] a | Soescrrcocem a | a LS a bpm te te Figure 22 Timer 1 Block Diagram a TIMER 2 put the data to it In addition to the timer 1, the HD63701X0 provides an 8-bit reloadable timer, which is capable of counting the external event. © Time Constant Register (TCONR) ($001C) ‘This timer 2 contains a timer output, so the MCU can generate The Timer Constant Register is an 8-bit write only register. It three independent waveforms. (Refer to Fig. 23.) is always compared with the T2CNT. ‘The timer 2 is configured as follows: When a match has been found, counter match flag (CMF) of Control/Status Register 3 (7 bit) the Timer Control/Status Register 3 (TCSR3) is set and the 8-bit Up Counter value selected by TOSO and TOSI of the TCSR3 will appear at Time Constant Register (8 bit) Port 26. When CMF is set, the FCR will be cleared simu- Mtancously and then a counting starts from $00. This enables reg- @ Timer 2 Up Counter (T2CNT) ($0010) ular interrupts and waveform outputs without any sofiware sup- This is an 8-bit up counter which is incremented by the clock port. The TCONR is set to “SFF" by resct. controlied by CKSO and CKSI of the TCSR3. The T2CNT is always readable without affecting itself. In addition, any value can @ Timer Control/Status Register 3 {TCSR3) ($001B) be written to the T2CNT by software even during counting. The Timer Conirol/Status Register 3 is a 7-bit register. All The counter is cleared when a match is found between the bits are readable while 6 bits except for CMF can be written. T2CNT and the TCONR or by reset. A write to the T2CNT at the clear cycle does not reset it but @HITACHI 696 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 * (415) 589-8300

HD63701X0, HD637A01X0, HD637B01X0 HD63701X0 Internal Data Bus igi ig: Timedt FRC Clock ‘ Time Timer2 Input Constant . Clock Port 2 Register Up Gounte: @ Select ‘ Bin? Level Port 2 | aan _ resra [cn fecml — [2¢| ros! $0018 IRQs o—_! | Figure 23 Timer 2 Block Diagram: The followings are each bit descriptions. Bit2 TOSO Timer Output Select 0 Bit 3 TOS1 Timer Output Select 1 Timer Control/Status Register 3 When a maich is found between the T2CNT and the Fa ieaaineenie- ener TCONR, timer 2 output selected by these bits shown in Table 8 will appear at Port 26. When both TOSO and [em [econ] = [v2 frossfrasefexssexsd soo1e TOSI are ciewted, Port 26 will be an 1/0 port. Table 8 Timer 2 Output Select Bit 0 CKSO Input Clock Select 0 Bit 1 CKS1 _ Input Clock Select 1 tos1 | Toso | Timer Output ‘An input clock to the T2CNT is selected by these bits T_[__0 [| __ Timer Output inhibited as shown in Table 7. When an external clock is selected, 7 Port 27 will be an input automatically. The positive edge OTT Tosaie Output of the external clock increments the T2CNT. The maxi- 7 [0 [Output "o™ mum external clock is half of the system clock frequency. 7 ‘Output "1" * When a match is found between the TZCNT and the TCONR, timer 2 Table 7 Input Clock Select ‘output level & reversed. This leads to production of a square wave with $o% duty tothe external without any toftware support KSI Input Clock to the Counter o [oJ Eetock o _ E clock/8* Bit4 T2E Timer 2 Enable Bit a ‘When this bit is cleared, the T2CNT will stop. When set, a clock selected by CKSI and CKSO (Table 7) pro- ToL External clock Widest the T2CNT. (Note) Py. is “0 when T2E is cleared and Pa: is configured as * ese locks come from he FR ofthe tines 1 on of hee cocks oe apt by TOSI of TOSD. It alsa is 0" when THE is ieee coe incense # wre to the FRC set and Py is configured as an output before the first counter match. Bit 5 Not Used Bit 6 ECMI Enable Counter Match interrupt @HITACHI Hitachi America, Ltd. © Hitachi Plaza # 2000 Sierra Point Pkwy. » Brisbane, CA 94005-1819 « (416) 589-8300 697

HD63701X0, HD637A01X0, HD637B01X0 When this bit is set, an internal interrupt (IRQ,) is The SCI is initialized by writing desirable control bytes to the enabled for CMI. When cleared, the interrupt is inhibited. RMCR and then to the TRCSR. Bit 7 CMF Counter Match Flag The transmit operation is enabled by TE in the TRCSR. This read only bit is set when a match is found be- When TE is set, the output of the TDSR is connected to P,, tween the T2CNT and the TCONR. It is cleared by writ- which will be configured as an output regardless of the DDR, , ing “0”. (It cannot be written “1” by software) and then the serial output is initiated by transmitting to a 10-bit Each bit of the TCSR3 is cleared by reset. preamble of ‘1" in the 8 Bit Data Format or an 11-bit preamble of “1” in the 9 Bit Data Format. Following the preamble, the in- ® SERIAL COMMUNICATION INTERFACE (SCi) ternal synchronization is established and the transmitter section The HD63701X0 SCI provides two operation modes; one is is ready for operation, an asynchronous mode by the NRZ format and the other is a AL this point one of two situation exist: clocked synchronous mode to transfer data synchronizing with 1) If the TDR is empty (TDRE=!), a continuous ‘string of the serial clock. ‘ones will be sent indicating an idle line. The serial interface is configured as follows: 2) Ifa byte has been written to the TDR (TDRE=0), it is + Transmit/Receive Control and Status Register (TRCSR) transferred to the TDSR, TDRE will be set and tran:.nis- Rate/Mode Control Register (RMCR) sion will begin. ~ Receive Data Register (RDR) During the transfer itself, the start bit (0) is first wansmitted. » Receive Data Shift Register (RDSR) Then the 8 data bits or the 9 data bits (beginning with bit 0) fol- + Transmit Data Register (TDR) lowed by the stop bit (1) are transmitted, When the TDR has * Transmit Data Shift Register (TDSR) been emptied, TDRE is set. The SCI is initialized by software. The procedure is usually as If the MCU fails to respond to the fag within the proper time, follows: (TDRE is still set when the next normal transfer from the TDR 1) Write a operation mode into each corresponding control to the TDSR should occure) then a “1” will be sent (instead of a dit of the RMCR. “0") at start bit time, followed by more I's until more data is 2) Write @ operation mode into each corresponding control ‘supplied to the TDR. No 0's will be sent while TDRE remains as bit of the TRCSR. oo bie When setting the baud raic and operation mode, TE and RE ‘The receive operation is enabled by RE which configures P,,. should be “0”, When TE and RE is set again, more than | bit The receive operation is controlled by the contents of the cycle of the current baud rate is necessary. If set in less than 1 bit TRCSR and the RMCR. The receiver bit interval is divided into cycle, the SCI cannot be initialized occasionally. 8 sub-intervals for internal synchronization. The received bit ‘Stream is synchronized by the first “0 (space) encountered. The @ Asynchronous Mode approximate center of each bit time is strobed during the next 10 An asynchronous mode contains the following (wo data for- bits. mats: If the tenth bit is not a “1” (stop bit), a framing error is as- 1 Start Bit + 8 Bit Data + | Stop Bit, 8 Bit Data Format sumed and ORFE is set. If the tenth bit is a “*I"", the data is I Start Bit + 9 Bit Data + 1 Stop Bit; 9 Bit Data Format \\ansferred to the RDR and interrupt flag RDRF is set. If RDRF. In 9 Bit Data Format, if the 9h bit is “1”, the format of is still set at the next tenth bit time, ORFE will be set, indicating. 1 Start Bit + 8 Bit Data + 2 Stop Bit an over-run has occurred. When the CPU responds to either flag 2 er es i: eo 7 ee~L TD TTT TTT) | ele dell [=|] H063701X0 Internal Date Bus LET ET ETT) bebe fedm [ef [eT~] It Transco Conta Bn Pop ‘recs ES Ln] Figure 24 Serial Communication interface Block Diagram | @HITACHI : 698 Hitachi America, Ltd. © Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 » (415) 589-8300

ED G3.701X0, HDE37A01X0, HDE37BO1XO (RDRF or ORFE) by reading the TRCSR followed by reading @ ‘Clocked Synchronous Mode the RDR, RDRF (or ORFE) will be cleared. In the clocked synchronous mode, the transmit operation is (Note) Clock Source in Asynchronous Mode synchronized with the clock pulse. In the clocked synchronous When using an internal clock for the SCI, the following mode an SCI clock 1/0 pin is only P,,, so the receive and trans- requirements arc applicable: mit operation cannot be simultancously enabled. Therefore, TE + Set CCI and CCO to “I” and “0" respectively. and RE should not be set simultaneously. Fig. 25 gives a syn- + A clock is generated regardless of the value of TE, — chronous clock and a data format in the clocked synchronous RE mode. + The maximum clock rate is E+ 16. The (ransmit operation is enabled by TE in the TRCSR. Py, is ~ The output clock is the same as the bit rate configured as an output regardless of the value of the corres- When using an external clock for the SCI, the following _ponding DDR. requirements ate applicable: Both the RMCR and TRCSR should be set in the desirable «Set CCI and CCO in the RMCR to “1” and “1” re- operating conditions for data transmit. spectively. If the uscr wishes to provide an external clock, the data bits + The external clock shoukd be sot 16 times the desired (beginning with bit 0) are transmitted from P,., synchronizing baud rate. with 8 clock pulses supplied 10 Pr,, when TDRE is “0”. TDRE is + the maximum clock frequency is the same as the sys- set when the TDSR is “empty". More the 9th clock pulse is ig- tem clock nored, = Trani oretion evron LE LULL LAS LS ‘lock Zz ~ Felo folofoeteleXZ Li EZZZZANos Vales + Transmit data is sent between the negative edge of # xynchronous clock and the next negative edge. + Receive data is latched at the positive edge. Figure 25 Clocked Synchronous Mode Format The receive operation is enabled by RE. Pzy is configured as available, By this, uninterested MCU can inhibit all ‘an input for the 8 bit external clock and P,, is configured as an further receive processing tll the next message starts. input for the receive data. The operating mode of data receive is ‘Then wake-up function is triggered by consecutive 1's decided by the TRCSR and the RMCR. with { frame length (10 bits for the 8-bit data format, or If the external clock is provided, RE should be set when Py, is 11 bits for the 9-bit data format). The software protocol “High”. The receive data is transferred to the RDSR by this should provide the idle time between messages. clock, and RDRF is set. More the 9h clock pulse are ignored. By setting this bit, the MCU stops data receive till the When RDRF is cleared by reading the RDR, the MCU starts re~ next message, The receive of consecutive “I” with one ceiving the next data frame length wakes up and clears this bit and then the RDRF, therefore, should be cleared with P,, “High”. When MCU restarts the receive operation. However, the RE the first byte data is received, RDRF is set. Afier the second flag should be set before setting this bit. In the clocked byte, the receive operation is enabled by clearing RDRF. synchronous mode WU is not available, so this bit should not be set © Teansmit/Receive Control and Status Register (TRCSR) Bit 1. TE Transmit Enable ($0011) When this bit is set, transmit data will appear at Pay The TRCSR is an 8 bit register which is readable. Bits 010 4 afier one frame preamble in asynchronous mode, while in are also writable. This register is initialized to $20 by reset. Each clocked synchronous mode appear immediately. This is bit functions as follows. execuicd regardless of the value of the corresponding DDR. When TE és cleared, the serial /O doesn’t affect Pog Bit 2 TIE Transmit Interrupt Enable Transmit/Receive Control Status Register ‘When this bit is set, an internal interrupt (IRQ,) is + 8 8 ee enabled when TDRE (bit 5) is set. When cleared, the in- terrupt is inhibited Cc When set, Py, is configured as an input for the receive operation regardless of the value of the DDR. When RE is cleared, the serial 1/0 doesn't affect Py. Bit WU Wake-up Bit 4 RIE Receive interrupt Enable Jn a typical multi-processor configuration, the software ‘When this bit is set, an internal interrupt, IRQ, is protocol will usually identify the address at the beginning enabled when RDRF (bit 7) or ORFE (bit 6) is set of the message. In order 10 permit uninterested MCU's ‘When cleared, the interrupt is inhibited, to ignore the remaining message, a wake-up function is Bit TORE Transmit Data Register Empty | @HITACHI | Hitachi America, Ltd. » Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1619 + (415) 589-8300 699

HD63701X0, HD637A01X0, HD637B01X0 TDRE is set when the TDR is transferred to the Rate/Mode Control Register TSR in the asynchronous mode, while it is set when the TDSR is “empty” in clocked synchronous mode. This bit is cleared by reading the TRCSR and writing the 7 6 5 4 3 2 1 0 new transmit data to the TDR. TDRE is set by resct. (Note) TE should be set before clearing TDRE. [108] ros [ 82 [oce ]ecs [cco] s+ [sso] $0010 Bit 6 ORFE Overrun Framing Error ORFE is set when an overrun or a framing error is oc- cured (during data receive only). An overrun error occurs when a new reccive data is ready (0 be transferred to the Bird $80 RDR with RDRF stil set. A framing error occurs when a Bit! SS1} Speed Select stop bit is “0. But in clocked synchronous mode, this Bits $82 bit is not affected, This bit is cleared when reading the TRCSR, then the RDR, or by reset Bit 7 ORF ‘Receive Data Register Full the internal clock for the SCI. When the source of the SCI inter- RDRF js set when the RDSR jis transferred to the nal clock is the timer 2's up counter, the desired baud rates may RDR. Cleared when reading the TRCSR, then the RDR, _be selected by the TCONR shown in Table 10. or by reset. (Note) When operating the SCI with internal clock, do not write (Note) When 2 few bits are set between bit $ to bit 7 in the {0 the counter which is the source of the SCI clock TRCSR, a read of the TRCSR is sufficient for clearing those bits. It is not necessary to read the TRCSR every- time to clear cach bit Bit2 cco © Rate/Mode Contro! Register (AMCR) Bit3 CCI} Clock Control/Format Select® ‘The RMCR controls the followings: Bia = CC? + Baud Rate + Data Format * Clock Source Pz, Function These bits select the data format and the clock source (refer In addition, if 9-bit data format is set in the asynchronous ‘® te cet and CC? are cleared and the MCU will be in mode, the 9th’ bit is put in this register. All bits are readable and the clocked synchronous mode (the external clock opera- writable except bit 7 (read only). This register is cleared by reset tion) by reset. Thon Ps, is forced 10 ve confgored ve a These bits select the baud rate when using the internal clock. input for the dock, Ir uding Par for sa puteet the DDR at Table 9 lists the available bit times and baud rates. The timer I's ate a : ‘i port 2 should be set to “I” and CC1, CCO must be set to FRC (SS2=0) and the timer 2's up counter (SS2=1) provide Lei . | @HITACHI 700 Hitachi America, Ltd. * Hitachi Plaza » 2000 Sierra Point Pkwy. # Brisbane, CA 94005-1819 « (415) 589-8300

HD63701X0, HD637A01X0, HD637B01X0 Table 9 SCI Bit Times and Rates (1) Asynchronous Mode ES ECL ssz_ss1_ssol_€ [eae [tome 1 28 oO ° oO €+16 26 s/38400Baud 16 18/62500Baud 13.08/76 800Baud o 0 1 e128 208,15/480080ud | 128.s/7812 SBad | 104 2,5/9600Baud 0 1 0 e+ 1024 1.671ns/600Baud | 1 024ms/976.68aud | 833.315/1200Baud o 14 £34096 6.67ms/1508a0d | 4096ms/244 1Baud | 3.333ms/300Baud 1 - - . * . When S82 is ‘“1"", Timer 2 provides SCT clocks. The baud rate is shown as follows with the TCONR as N. _ f f: input clock frequency to the’ Baud Rate = S71) ( timer 2 counter N=O0~ 255 {2) Clocked Synchronous Mode * LL ssa_ss1_ssof— © [one sine me oO °o oO E52 2ysfoit 1 33ys/bit Vusfon oO ° 1 +16 16yS/dit 10 7S/dit Bys/ot o 1 0 €5128 128,,s/o1 85.3 45/8 64,,s/bt o1 4 £5512 512 ,s/on 341 s/t 256,/bi 1 = = o o * Bit rates in the case of internal clock operation. In the case of external clock operation, the extemal clock is uperatable up to DC ~ 1/2 system clock. ** The bit rate is shown as follows with the TCONR as N. . = 4a) £1 input clock frequency to the Bit Rate (us/bit) i timer 2 counter N=0~ 255 Table 10 Baud Rate and Time Constant Register Example 24576Mne | 36864MHe a.oMHr 110 ri Era Erg wr 7 150 127 191 207 255 si 300 63 95 103 127 207 600 31 a 51 63 103 1200 15 2a 25 3 51 (2400 7 Ww 12 15 25 4800 3 5 7 12 9600 1 2 3 19200 ° 1 _ 38400 - - oO - TETB cick i provided 10 the timer Pup counter, | @HITACHI | Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 701

Table 11. SCI Format and Clock Souree Contra 2 TIMER, SCI STATUS FLAG OCR and the FCR. Table 12. Timer 1, Timer 2 and SCI Status Flag

1. Framing Error (Asynchronous Mode) 1. Read the TACSR then ADR, when ORFE=1
2. Overrun Error (Asynchronous Mode)
3. Clocked Synchronous Mode (Note) Clea TORE after setting TE.
4. For example; “ICRH” mesns High byte of ICR

TT _D63701X0, HD637A01X0, HD637B01X0 = LOW POWER DISSIPATION MODE eration. ‘The HD63701X0 provides two low power dissipation modes, sleep and standby. © Standby Mode In MCU mode, the H1D63701X0 stops and reset with STBY © Sleep Mode “tow, In this mode, the power dissipation is reduced con- The MCU will be in the sleep mode when SLP instruction is spicuously. All pins except for the power supply, STBY and executed. In the sleep mode, the CPU stops and the registers’ XTAL are detached from the MCU internally and will be the contents are retained. While the peripherals such as timers, SCl_ high impedance stat. tc. continue their functions. The power dissipation of the sleep- ‘While the contents of RAM is retained. The MCU returns condition is one fifth that of the operating condition from this mode by reset. The followings are typical usage of this ‘The MCU returns from this mode by an interrupt, RES or mode. STBY: it will be reset by RES and the standby mode by STBY. Save the CPU information and SP contents on RAM by RMT. When the CPU responds to an interrupt request, it cancels the Then disable the RAME bit of the RAM control register and set sleep mode, returns to the operation mode and branches to the the STBY PWR bit to go to the standby mode. If the STBY interrupt routine. When the CPU masks this interrupt, it cancels PWR bit is slill sct at reset, that indicates the power is supplied the sleep mode and executes the next instruction. However, for to the MCU and RAM contents are retained property. So system ‘example if the timer | or 2 prohibits a timer interrupt, the CPU _can restore itself by returning their pre-standby informations to doesn’t cancel the steep mode because of no interrupt request. the SP and the CPU. Fig. 26 depicts the timing at each pin with This sleep mode is effective to reduce the power dissipation _this example. for a system with no need of the HD63701X0's consecutive op- vee om a 1 (0) 1 H 0697010 | aes sree | i , [>* 1} ' ro ® 1 ' tor \\ p> bo toot ‘oSave Registers 6 Onzilator o RAM/Port § Control Start Time Register Set mel Restart Figure 26 Standby Mode Timing = TRAP FUNCTION Table 13 Addresses Applicable to Address Errors The CPU generates an interrupt with the highest priority (TRAP) when fetching an undefined instruction of an instruction Moe | 1 | 2 ‘| 3 from non-memory space. The TRAP prevents the system-burst caused by noise of a program error. ‘$0000 ‘$0000 so000 t t t © Op Code Error Address soo1F $001F $003F When fetching an undefined op code, the CPU saves CPU $0100 tegisters as well as a normal interrupt and branches to the TRAP t (SFFEE, SFFEF). This provides the priority next to reset. ‘SEFFF © Address Error ‘When an instruction feich is made excluding internal ROM, _(Note) The TRAP interrupt provides a retry function differently RAM and external memory area, the MCU generates an inter- from other intercupis. This is a program flow return to Fupt as well as an op code error. But on the system with no the address where the TRAP occurs when a sequence re- memory in its external memory area, this error processing is not tums to a main routine from the TRAP interrupt routine applicable if un instruction fetch is made from the external non- by RTI. The retry can prevent the system burst caused by memory area, Table 13 provides addresses where an address noise etc. . error occurs to each mode. However, if another TRAP occurs, the program repeats : This processing is available only for an instruction fetch and is the TRAP interrupt forever, so the consideration is nec- not applicable to the access of normal data read/write essary in programming. | @HITACHI Hitachi America, Ltd. « Hitachi Plaza 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 + (415) 589-8300 703

a HD63701X0, HD637A01X0, HD637B01X0 = INSTRUCTION SET Extended Addressing The HD63701X0 provides object code upward compatible In this mode, the second byte shows the upper 8 bit of the with the HD6801 to utilize all instruction set of the HMCS6800. daia stored address and the third byte the lower 8 bit. This indi- It also seduces the execution times of key instructions for cates the absolute address of 3 byte instruction in the memory. throught improverven indexed Addressing Bit manipulation instruction, change instruction of the index ‘The second byte of an instruction and the lower 8 bit of the register and accumulator and slecp instruction are also added. index register are added in this mode, As for AIM, OIM, EIM ‘The followings arc explained here. and TIM, the third byte of an instruction and the lower 8 bits of = CPU Programming Model (refer to Fig. 27) the index register are added. + Addressing Mode This carry is added to the upper & bit of the index register and + Accumulator and Memory Manipulation Instruction the result is used for addressing the memory. The modified ad- (refer to Table 14) ‘dress is re‘*ined in the temporary address register, so the con- + New Instruction tenis of the index register docsn’t change. This is a 2-byte in- ~ Index Register and Stack Manipulation Instruction struction except AIM, OIM, EIM and TIM (3-byte instruction). (refer wo Table 15) implied Addressing + Jump and Branch Instruction (refer to Table 16) An instruction itself specifies the address. That is, the instruc- (refer to Table 17) byte instruction. + Op Code Map (refer to Table 18) Relative Addressing The second byte of an instruction and the lower 8 bits of the @ Programming Model program counter are added. The carry or borrow is added to the Fig. 27 depicts the 11D63701X0 programming model. The upper 8 bit. So addressing from — 126 to +129 byte of the cur- double accumulator D consists of accumulator A and B, so when rent instruction is enabled. This is a 2-byte instruction. using the accumulator D, the contents of A and B are destroyed. (Note) CLI, SEI Instructions and Interrupt Operation When accepting the IRQ at a preset timing with the help of CLI and SEI instructions, more than 2 cycles are nec- secnunerctteae essary between the CLI and SEI instrucions. For exam- © 16 hs Onur Accummane © ple, the following program (a) (b) don’: accept the IRQ but (c) accepts it. a CS ‘ 1 NOP enon cu cL NOP A 2 ‘SEL NOP NOP COTL TET) evese connie vem . SEI SEI Figure 27 CPU Programming Model @ to) © @ CPU Addressing Mode stead of the CLI and SEI instructions. The HD63701X0 provides 7 addressing modes. The address- ing mode is desided by an insiuction type and code. Table 14 through 18 show addressing modes of each instruction with the When the clock frequency is 4MIIz, the machine cycle time becomes microseconds directly Accumulator (ACCX) Addressing Only an accumulator is addressed and the accumulator A or B is selected. This is a onc-byte instruction. Immediate Addressing This addressing locatcs a data in the second byte of an in- struction, However, LDS and LDX locate a data in the second and third byte exceptionally, This addressing is a 2 of 3-byte in- Drect Addressing In this addressing mode, the second byte of an instruction shows the address where a data is stored. 256 bytes ($0 through $255) can be addressed directly. Execution times can be reduced by storing data in this area so it is recommended to make it RAM for users’ data arca in configurating a system, This is a 2- byte instruction, while 3 byte with regard to AIM, OIM, EIM and TIM. | @HITACHI : 704 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300

a HD63701X0, HD637A01X0, HD637B01X0 Table 14 Accumulator, Memory Manipulation Instructions ssreving Moe wen [fol fo[-[- lor [| a fe nea WERE ENE [“xoos Tee fe t>[osta [2 fee{ela|eafefat {| jeem=e [etary te ‘Aaaposwe [sooo [ca {a[s]os[e[2les|s{2ra[s [a] | [ [a erm wirva oe [ole lafelats ‘Aad Accumulators ae tet tet beet 7 admin cory | aoca [as [alafootafelaslete tele lst [| facwecma frfefe tf ty [“aoce feo {72 ofa | festel2 rolfs| | [yewmecze leh te tty 0 [avon foe fafa foe toffee fe fe] UY tag te [vow [ee {2 |2]oels [2 fee le] [eefala[ [owe eogooo Ba Tew [Ferra fas [> [2 os [3 [2 [asta] 2 fue fe fa] aw pe [are fes|>]z[os}a eles [a[>yes[efat [ew ee tae om [roe fT ter tsta pets ist ft fore Te fetes fa a [reer ee fh foo ae ies fale freee Toe foo ef fe nfs ft Comoe [rows [atl tobtafele lore bt Tf fam [ewe for 2fofor|a fete fefafefepy [Tee ee Some fom TTT TT TTT Tt ete fare eb fete fee Comowmens.re | cow I PP} | [yale balept Tt tex felt als [coma PP es i eae ete tats [reo TE eee es Conoenen Pe [ones PP pte tela pees] fT foo wm ee fot (vega [weca feo a Yoo aa foe TO CC Conve brary 368 9F BOD So from TTT TA Ue fol Neceseames fehE e NS 8 ageooo (occa ea a te te fate I Exctawe oR | _eona [oa [7] [oe [3 fo [ase [2 [6s [e 3] [Tao w= felt Te lay [cone [ca [2 [2 foals fa en[e[> [rele [s[ Tf jeous eT ete tii ies a A A CE a a CS [owe TT feet foe ete tte os a Co 9 NN TC OT Accominor [toms [oe jz |zfos|afzleclelatrelefat | [ [w=e de tefs fe fale Cod Dose seer | coo [ecsfofoc[e[afec[s[frels[a] | [wer-nm en [ele [ele ale wuiveiv Une [wet LP pola faee a el foe ‘OR, tnctse | naa faa la fafaala|afaalelafeate[a] [| [arms [Pir |ale [onae —feala [> [oats fz lente ts [rale[s | [ferme eens Peak Coe ey ee oar ——feretetetede ee es eee Pull Date re Ed Ee eee Oo a OE ee Powers fomox | ttt fp felelapete st ty. [ele ft ole Pro pe) Secs pepe fate es a a aaa Rowsie Reght (aon TTT TT eee tS Compo oa Pee CEHE ERE ET isi PS Ee Co] Py riser: Erbe (Note) Condition Code Register will be explained in Note of Table 17. (continued) @HITACHI Hitachi America, Ltd. # Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 705

HD63701X0, HD637A01X0, HD637B01X0 Table 14 Accumulator, Memory Manipulation Instructions [___sereareieon | eae ope oommare [iameoTormecr [woex exrewo [mnt | Soon00 [or [= [> Jor] [fo [To [ow = Toor] [+] O0806 Ste Late [ase TTY tes fefe pe feta TT — noon oO rere ast TE pe | ccs « fe fe ee fefr ase Ce fee Tor eatin |e | TTT TTT TTT TT del fear [> Se Riana [ase TT fer folate fo fat TT To, — fete tels Ole ome ase PP Pe) poo lero [ase et jogegoo san a eat ite = [ele lal fol tenet EOE EEE Cet leecornttine [eel] ope [see ee felelale tore ae co eee Ron Lopeat pre Sere Re CN AC CO Accomuinor [sta [| for[a fa fer tela ter feist TT fem Tele fete [rye ab 5 Fa ‘Subteet |suea [eo [2]? |oo [ala Jaol« | Joofejs[ TT [a-m=a Pele tete fete “Boar | wee feral fe stssis|e fo Sp] P| [eve srsa oer DoubieSubsraet_ | suao [83 |3| {5 [2 [es [s| fo[efe lets Sire os 0 ‘Siovecs [seca [aa [a [a foe [a fo [aa oa [eo a wea eee wamcary [secs fer fa[z for|a fafa [ele refefs{ [fe-w-cme eee er Tranter ZO 8 OO a A CC Tenzeoo | rst | [TT | | [solelefofalst |} [wooo tele [ets [ata minus [rsa TT Pa a 00 ee a YC SE Andimmesate [Am | Tafelsfertrtst TTT TT fan Pelee te [aye oninmeaawe [om [| [pate fafeatr tay PTL [mane Teo etre “eon immeaawe [om 35) 08 Cole ee OBA CO Teatinmeaate | Ti 7 8 ee OO ECO (Note) Condition Code Register wil be explained in Note of Table 17 In addition to the HD6801 instruction set, the HDt Bp “AND” ccutes “AND" operation to immediate data and prepares the following new instructions. changes the telative fag of the condition code register. “AND" i These area 3-byte instructions; the first byte is op code, the Executes “AND” operation to immediate data and the memory contents and stores its result in the memory. second immediate data and the third address modifier. Executes “OR” operation to immediate data and the ister. memory contents and stores its result in the memory. ‘SLP Executes “EOR™ operation to immediate data and the SIPATION MODE" for more details of the sleep mode memory contents and stores its result in the memory. | @HITACHI ) 706 Hitachi America, Ltd. » Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 (415) 589-8300

HD63701X0, HD637A01X0, HD637B01X0 Table 15 Index Register, Stack Manipulation Instructions Ln “ae ‘Renter, Pointe Operations [—— faster oer ae | ttn REET [or [= [=r |=] lor [=[= lor [-T= [or [= Te] COACH Compwe indexrey [crx Jac[a[afec[elaacts[ztects[a] [ [ [x-wwer Tefeli fitz tt Oreronentinden mea [oem | TTT Pty Pit ft fetter x pelefete fee perme tet eee EEE Increment taden Ree a | ° EN Eo Loesingex Res | tox fee{a[sfoela|zeels|z[rets|s] TT [w=xcmen= xe [ofefa fi fale Cena Swe Pav | vos lor [3 fo ot fe[a acls|afer[s[a{ { [ [was anmas, folie late soreinden eo | ste | | | forfa|zfer{sta|er[sfa]" V [xw=mxcsmen [efoto | [ale ES Ta CO Inde Reg = Stock Pri Pe Te HES o Ec OO fad Lc room eee PP Xie Mig. SP == 5 mo ee Peer SP 1 SP Mg =X Exchange [xcox PETE TTT TTT TT tefets acco Tefefetefole (Note! Condition Cade Register will be explained in Note of Table 17 ‘Table 16 Jump, Branch Instruction ——— ~— [oof =[= fords f= or|=[=tor[=[elor[=[| Eetrfatete G CY OT Branch Newt {eee baat es o tema {rep PE pete Sranch i Cory Bt — $ Genitzwe | eco fa tate] tp Py pe epee fof eenenvtotwe | ace feehafat Tt PPP ttt Ty [wove Tepe fe fetes tenent>zeo {ect fefatat TTT rt Ti rl [wows fefefefe tele Ec pers Pe fob ttt tit dee Peee re ree be eH ECE EEE EE Branch W Minos eer = i Wot . sores oe deb TTT TTT TTT TT fee EE Tench Onviow 5 Bee a ee Wench WOwrow se] evs fatale} TT rr ye ee te te Tete Branch Pit pe ee 5 srnen tosetroutne [ose feof stat TTT TTT rr Boggo Ed Taree pet | ggggad de To Sebrouting [set YY ets 2 frets ta foots Tt — googoo ee eee Rewwen From icwrvorl ate {TT TT pelole — 4 — Return From 5 eo ele EI Softee erat fam ef egogod waintor tovervot® [war TT PT Pr tT pele te maoggo ES A A SA 8 8 OY CC (Note! * WA put RA high: Adress Bus goes 1 FFF; Date Bus becomes sated Condition Code Register wilbe explained in Not of Table 1? @HITACHI Hitachi America, Ltd. © Hitachi Piaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 * (415) 589-8300 707

HD63701X0, HDE37AOIXO, HDOS7BOIXO Table 17 Condition Code Register Manipulation Instructions Condition Code Regater Operations IMPLIED. Boolean Operation [sT«TaJfzy' Je [or [= Tr] Petr tete [ve ‘Cher Corry Se 8 AC a A A XC OC ACC Cie Overt = CS 2 Co CC Se Gory [see roo ee ee ee Ts Set art ME se fore Te = a a “KecamulatorA=CoR | tar_—sdt ow | ttn) ‘A= co = Gon Acconvino A [wa for tv tvy ena Te TT Te Te LEGEND CONDITION CODE SYMBOLS (OP Operation Code (Hexadecimal) He Haltcarey from bit 310 bit = Number of MCU Cyeles 1 Interrupt mask Map Contents of memory tocation pointed to by Stack Pointer Negative (sign bit) 12” Number of rogram Bytes 2 Zero thy), f Antieetic lus V._ Overtion, 2's complement = Arithmetic Minus C Carry/Borrow from/to bit 7 = Goolean AND R Rew Always + Boolean inclusive OR $ Set Always © Boolean Exclusive OR + Set if wue atter test or clear Mi Complement of M Nov attested S Transter into © B= Zero

00 Byte = Zero

{Note Condition Code Register Notes: (Bit set tat ie ue and cleared otherwise) (Biv) Test: Result = 100000007 @ (enc) ‘Test: Result ¥ 000000007 @ (Bec) ‘Test: BCD Character of high-order byte greater than 10? (Not cleared if previously set) @ (Bit) Test: Operand = 10000000 prior to execution? 3) (iV) Test: Operand = 01111115 prior to execution? (®) (Bin) Test: Set equal to N@ C= 5 after the execution of instructions (BN) Tent: Regul tee than tero? (Bit 15*1) @ (ANB) Lo2d Condition Code Register from Stack (Bit 1) Set when nterrupt aceurs. IM previousty set, a Non-Maskable Interrupt is required to exist the wait state (i) (ANBit) Set according to the contents of Accumulator A (3) (BitC) Result of Multiplication Bit 7=17 (ACB) Table 18 OP-Code Map er te | [rp Pr wo oT | Dees J a PO Pepe ype pape ts fe fe pepe pete pe Tote Try few eee ee ee = | eT] A a a a a CU [3] [ovo] « [con [J ece [ors [tsk [a [paso [Tees ras fo [« [tar [a8] [psua [ROR [onni| 7 [wa [Tex [aca [ rene [ase sta esr [insole [iwx | XGox] eve [rucx[ ast ton eT [wiofa fev [scr lore [ax | pre ee ee CY) Pe ee ime Hirota no [nerfof see far [wow | rsh ase [ae Tso | Ea ea ee ee CS a Ee ee =< | StS. [eT six fF} Ce fe pets pepe terete tse te Pepe Tele unotsined or coor =D | + Occurs only on each instruction of AIM, OIM. EIM, TIM @HITACHI 708 Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300

—______ 163701X0, HD637A01X0, HD637B01X0 = CPU OPERATION ‘© CPU Instruction Flow When operating, the CPU fetches an instruction from a memory and executes the required Functions. This sequence BS Pe, starts after the reset release and repeats itself timitiessly if not af- €& a fected by a special instruction or a control signal. SWI, RTI, WAI D s\\> Sans °° and SLP instructions are to change this operation, while NMI, & ANS TRO, TRO,, IRQ,, HALT and ‘STBY are to control it. Fig. 28 2\\5 Z gives the CPU mode shift and Fig. 29 the CPU system flow- RESn0 a chart. Table 19 shows the CPU operating states and port states =o © Operation at Each Instruction Cycle > st 2 ‘Fable 20 provides the operation at each instruction cycle. By the [2 & pipeline contol ofthe HDSOTOINO, MULT, PUL. DAA and XGDX aNs NS 5 instructions ctc. prefetch the next instruction. So atiemtion is necessary 10 Zy oN ry the counting of the instruction cycles because it is different from the > WO existent one from op code fetch to the next instruction op code 3 \\ & Standby \\_STBY=0 Table 19 CPU Operation State and Port State Mode Port [Mode [Rem [sraye-++ [watt- | sieeo | Mose 1.2 [ #_| 4 iene penizte t+ fo = Figure 28 CPU Operation Mode Transition met Reese tt BE te Port t y prt Pon [Mode 2 | Hy w tas~ Aud [Mode 3 [7 || Keo me fe | Pons fweeets | os Lee Keto [Mode 3 | [| por? PMoeez] <P > fo] [Mode 3 [TI [| Kero Hi; High, L; Low, Ts High Impedance + A, WR, RAW, CIR=H, BASL #2 RO, WA, R/W-T, CIR, BA-H 1° HAUT is unacceptable in mode 3. ++ Eppin goes to high impedance state. @HITACHI Hitachi America, Ltd. « Hitachi Plaza * 2000 Sierra Point Pkwy. « Brisbane, CA 94006-1819 « (415) 589-8300 709

HD63701X0, HD637AQIXO, HD637BOIXO age 8 y. gae2 28 B Ey 2 - 6 eave] oS || | oe ag | js OI & EHE i asl Lal a[lGhooe 109-909 1-04) 710 Hitachi America, Ltd. © Hitachi Plaza « ns ACH Brisbane, CA 94005-1819 # (415) 589-8300

OO __ HD63701X0, HD637A01X0, HD637B01X0 Table 20 Cycie-by-Cycle Operation Meniare ROC AOD i Cae RTT TF Seen De AND Bit Op Cove adavess 12 i fo Next Op Cove cp €OR ton ona sec__ Sue 3000 cx 1 Ba tose Rae aad Baie SET too” tos 3 | 2 | opcose admess «2 Operard Date 158) tox__sus0 3 | Ob come aawess 3 Net Op Cove oinect ROC KOE Op Cae RaBETT Rear OBST TSE ano ar Aedes of Ovmnan Operand Date cme €OR Op cove Adsrese¥? Nest Op Code toa Ona sec_svB St OP Code RITES Desa RITES Cesuravon Ades Accumulator Data Op Code Adovess 2 Nest Op Code AOD OK Op Case Adare > Kasra ot Opera TST too” tos adress of Operand 8 Operand Dato MSBi tox suBo Adsress of Operard ° Operand Date USB On cove Adsress+? ° Nest Op Code

5 Optooe Aaaressrt Best Rares SBT

six Desunavan Address Repster Dera (MSB) Desonauon Addess 9 Regster Date (58) Op cove Adaress 2 Nett Op Code aR ‘Op-Code Rares TT po une Rares USB) were tla da estar Ades SB) Stock Ponte o}i fo fewin Address (LSB) Stes Pomter-4 o |i fo fewwn Address (MSD) dump Address v|o |S Fart Suprovine Op Code

7 Dip Code Raarena7 Tomes Date

Op Cove Adoress +2 Aodress of Operand (LSB) ‘advoss of Operand Operand Data Op-Code Addiess 3 Nest Op Code aE ‘Op Code Roars FT 0 innnedate Date om Op Code Adsress+ 2 Aedress of Operend (LSB) ‘adress of Opersnd Operand Date free Restart agaess (S81 ‘Address of Operand New Operand Data Op cose Adcreset 3 Nest Op Code (Continued) @HITACHI Hitachi America, Ltd. Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 711

HD63701X0, HD637A01X0, HD637B01X0 imoexeo THF TY oa Cone Rae 5 OF 2 | rr Restart Addvess (SB) 3_| dum Address Fst Op Code of rp ovine OC ROB 1 [op code KasressT 3 Ofser AND ely 2 | ee Restart Address (LSB) CMP EOR 3 | evonset Operand Oate (Dx Ona 3 | op code Adsess 2 Nest Op Code sec SUB 1st 31H Op Code RATESTT 3 Weer rere Restart Address (SB) x voter ‘Accumulator Data Op Code Addiess +2 Next Op Code 7005 1 on Code Raaress 3 Feet crx LoD 2 | re Restart Addvess1LS8! tos tox 3 | ixvottser Operand Date (MSB} uso 2 | ix rortere1 Operand Data (SB) 5_| op cove adiress+2 Nest Ov Code s¥O St TP op code aaarest +t 3 Ose six 2 | err Restart Addvess (S81 3 | ix+ortser Regates Date (SB! a | oromserss Register Data (LSB) 5 | Op cove Adivess+? New On Code TF Op Cade Rodress? To Otset rere vf Restart Address (LSB) Stace Ponter of 5 few Address (USB) Stact Pomtet 1 of 4 Retwn Address (SB) Xs Ofse Lipo Fast Subroutine Op Code ASC ASR Op Code Raa Po ist com o€c fare bada Restart Address (LSB) we Usk x Offset ro Operand Oata NEG ROL free id Restart Address (LSB) OR 1x Ofer o|4 New Operand Data Op Cove Address +3 to Newt Op Cave ry Op Code Raa T O-] | 1 iewmesiaie Data Op Code Adgess +2 of 4 | 4 | ote reer Sf] ot | a | restart Aadress ase ks Oftset 0 | t | 4 | Opernd date Ob Code Address +3 o | 1 | 0 | Neston cove TUR ‘Op-Code Adress T Ota fr Restor Address (LS8) + oftset Operand Date xsOMeet 00 Op Cove Aderess +2 Nest Op Code tim ‘Op Code AasiesesT 3 Termes Dae om 0p Cove Address +2 Otiset free Restart Address (LSB) 1xs Ofer Operand Date rer Restart Adsress (LSB) 1x +ofset New Operand Data Op Code Address43 Next Op Code (Continued) | @ HITACHI 712 Hitachi America, Ltd. * Hitachi Plaza ¢ 2000 Sierra Point Pkwy. ¢ Brisbane, CA 94005-1819 * (415) 589-8300

HD63701X0, HD637A01X0, HD637B01X0 Sarees Wade oo im See ee] mee [ew] we] oe exten J OF UGE RETOATT aap arene ISBT [2 | Oo Goae ares? Time aasress 38" dmp Address Newt Op Code KOC 0D Op Code Address +7 6 “Address of Operand (MSB) AND ott Op Cove Address +2 ‘address of Operand (LSB) cue con ‘adress of Operands Operand Data (Da ORA Op Code Adoess 3 Nest Op Code sec_suB Op Case Rae v1 5 Daven Rares OASDT Op Code Address +2 Destination Address SBI Desonaton Address Accumdstor Data Op Code Address +3 Nest Op Code Doo Op Code Address 3 ‘adress of Operand MSE) GPx” Loo Op Code Address +2 1] Address of Operand (LSB) los Lx Address of Opetand r|o Operand Data [MSE sv80 redress of Operands | 1 | 0 Operand Data (50) Op Code Address 3 io Next Op Cove D Op Code Adaress +7 3 Destinator AOGreas AEDT six Op Code Address +2 Destination Address (LSB) Destination Address Register Data (MSB) Destinon Address +1 Aegster Oat ((SB) Op Code Address 3 Newt Oo Code SR ‘Op Code Aadress +7 Tarp Rae SET Op Code Address +2 “lump Address (LS) free Restart Address (S01 Stack Pointer fetwen Address (LSB) Sack Pornter=1 Retwn Address (MSB) dump Address frst Sebrovtne Op Code 5S ASH Op Code Raaieas TT 9 1 [-Adaress of Operand (MSE) com DEC Op Code Address-+2 1 | Address of Operand (LSB) INC) USR [Address of Operand 1 | Operand Oata Neo ROL fer + | estar address U6) ROR ‘Address of Operand 1 | New Operand Osta Op Code Address +3 0_| Nest Op Code TH Op Coor Radress 3 ‘Rada of OpeTond WISE Op Code Address +2 Aedress of Operand (LSB) Address of Operond Operand Osta ‘Address of Operond ry Op-Code adders 3 Next Op Code {Continued} @ HITACHI Hitachi America, Ltd. # Hitachi Plaza © 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 « (415) 589-8300 713

HD63701X0, HD637A01X0, HD637B01X0 Tareas Mode 77 tame [oo] Aeennm [ow] 0 [we [ow] omen mpuieo aK BK Op Code AaaressTT Tt OF Coe ASL ASLO ASR CBA ac cu cur civ com DEC DES Ex INC NS wx SR USO ROL ROR NOP SOA SEC sel Sev TAB TAP TeA TPA 1st 15x 1xs BA 5 Op Cade Rares F7 Wont Op Code ucR FUE Op COGS RaareaeFT Next Op Code ree Restart Address (LSB) RFR Bp Code harass eT 3 Went Op Code rrr Restart Address (LSB) Stack Powter ‘Accumulator Oata Op Code Address +1 Nest Op Code UL ‘Op Code Address + o ‘Next Op Code reer Aestart Address (LSB) Stack Powter +1 Data trom Stack (MSB Stack Pooter +2 Data from Stack (L580 PH Op Cade Address #7 2 Next Op Code rere Restart Address (58) Stach Ponte Index Register (LSB) Stack Powter—1 tndos Register (SB) Op Code Address +1 Next Op Code a Op Coae Radress* 0 fest Ob Code reer estat Address (S01 Stack Pomter+1 Return Adress (MSB) Stack Pointer +2 Rewwn Address (SB) Retwen Adaress Fst Op Cade of Rat Resting mor 1} Op Cade Raress > 3 0] Newt Op Code 2 | reer Restart Address (LSB a | vere Restart Address (LSB) a | sere Restart Address (LSB) S| Fre Restart Address (LS6) 6 | Fre Restart Address (LSB) 7_| frre Restart Address (LS81 (Continued) | @HITACHI : mN4 Hitachi America, Ltd. * Hitachi Plaza * 2000 Sierra Point Pkwy. * Brisbane, CA 94005-1819 + (415) 589-8300

a HD63701X0, HD637A01X0, HD637B01X0 A A ia Woe eye a eld marie Wai Op Cade Aa TT Ty Wan Op Code reve rfa fa Restart Adéress (LSB) Stack Poster o|1|o Return Address (LSB) Stark Pownter~1 0 |i jo Return Address (MSB) Stack Powter=2 0 | 1 |o Index Regrster (LSE) Stack Pomnter=3 0 | 1 |o Index Register (MSO) Stack Pomter = o | 1 | o ‘ecurdstor A Stack Pomter—5 2] 1 | 0 ‘ecumoator 8 Steck Ponter—6. oj: |o Condonet Cade Register ATT Op Code Raaresn FT 3 Next Op Cove free 1 Restart Address (58) Stack Pomters 4 ° Conditional Code Register Stock Powter #2 ° decorator 8 Stack Powter +3 ° fecumator A ‘Stack Powter +4 ° Index Register (MSB) Stack Pomnter +5 ° inden Register (LSB) Stack Powter 6 ° Return Address (MSB) Stack Pomter +7 ° Return addres (8) Rein Address ° Fs Op Code of Retr Ration ar 1 }-Op Code Adarese FT t+ Op Code 2 | ere 1 1 Restart dees (LSB) 3 | ‘stack Pomter ° o evra Address (LSB) 2 | Stock Powter 1 ° ° Return Address (MSB) 5 | Stack Powter? ° ° Index Register (LSB) 6 | Stack Pomter—3 ° ° Index Register (MSB) > | Stack Pomter=& ° ° ‘ccurndator A 8 | Stack Powter 5 ° ° ‘ccurdator B 3 | Stack Pomter6 ° ° Cendivansl Code Ragiter 10 | Vector Aadvess FFFA 1 : adress of SW Rosiew ASB) Tt | Vector Address FFFB 1 1 Aedes of Wt Rosine ASD. 12_| Aedeess of Swi Rouse | 1 : Fest Op Cove of SM Rovine sl 1 Op Code Rasrens 3 1] Wen Os Code 2 | rr re] or |r |r | pester nares ws silo | I | 3 | see tL a [+ | estar Aare 058) 4 | 09 Code Address +1 to 11 | 0 _| neon cove RELATIVE x Op Cae Raa 3 Taner OHat sco AGE ree Restart Address (SB) ect BH (tne dato te Frat Op Code of Branch Rosine ee ats On Com ates 1 Tests" Nett Op Code eit eM ONE Bre BRA BRN bree 5S Op Coda KaareaeFT o ‘Feet ree Restart Address (LSB) Stack Pomter Rewwen Address (LSB) Stack Poter—1 Return Address (MSB) Branch Aderese Fest Op Code of Siena @ HITACHI Hitachi America, Lid. * Hitachi Plaza * 2000 Sierra Point Pkwy. © Brisbane, CA 94005-1819 * (415) 589-8300 715

HD63701X0, HD637A01X0, HD637B01X0

1 DIFFERENCES BETWEEN HD63701X0 AND HD6301X0

function MCU mode; Connected to Vgg voltage Connected to Vsg Voltage PROM mode; Input for the programming voltage Input capacitance Vpp/OE, 25pF max All inputs, 12.5pF max Ail other inputs, 12.5pF max Input high voltage Vi = Vgg - 0.5V min Vin = 2.0V min of MPo, MP4 Bus Timing [_T Hoss7o1xo “[ wbes7aoixo T woes7eorxo | [| wossorxo [ Hosaaorxo | HoesB01x0 | * Address, RW, = [i [70 Tas 0 ge [eo sos hold timing ee * Data hold timing Une Unie na Crystal oscillator Internal resistance of crystal oscillator —_Internal resistance of crystal oscillator characteristics Rg Rs [Femeyaais [2s [<0 Teo Tao] Rs = 600 max [Remax [500 T r20 j 20 [80 J Storage Taig = 55 to 125°C Tatg = -55 to 150°C temperature Caution The HD63701X0 differs from HD6301X0 in chip design and manufacturing process. When applying the HD63701X0 system to HD6301X0, and HD6301X0 system to HD63701XO, note that characteristic values are not exactly the same even if guaranteed values are the same. 1@ PRECAUTION TO THE BOARD DESIGN OF OSCILLATION e-em max —e| CIRCUIT as signal ines As shown in Fig. 30, there is a case that the cross talk disturbs the ZZ ZS imams ‘normal oscillation if signal lines are put near the oscillation circuit. GZ Lj ‘When designing a board, pay attention to this. Crystal and C, must be ANAS Y put as near the HD63701X0 as possible. y) x Be go H zB GZ at LY cas 2 ¢ oe ‘ Ft $f exTaL, La : D69701x0 Hoss701%0 : (DP-64S) Do not use this kind of print board design. (Top view) Figure 20 Precaution fo the board design Figure 31 Example of Oscillation Circuits in Board Design @HITACHI | 716 Hitachi America, Ltd. « Hitachi Plaza » 2000 Sierra Point Pkwy. « Brisbane, CA 94005-1819 « (416) 589-8300