HCTL-2032 AVAGO | Alldatasheet
Document overview
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Technical content
Features
- Interfaces Encoder to Microprocessor
- 33 MHz Clock Operation
- Programmable Count Modes (1x, 2x or 4x)
- Single or Dual Axis Support
- Index Channel Support
- High Noise Immunity:
- Schmitt Trigger Inputs and Digital Noise Filter
- 32-Bit Binary Up/Down Counter
- Latched Outputs
- 8-Bit Tristate Interface
- 8, 16, 24, or 32-Bit Operating Modes
- Quadrature Decoder Output Signals, Up/Down and Count
- Cascade Output Signals, Up/Down and Count
- Substantially Reduced System Software
- 5V Operation (VDD - VSS)
- TTL/CMOS Compatible I/O
- Operating Temperature: -40°C to 100°C
- 32-Pin PDIP, 32-Pin SOIC, 20-Pin PDIP
Applications
- Interface Quadrature Incremental Encoders to Microprocessors
- Interface Digital Potentiometers to Digital Data Input Buses ESD WARNING: Standard CMOS handling precautions should be observed with the HCTL-2032 family ICs.
Part Number Description Package Drawing HCTL-03 3-bit counter, dual axis, decoder and cascade outputs, index channel support, programmable count modes, and 33 Mhz clock operation. A HCTL-03-SC All features of HCTL-03. B HCTL-0 Most of the HCTL-03 features. The device supports single axis, and no decoder out- put and cascade signals. The programmable count mode is set to 4x internally. C PINOUT A PINOUT B PINOUT C HCTL-2032 VDD EN1 EN2 CLK SEL1 OE U/DX U/DY RSTY RSTX CHBY CHBX CHAX CHAY X/Y CNTDECX CNTDECY SEL2 CNTCASX CNTCASY TEST CHIY VSS CHIX HCTL-2032-SC VDD EN1 EN2 CLK SEL1 OE U/DX U/DY RSTY RSTX CHBY CHBX CHAX CHAY X/Y CNTDECX CNTDECY SEL2 CNTCASX CNTCASY TEST CHIY VSS CHIX HCTL-2022 VDD CLK SEL1 OE U/D RST CHA CHB SEL2 TEST INDEX VSS Package Dimensions (dimensions in inches) 1) HCTL - 2032
2) HCTL - 2032 - SC 3) HCTL - 2022
4) HCTL-2032 –SCT (Tape and Reel Version of HCTL-2032-SC) Notes: 1. 10 Sprocket hole pitch cumulative tolerance 0.2 2. Camber in compliance with EIA 481 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole 4. All dimensions in mm
- Including package capacitance
Table 1. Absolute Maximum Ratings Table 2. Recommended Operating Conditions Table 3. DC Characteristics VDD = 5V ± 5%; TA = -40 to 100°C
Description
CLK 5 3 CLK is a Schmitt-trigger input for the external clock signal. CHAX 15 10 CHAX, CHAY, CHB X, and CHB Y are Schmitt-trigger inputs that accept the outputs from a quadrature-encoded source, such as incremental optical shaft encoder. Two channels, A and B, nominally 90 degrees out of phase, are required. CHAX and CHBX are the 1st axis and CHAY and CHBY are the 2nd axis. CHAY 16 NC CHBX 14 9 CHBY 13 NC CHIX 17 11 CHIX and CHIY are Schmitt-trigger inputs that accept the outputs of Index channel from an incremental optical shaft encoder.CHIY 19 NC RSTNX 12 8 This active low Schmitt-trigger input clears the internal position counter and the position latch. It also resets the inhibit logic. RSTX/ and RSTY/ are asynchronous with respect to any other input signals. RSTX/ is to reset the 1st axis counter and RSTY/ is to reset the 2nd axis counter. RSTNY 11 NC OEN 7 5 This CMOS active low input enables the tri-state output buffers. The OE/, SEL1, and SEL2 inputs are sampled by the internal inhibit logic on the falling edge of the clock to control the loading of the internal position data latch. SEL1 6 4 These CMOS inputs directly controls which data byte from the position latch is en - abled into the 8-bit tri-state output buffer. As in OE/ above, SEL1 and SEL2 also con- trol the internal inhibit logic. BYTE SELECTED SEL1 SEL2 MSB 2ND 3RD LSB 0 1 D4 1 1 D3 0 0 D2 1 0 D1 SEL2 26 17 EN1 2 NC These CMOS control pins are set to high or low to activate the selected count mode before the decoding begins. Count Modes EN1 EN2 4x 2x 1x 0 0 Illegal Mode 1 0 On 0 1 On 1 1 On EN2 3 NC X/Y 32 NC Select the 1 st or 2 nd axis data to be read. Low bit enables the 1 st axis data, while high bit enables the 2nd axis data. CNTDECX 27 NC A pulse is presented on this LSTTL-compatible output when the quadrature decod- er (4x/2x/1x) has detected a state transition. CNTDECX is for 1 st axis and CNTDECY is for 2nd axis. CNTDECY 28 NC U/Dx 8 6 This LSTTL-compatible output allows the user to determine whether the IC is count- ing up or down and is intended to be used with the CNTDEC and CNTCAS outputs. The proper signal U (high level) or D/ (low level) will be present before the rising edge of the CNTDEC and CNTCAS outputs. U/Dy 9 NC Functional Pin Description Table 4. Functional Pin Descriptions
CNTCASX 25 NC A pulse is presented on this LSTTL-compatible output when the HCTL-2032 / 2032- SC internal counter overflows or underflows. The rising edge on this waveform may be used to trigger an external counter.CNTCASY 24 NC TEST 23 16 This pin is used for internal testing. Tied it to ground or leave it floating for normal operation. D0 4 2 These LSTTL-compatible tri-state outputs form an 8-bit output ports through which the contents of the 32-bit position latch may be read in 4 sequential bytes. The MSB is read first followed by the rest of the bytes with the LSB is read last. D1 31 20 D2 30 19 D3 29 18 D4 22 15 D 4 D 0 3 D 0
- tclk - max delay (item 20/21) + min delay (item 22/23)
- tclk - max delay (item 22/23) + min delay (item 20/21)
Table 5. Switching Characteristics
scribed in the following sections.
32 Bits Binary
32 Bits Latch Octal 4 bit
Figure 10. Simplified Logic Diagram
Figure 12. Signal Propagation through Digital Noise Filter able to provide better system control. and a direction signal to the integral position counter.
4 Valid State
0 Pulse
0 Pulse - Pulse -
Figure 13. 4x Decoder Mode Figure 14. 2x and 1x Decoder Modes gate in a maximum of seven clock periods. B. The system is cyclic with 32 bits of count per cycle. system uses the data to interpolate within the cycle. position from these periodic position updates.
3 L L L Read 3rd Byte
4 H L L Read LSB
Figure 15. Four Bytes Read Sequence hibit logic, enabling the latch. 20XX-XX, the data latch is 32 bit wide.
tion delays through the external counters and registers. update again till the inhibit is reset. updated when the internal latch is inhibited. counted by the external counter and is not lost. cle will show FFFFFFFFh from the HCTL-2032 / 2032-SC. the external latch will read F1h. Figure 16. Decode and Casade Output Diagram (4x)
lines D0-D7 are connected to the Atmel AVR bus port. Figure 17. An HCTL-2032-to-Atmel AVR Interface
Figure 18. Typical Program for Reading HCTL-2032 with Atmel AVR
Get_hi: Hi_old = Pina ‘Get current data Hi_new = Pina ‘Get 2nd Data If Hi_new = Hi_old Then Result_hi = Hi_new ‘Get stable data Return Else Goto Get_2nd End If Get_2nd: 2nd_old = Pina ‘Get current data 2nd_new = Pina ‘Get 2nd Data If 2nd_new = 2nd_old Then Result_2nd = 2nd_new ‘Get stable data Return Else Goto Get_2nd End If Get_3rd: 3rd_old = Pina ‘Get current data 3rd_new = Pina ‘Get 2nd Data If 3rd_new = 3rd_old Then Result_3rd = 3rd_new ‘Get stable data Return Else Goto Get_3rd End If Get_lo: Lo_old = Pina ‘Get current data Lo_new = Pina ‘Get 2nd Data If Lo_new = Lo_old Then Result_lo = Lo_new ‘Get stable data Return Else Goto Get_lo End If Figure 18 Cont. Typical Program for Reading HCTL-2032 with Atmel AVR
For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright © 00 Avago Technologies Limited. All rights reserved. Obsoletes 99-000EN AV0-009EN - January , 00 Actions 1. At first, Port B4, B5, and B6 are setup for 4X encoding and X/Y axis selection. 2. The HCTL-2032 detects that OE/ are low on the next falling edge of the CLK and asserts the internal inhibit signal. Data can be read without regard for the phase of the CLK. 3. SEL1 and SEL2 are setup to select the appropriate bytes. The “Get_hi” subroutine is called and the data is read into the AVR. 4. Step 3 is repeated by changing the SEL1 and SEL2 combinations and specific subroutine is called to read in the appropriate data. 5. The HCTL-2032 detects OE/ high on the next falling edge of the CLK. The program set OE/ high by writing the correct value to the respective Port. This causes the data lines to be tristated. On the next rising CLK edge new data is transferred from the counter to the position data latch. 6. For displaying purposes, the data is arranged in 32- bit data by shifting the MSB to the left through multiplication.