HCTL-2017 AVAGO | Alldatasheet
Document overview
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- PDF pages: 12
Technical content
Features
- Interfaces Encoder to Microprocessor
- 33 MHz Clock Operation
- High Noise Immunity: Schmitt Trigger Inputs and Digital Noise Filter
- 16-Bit Binary Up/Down Counter
- Latched Outputs
- 8-Bit Tristate Interface
- 8 or 16-Bit Operating Modes
- Quadrature Decoder Output Signals, Up/Down and Count
- Cascade Output Signals, Up/Down and Count
- Substantially Reduced System Software
- 5V Operation (VDD – VSS)
- TTL/CMOS Compatible I/O
- Operating Temperature: -40 °C to 85 °C
- 16-pin and 20-Pin Launch Pad
Applications
- Interface Quadrature Incremental Encoders to Microprocessors
- Interface Digital Potentiometers to Digital Data Input Buses
Description
The HCTL-2021/2017 is CMOS ICs that performs the quadrature decoder, counter, and bus interface function. The HCTL-2021/2017 is designed to improve system performance in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-2021/2017 consists of a quadrature decoder logic, a binary up/down state counter, and an 8-bit bus interface. The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2021/2017 contains 16-bit counter and provides TLL/CMOS compatible tri-state output buffers. Operation is specified for a temperature range from –40 to +85 °C at clock frequencies up to 33MHz. The HCTL-2021/2017 provides quadrature decoder output signals and cascade signals for use with many standard computer ICs. The HCTL-2021/2017 is compliant to RoHS directive and had been declared as a lead free product. Devices Part Number Description Pinout HCTL-2017 33 MHz clock operation. 16-bit counter. PINOUT A HCTL-2021 33 MHz clock operation. 16-bit counter. Quadrature decoder output signals. Cascade output signals. PINOUT B
Soldering and Mounting Considerations It is recommended to use manual soldering for HCTL- 2021/2017 launch pad devices due to the characteristics of the material used in the launch pad design that not allow wave soldering. Direct mounting on printed circuit board (PCB) only is recommended for HCTL-2021/2017 launch pad devices. Mounting gap of 1mm between the base of the launch pad and customer’s printed circuit board (PCB) is required. NOTE: Precaution is required in order to avoid bend or loose pin during product handling. Length (L) Width (W) Thickness (T) CLK SEL OE RST CH B CH A VSS VDD PINOUT A VDD CNTdec CNTcas CLK SEL OE U/D NC RST CH B CH A VSS 165 201 PINOUT B (dimension in mm) HCTL-2021 SHOWN PIN DRAWING Package Dimensions with Tolerances
Table 2. Recommended Operating Conditions Table 3. DC Characteristics VDD = 5V ± 5%; TA = -40 to 85 °°°°°C Table 1. Absolute Maximum Ratings
- Including package capacitance but excluding PCB capacitance.
Table 4. Functional Pin Descriptions CLK 2 2 CLK is a Schmitt-trigger input for the external clock signal. channels, A and B, nominally 90 degrees out of phase, are required. with respect to any other input signals. of the clock to control the loading of the internal position data latch. also control the internal inhibit logic. present before the rising edge of the CNT DCDR and CNT CAS outputs. may be used to trigger an external counter. NC NA 6 Not connected - this pin should be left floating.
The quadrature decoder decodes the incoming filtered signals into count information. This circuitry multiplies the resolution of the input signals by a factor of four (4X decoding). The quadrature decoder samples the outputs of the CHA and CHB filters. Based on the past binary state of the two signals and the present state, it outputs a count signal and a direction signal to the integral position counter. Figure 9 shows the quadrature states of Channel A and Channel B signals. The 4x decoder will output a count signal for every state transition (count up and count down). Figure 9 shows the valid state transitions for 4x decoder. The 4x decoder will output a count signal at respective state transition, depending on the counting direction. Channel A leading channel B results in counting up. Channel B leading channel A results in counting down. Illegal state transitions, caused by faulty encoders or noise severe enough to pass through the filter, will produce an erroneous count.Figure 9. 4x Decoder Mode 1 23 4 clk state chA chB Tes Te Telp
4 Valid State
(Count Up & Count Down) 10 1 P u l s e 11 2 P u l s e 01 3 P u l s e 00 4 P u l s e Design Considerations The designer should be aware that the operation of the digital filter places a timing constraint on the relationship between incoming quadrature signals and the external clock. Figure 8 shows the timing waveform with an incremental encoder input. Since an input has to be stable for three rising clock edges, the encoder pulse width (t E - low or high) has to be greater than three clock periods (3t CLK). This guarantees that the asynchronous input will be stable during three consecutive rising clock edges. A realistic design also has to take into account finite rise time of the waveforms, asymmetry of the waveforms, and noise. In the presence of large amounts of noise, t E should be much greater than 3t CLK to allow for the interruption of the consecutive level sampling by the three-bit delay filter. It should be noted that a change on the inputs that is qualified by the filter will internally propagate in a maximum of seven clock periods. The quadrature decoder circuitry imposes a second timing constraint between the external clock and the input signals. There must be at least one clock period between consecutive quadrature states. As shown in Figure 8, a quadrature state is defined by consecutive edges on both channels. Therefore, t ES (encoder state period) > tCLK. The designer must account for deviations from the nominal 90 degree phasing of input signals to guarantee that tES > tCLK. Position Counter This section consists of a 16-bit binary up/down counter which counts on rising clock edges as explained in the Quadrature Decoder Section. All 16-bit of data are passed to the position data latch. The system can use this count data in several ways: A. System total range is d ≤ 16 bits, so the count represents "absolute" position. B. The system is cyclic with ≤ 16 bits of count per cycle. RSTN (or CHI) is used to reset the counter every cycle and the system uses the data to interpolate within the cycle. C. System count is > 8 or 16 bits, so the count data is used as a relative or incremental position input for a system software computation of absolute position. In this case counter rollover occurs. In order to prevent loss of position information, the processor must read the outputs of the IC before the count increments one-half of the maximum count capability. Two's-complement arithmetic is normally used to compute position from these periodic position updates. D. The system count is >16 bits so the HCTL-2021/2017 can be cascaded with other standard counter ICs to give absolute position.
asynchronously by the RST signal. inhibit logic, enabling the latch. not the output bus is in the high-Z state. Figure 10. Two Bytes Read Sequence Figure 11. Simplified Inhibit Logic outputs are not affected by the inhibit logic. affected by the inhibit logic.
1 L L Falling 1 Set inhibit; read high byte
2 H L Falling 1 Read low byte; starts reset
3 X H Falling 0 Complete inhibit logic reset
latch is used to count any count that exceeds 16 bits. 2017 internal counter/latch combination. starts as the HCTL-2021/2017 internal counter rolls over. and do not update again till the inhibit is reset. Figure 12. Decode and Cascade Output Diagram (4x) get updated when the internal latch is inhibited. external latch will read F1h.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved. Obsoletes 5989-4610EN AV01-0353EN - September 13, 2006