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HCT7000M, HCT70000MTX, HCT7000MTXV © TT electronics plc Issue A 11/2016 Page 1 OPTEK Technology, Inc.
1645 Wallace Drive, Carrollton, TX 75006|Ph: +1 972 323 2200
www.optekinc.com | www.ttelectronics.com General Note TT Electronics reserves the right to make changes in product specification without notice or liability. All information is subject to TT Electronics’ own data and is considered accurate at time of going to print. Description: The HCT7000M is a high performance enhancement mode N‐channel MOS transistor chip packaged in the ultra small 3 pin ceramic LCC package. Electrical characterisƟcs are similar to those of the JEDEC 2N7000. The pin‐out and footprint matches that of most enhancement mode MOS transistors built in SOT23 plasƟc packages. TX and TXV devices are processed to OPTEK’s military screening program paƩerned aŌer MIL‐PRF‐19500. TX products receive a VGS HTRB at 24 V for 48 hrs. at 150° C and a VDS HTRB at 48 V for 260 hrs.at 150° C. Applications: Switching applications: small servo motor control, power MOSFET gate drives Relay Drivers High Speed Line Drivers Power Supplies Features: 200 mA ID Ultra small surface mount package RDS(ON) < 5Ω Pin-out compatible with most SOT23 MOSFETS Part Number Sensor Type VDSS Min VGS(TH) Min/ Max ID(ON) (mA) Min Gfs (ms) Min t(ON) / t(OFF) (ns) Max Package HCT7000M N‐Channel Enhanced MOSFET 60 75 100 10 / 10 3‐pin Ceramic HCT7000MTX HCT7000MTXV 0.8 / 3.0
© TT electronics plc General Note TT Electronics reserves the right to make changes in product specification without notice or liability. All information is subject to TT Electronics’ own data and is considered accurate at time of going to print. N-Channel Enhancement Mode MOS Transistor HCT7000M, HCT70000MTX, HCT7000MTXV Issue A 11/2016 Page 2 OPTEK Technology, Inc. www.optekinc.com | www.ttelectronics.com Absolute Maximum RaƟngs Drain Source Voltage 60V Gate‐Source Voltage ±40 V Drain Current 200 mA Power DissipaƟon (TA = 25° C) 300 mW Power DissipaƟon (TS (1) = 25° C) OperaƟng and Storage Temperature ‐55° C to 150° C Thermal Resistance RØJC 100° C/W Thermal Resistance RØJA 583° C/W 600 mW(2) Note: 1) TS = Substrate temperature that the chip carrier is mounted on. 2) This raƟng is provided as an aid to designers. It is dependent upon mounƟng material and methods and is not measurable as an outgoing test. Electrical CharacterisƟcs (TA = 25° C unless otherwise noted) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VDSS Drain Source Voltage 60 V VGS = 0 V, ID = 10 µa VGS(TH) Gate Threshold Voltage .8 3.0 V VDS = VGS, ID = 1 mA IGSS Gate Leakage ±10 nA VDS = 0 V, VGS = ±15 V IDSS Zero Gate Voltage Drain Current 1 µA VGS = 0 V, VDS = 48 V ID(ON) On‐Site Drain Current 75 mA VDS = 10 V, VGS = 4.5 V RDS(ON) Drain Source on-Resistance 5 Ω VGS = 10 V, ID = 0.5 A VDS(ON) Drain Source on‐Voltage 2.5 V VGS = 10 V, ID = 0.5 A Gfs Forward Transconductance 100 mS VDS = 10 V, ID = 0.2 A Ciss Input Capacitance 60 pF VDS = 25 V, VGS = 0 V, f = 1MHz Coss Output Capacitance 25 pF Crss Reverse Transfer Capacitance 5 pF t(on) Turn‐on Time 10 ns VDD = 15 V, ID = 0.5 A, Vgen = 10 V, Rg = 25Ω t(off) Turn‐off Time 10 ns