DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 16
Technical content
Features
Performance Guaranteed over Full Military Temperature Range: -55C to +125C Manufactured and Tested on a MIL-PRF-38534 Certifi ed Line Hermetically Sealed Packages Dual Marked with Device Part Number and DLA Drawing Number QML-38534 HCPL-3120 Function Compatibility 2.0 A Minimum Peak Output Current 0.5V Maximum Low Level Output Voltage (V OL) : Eliminates Need for Negative Gate Drive 10 kV/ s Minimum Common Mode Rejection (CMR) at VCM = 1000V I CC = 5 mA Maximum Supply Current Under Voltage Lock-Out Protection (UVLO) with Hysteresis Wide Operating V CC Range: 15 to 30 Volts 500 ns Maximum Propagation Delay 0.35s Maximun Delay Between Devices CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. SHIELD N/C CATHODE ANODE N/C VCC VO VO VEE
LED V CC - VEE VCC- VEE VO “POSITIVE GOING” (i.e., TURN-ON) “NEGATIVE GOING” (i.e., TURN-OFF) OFF 0 - 30 V 0 - 30 V LOW ON 0 - 11 V 0 - 9.5 V LOW ON 11 - 13.5 V 9.5 - 12 V TRANSITION ON 13.5 - 30 V 12 - 30 V HIGH A 0.1 F bypass capacitor must be connected between pins 5 and 8. Truth Table Selection Guide: Lead Confi guration Options Avago Technologies Part Number and Options Commercial HCPL-5120 MIL-PRF-38534, Class H HCPL-5121 Standard Lead Finish Gold Plate Solder Dipped * Option - 200 Butt Cut/Gold Plate Option - 100 Gull Wing/Soldered * Option - 300 SMD Part Number Prescript for all below 5962- Gold Plate 0420401HPC Solder Dipped * 0420401HPA Butt Cut/Gold Plate 0420401HYC Butt Cut/Soldered * 0420401HYA Gull Wing/Soldered * 0420401HXA * Solder contains lead Device Marking COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) A HCPL-512x 5962-04204 01Hxx 50434 COUNTRY OF MFR. AVAGO CAGE CODE* AVAGO DESIGNATOR DLA SMD* PIN ONE/ ESD IDENT AVAGO P/N DLA SMD* * QUALIFIED PARTS ONLY SGP QYYWWZ Outline Drawing 3.81 (0.150) MIN. 4.32 (0.170) MAX. 9.40 (0.370) 9.91 (0.390) 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) MIN. 0.76 (0.030) 1.27 (0.050) 8.13 (0.320) MAX. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) 7.16 (0.282) 7.57 (0.298) NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Hermetic Optocoupler Options Option Description 100 Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product (see drawings below for details). 200 Lead fi nish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product. DLA Drawing part numbers contain provisions for lead fi nish. 300 Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial and hi-rel product (see drawings below for details). This option has solder dipped leads. 1.14 (0.045) 1.40 (0.055) 4.32 (0.170) MAX. 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) MIN. 7.36 (0.290) 7.87 (0.310) 0.20 (0.008) 0.33 (0.013) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 0.51 (0.020) MIN. 4.57 (0.180) MAX. 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 9.65 (0.380) 9.91 (0.390) 5° MAX. 4.57 (0.180) MAX. 0.20 (0.008) 0.33 (0.013) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 1.07 (0.042) 1.32 (0.052) * Solder contains lead
Electrical Specifi cations (DC) Over recommended operating conditions (TA = -55 to +125C, IF(ON) = 10 to 18 mA, V F(OFF) = -3.0 to 0.8V, VCC = 15 to 30 V, VEE = Ground), unless otherwise specifi ed. Parameter Symbol Test Conditions Group A Subgroups (13) Limits Units Fig NoteMin. Typ. * Max. High Level Output Current IOH VO = (VCC - 4 V) 1, 2, 3 0.5 1.5 A 2, 3, 17 2 VO = (VCC - 15 V) 2.0 A 1 Low Level Output Current IOL VO = (VEE + 2.5 V) 1, 2, 3 0.5 2.0 A 5, 6, 18 2 VO = (VEE + 15 V) 2.0 A 1 High Level Output Voltage VOH IO = -100 mA 1, 2, 3 (V CC - 4) (V CC - 3) V 1, 3, 19 3, 4 Low Level Output Voltage VOL IO = 100 mA 1, 2, 3 0.1 0.5 V 4, 6, 20 High Level Supply Current ICCH Output Open, IF = 10 to 18 mA 1, 2, 3 2.5 5.0 mA 7, 8 Low Level Supply Current ICCL Output Open, VF = -3.0 to +0.8V 1, 2, 3 2.5 5.0 mA Threshold Input Current Low to High IFLH IO = 0 mA, VO > 5 V 1, 2, 3 3.5 9.0 mA 9, 15, 21 Threshold Input Voltage High to Low VFHL 1, 2, 3 0.8 V Input Forward Voltage VF IF = 10 mA 1, 2, 3 1.2 1.5 1.8 V 16 Temperature Coef- fi cient of Forward Voltage VF/TA IF = 10 mA -1.6 mV/C Input Reverse Breakdown Voltage BVR IR = 10 A 1, 2, 3 5 V Input Capacitance CIN f = 1 MHz, VF = 0 V 80 pF UVLO Threshold V UVLO+ VO > 5 V, IF = 10 mA 1, 2, 3 11.0 12.3 13.5 V 22, 37 VUVLO- 1, 2, 3 9.5 10.7 12.0 UVLO Hysteresis UVLO HYS 1.6 *All typical values at TA = 25C and VCC - VEE = 30 V, unless otherwise noted.
Switching Specifi cations (AC) Over recommended operating conditions (TA = -55 to +125C, IF(ON) = 10 to 18 mA, VF(OFF) = -3.0 to 0.8V, VCC = 15 to 30 V, VEE = Ground), unless otherwise specifi ed. Parameter Symbol Test Conditions Group A Subgroups (13) Limits Units Fig NoteMin. Typ. * Max. Propagation Delay Time to High Output Level tPLH Rg = 10 , Cg = 10 nF, f = 10 kHz, Duty Cycle = 50% 9, 10, 11 0.10 0.30 0.50 s 10, 11, 12, 13, 14, 23 Propagation Delay Time to Low Output Level tPHL 9, 10, 11 0.10 0.30 0.50 s Pulse Width Distortion PWD 9, 10, 11 0.3 s 12 Propagation Delay Dif- ference Between Any Two Parts PDD PHL - tPLH) 9, 10, 11 -0.35 0.35 s 33, 34 7 Rise Time t r 0.1 s 23 Fall Time t f 0.1 s UVLO Turn On Delay t UVLO ON VO > 5 V, IF = 10 mA 0.8 s 22 UVLO Turn Off Delay t UVLO OFF VO < 5 V, IF = 10 mA 0.6 Output High Level Com- mon Mode Transient Immunity |CM H|I F = 10mA, VCM = 1000 V, VCC = 30 V, TA = 25C 91 0 kV/s 24 8, 9, Output Low Level Com- mon Mode Transient Immunity |CM L|V CM = 1000 V, VF = 0 V, VCC = 30 V, TA = 25C 91 0 kV/s 8, 10, *All typical values at TA = 25C and VCC VEE = 30 V, unless otherwise noted.
Over recommended operating conditions (TA = -55 to +125C) unless otherwise specifi ed. Parameter Symbol Test Conditions Group A Subgroups (13) Limits Units Fig NoteMin. Typ.* Max. Input-Output Leakage Current II-O VI-O = 1500Vdc, RH 65%, t = 5 sec., TA = 25C 1 1.0 A 5, 6 Resistance (Input-Output) RI-O VI-O = 500 VDC 1010 6 Capacitance (Input-Output) CI-O f = 1 MHz 2.5 pF 6 *All typicals at TA = 25C. Notes: 1. Maximum pulse width = 10 s, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. See Applications section for additional details on limiting IOH peak. 2. Maximum pulse width = 50 s, maximum duty cycle = 0.5%. 3. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps. 4. Maximum pulse width = 1 ms, maximum duty cycle = 20%. 5. This is a momentary withstand test, not an operating condition. 6. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 7. The diff erence between t PHL and tPLH between any two HCPL-5120 parts under the same test condition. 8. Pins 1 and 4 need to be connected to LED common. 9. Common mode transient immunity in the high state is the maximum tolerable dV CM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15.0 V). 10. Common mode transient immunity in a low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V). 11. This load condition approximates the gate load of a 1200 V/75A IGBT. 12. Pulse Width Distortion (PWD) is defi ned as |t PHL-tPLH| for any given device. 13. Standard parts receive 100% testing at 25C (Subgroups 1 and 9). SMD and Class H parts receive 100% testing at 25, 125, and -55C (Sub groups 1 and 9, 2 and 10, 3 and 11, respectively). 14. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specifi ed for all lots not specifi cally tested.
10 KHz
Figure 23. tPLH, tPHL, and tf Test Circuit and Waveforms Figure 24. CMR Test Circuit and Waveforms
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Under Voltage Lockout Feature. Figure 37. Under Voltage Lock Out also in compliance with DLA drawing 5962-04204. mance inspection to MIL-PRF-38534.