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Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
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Technical content
Features
/g120 Easy to use /g120 Interfaces directly with microprocessors /g120 0.15” character height in 4 and 8 character package /g120 0.20” character height in 4 and 8 character package /g120 Rugged X- and Y-stackable package /g120 Serial input /g120 Convenient brightness controls /g120 Wave solderable /g120 Low power CMOS technology /g120 TTL compatible /g120 3.3 V operating voltage
Applications
/g120 Telecommunications equipment /g120 Portable data entry devices /g120 Computer peripherals /g120 Medical equipment /g120 Test equipment /g120 Business machines /g120 Avionics /g120 Industrial controls HCMS-39xx
3.3 V High Performance CMOS
Description Yellow Red Green Orange 1 x 4 0.15” Character HCMS-3901 HCMS-3902 HCMS-3903 HCMS-3904 1 x 8 0.15” Character HCMS-3911 HCMS-3912 HCMS-3913 HCMS-3914 1 x 4 0.20” Character HCMS-3961 HCMS-3962 HCMS-3963 HCMS-3964 1 x 8 0.20” Character HCMS-3971 HCMS-3972 HCMS-3973 HCMS-3974 Absolute Maximum Ratings Storage Temperature, T Soldering Temperature [1.59 mm (0.063 in.) below body] A = 25°C[1] Note: 1. For operation in high ambient temperatures, see Appendix A, Thermal Considerations. Recommended Operating Conditions over Temperature Range (-40°C to +85°C) Parameter Symbol Min. Max. Units Logic Supply Voltage[1] VLOGIC 3.1 5.5 V LED Supply Voltage[1] V LED 3.1 5.5 V GNDLED to GNDLOGIC[1] – -0.3 +0.3 V Note: 1. For further description, see Appendix B, Electrical Considerations, “VLOGIC and VLED Considerations” .
Electrical Characteristics over Operating Temperature Range (-40°C to +85°C) TA = 25°C -40°C < TA < 85°C VLOGIC = 3.3 V 3.0 V < V LOGIC < 5.5 V Parameter Symbol Typ. Max. Min. Max. Units Test Conditions Input Leakage Current I I μA V IN = 0 V to VLOGIC HCMS-390X/396X (4 char) +7.5 -2.5 +50 HCMS-391X/397X (8 char) +15 -5.0 +100 I LOGIC OPERATING I LOGIC (OPT) mA V IN = VLOGIC HCMS-390X/396X (4 char) 0.4 2.5 5 HCMS-391X/397X (8 char) 0.8 5 10 I LOGIC SLEEP[1] ILOGIC (SLP) μA V IN = VLOGIC HCMS-390X/396X (4 char) 5 15 25 HCMS-391X/397X (8 char) 10 30 50 ILED BLANK I LED (BL) mA BL = 0 V HCMS-390X/396X (4 char) 2.0 4.0 4.0 HCMS-391X/397X (8 char) 4.0 8.0 8.0 I LED SLEEP[1] I LED (SLP) μA HCMS-390X/396X (4 char) 7.5 20 50 HCMS-391X/397X (8 char) 15 40 100 Peak Pixel Current pixels ON, average value per pixel HIGH level input voltage V IH 2.4 V 3.0 V < V LOGIC < 5.5 V LOW level input voltage V IL 0.4 V 3.0 V < V LOGIC < 5.5 V HIGH level output voltage V OH 2.4 V 3.0 V < V LOGIC < 5.5 V LOW level output voltage V OL 0.4 V 3.0 V < V LOGIC < 5.5 V Thermal Resistance Rθ J-P 70 oC/W Notes: 1. In SLEEP mode, the internal oscillator and reference current for LED drivers are off. 2. Average peak pixel current is measured at the maximum drive current set by Control Register 0. Individual pixels may exceed this value. Optical Characteristics at 25°C ±1°C[1] VLED = 3.3 V, 100% Peak Current, 100% Pulse Width[2] Luminous Intensity per LED [3] Peak Wavelength Dominant Wavelength Character Average (μcd) λPeak (nm) λd [4] (nm) Display Color Minimum Typ. Typ. Typ. Red 30 128 641 628 Orange 30 128 592 588 Yellow 70 148 583 585 Green 77 252 568 574 Notes: 1. Refers to the initial case temperature of the device immediately prior to measurement. 2. For comparison purpose with existing HCMS-29xx 5 V devices. The Typical and Minimum Luminous Intensity per LED Character Average can be calculated by dividing the values in the table by two for the test condition 50% Peak Current, 100% Pulse Width and V LED = 3.3 V. 3. Measured with all LEDs illuminated in a digit. 4. Dominant wavelength, λ d, is derived from the CIE chromaticity diagram and represents the single wavelength which defines the perceived LED color.
RESET (RST) Sets Control Register bits to logic low. The Dot Register contents are unaffected by the Reset pin. (logic low = reset; logic high = normal operation). DATA IN (D IN) Serial Data input for Dot or Control Register data. Data is entered on the rising edge of the Clock input. DATA OUT (DOUT) Serial Data output for Dot or Control Register data. This pin is used for cascading multiple displays. CLOCK (CLK) Clock input for writing Dot or Control Register data. When Chip Enable is logic low, data is entered on the rising Clock edge. REGISTER SELECT (RS) Selects Dot Register (RS = logic low) or Control Register (RS = logic high) as the destination for serial data entry. The logic level of RS is latched on the falling edge of the Chip Enable input. CHIP ENABLE (CE) This input must be a logic low to write data to the display. When CE returns to logic high and CLK is logic low, data is latched to either the LED output drivers or a Control Register. OSCILLATOR SELECT Selects either an internal or external display oscillator source. (SEL) (logic low = External Display Oscillator; logic high = Internal Display Oscillator). OSCILLATOR (OSC) Output for the Internal Display Oscillator (SEL = logic high) or input for an External Display Oscillator (SEL = logic low). BLANK (BL) Blanks the display when logic high. May be modulated for brightness control. GND LED Ground for LED drivers. GNDLOGIC Ground for logic. VLED Positive supply for LED drivers. VLOGIC Positive supply for logic.
AC Timing Characteristics over Temperature Range (-40 to +85°C) Timing Diagram 4.5 V<V LOGIC < 5.5 V V LOGIC = 3 V
1 Register Select Setup Time to Chip Enable t rss 10 10 ns
2 Register Select Hold Time to Chip Enable t rsh 10 10 ns
3 Rising Clock Edge to Falling Chip Enable Edge t clkce 20 20 ns
4 Chip Enable Setup Time to Rising Clock Edge t ces 35 55 ns
5 Chip Enable Hold Time to Rising Clock Edge t ceh 20 20 ns
6 Data Setup Time to Rising Clock Edge t ds 10 10 ns
7 Data Hold Time after Rising Clock Edge t dh 10 10 ns
8 Rising Clock Edge to D OUT [1] t dout 10 40 10 65 ns
9 Propagation Delay D IN to DOUT
Simultaneous Mode for one IC [1,2] t doutp 18 30 ns
10 CE Falling Edge to D OUT Valid t cedo 25 45 ns
11 Clock High Time t clkh 80 100 ns
12 Clock Low Time t clkl 80 100 ns
Reset Low Time t rstl 50 50 ns Clock Frequency F cyc 5 4 MHz Internal Display Oscillator Frequency F inosc 80 210 80 210 KHz Internal Refresh Frequency F rf 150 410 150 410 Hz External Display Oscillator Frequency F exosc Prescaler = 1 51.2 1000 51.2 1000 KHz Prescaler = 8 410 8000 410 8000 KHz Notes: 1. Timing specifications increase 0.3 ns per pf of capacitive loading above 15 pF. 2. This parameter is valid for Simultaneous Mode data entry of the Control Register.
Register), two 7-bit Control Words, and refresh circuitry. uniquely controls a single LED. Eight-character displays have two ICs that are cascaded. connected directly to both ICs. cleared to all zeros by Reset. the procedure shown in Table 1 and Figure 5. Table 1. Register Truth Table
- BIT D0 of Control Word 1 must have been previously set to Low for serial mode or High for simultaneous mode.
- Selection of Control Word 1 or Control Word 0 is set by D7 of the Control Shift Register. The unselected control word retains its previous value.
- Control Word data is loaded Most Significant Bit (D7) first.
Figure 5. HCMS-39XX write cycle timing diagram displayed. Column 0 controls the left-most column. or not pixels in Column 0 are turned-on or turned-off. will appear to scroll from right to left.
- DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.
Figure 6. Block diagram for HCMS-39xx
40 BIT
Figure 7. Pixel map
The Control Register allows software modification of the IC’s operation and consists of two independent 7-bit control words. Bit D 7 in the shift register selects one of the two 7-bit control words. Control Word 0 performs pulse width modulation brightness control, peak pixel current brightness control, and sleep mode. Control Word 1 sets serial/simultaneous data out mode, and external oscillator prescaler. Each function is independent of the others. Control Register Data Loading Data is loaded into the Control Register, MSB first, according to the procedure shown in Table 1 and Figure 5. First, RS is brought to logic high and then CE is brought to logic low. Next, each successive rising CLK edge will shift in the data on the D IN pin. Finally, when 8 bits have been loaded, the CE line is brought to logic high. When CLK goes to logic low, new data is copied into the selected control word. Loading data into the Control Register takes place while the previous control word configures the display. Control Word 0 Loading the Control Register with D7 = Logic low selects Control Word 0 (see Table 2). Bits D 0 -D 3 adjust the display brightness by pulse width modulating the LED on time, while Bits D 4 -D5 adjusts the display brightness by changing the peak pixel current. Bit D6 selects normal operation or sleep mode. Sleep mode (Control Word 0, bit D 6 = Low) turns off the Internal Display Oscillator and the LED pixel drivers. This mode is used when the IC needs to be powered up, but does not need to be active. Current draw in sleep mode is nearly zero. Data in the Dot Register and Control Words are retained during sleep mode. Control Word 1 Loading the Control Register with D 7 = logic high selects Control Word 1. This Control Word performs two functions: serial/simultaneous data out mode and external oscillator prescale select (see Table 2).
Table 2. Control Shift Register.
Serial/Simultaneous Data Output D 0 Bit D0 of control word 1 is used to switch the mode of DOUT between serial and simultaneous data entry during Control Register writes. The default mode (logic low) is the serial D OUT mode. In serial mode, D OUT is connected to the last bit (D7) of the Control Shift Register. Storing logic high to bit D 0 changes D OUT to simultaneous mode, which affects the Control Register only. In simultaneous mode, D OUT is logically connected to DIN. This arrange ment allows multiple ICs to have their Control Registers written to simultaneously. For example, for n ICs in the serial mode, n * 8 clock pulses are needed to load the same data in all Control Registers. In the simultaneous mode, n ICs only need 8 clock pulses to load the same data in all Control Registers. The propaga- tion delay from the first IC to the last is n * t DOUTP. External Oscillator Prescaler Bit D 1 Bit D1 of Control Word 1 is used to scale the frequency of an external Display Oscillator. When this bit is logic low, the external Display Oscillator directly sets the internal display clock rate. When this bit is logic high, the external oscillator is divided by 8. This scaled frequency then sets the internal display clock rate. It takes 512 cycles of the display clock (or 8 x 512 = 4096 cycles of an external clock with the divide by 8 prescaler) to completely refresh the display once. Using the prescaler bit allows the designer to use a higher external oscillator frequency without extra circuitry. This bit has no affect on the internal Display Oscillator Frequency. Bits D2 -D6 These bits must always be pro-grammed to logic low. Cascaded ICs Figure 8 shows how two ICs are connected within an HCMS-39XX display. The first IC controls the four left- most characters and the second IC controls the four right-most characters. The Dot Registers are connected in series to form a 320-bit dot shift register. The location of pixel 0 has not changed. However, Dot Shift Register bit 0 of IC2 becomes bit 160 of the 320-bit dot shift register. The Control Registers of the two ICs are independent of each other. This means that to adjust the display brightness the same control word must be entered into both ICs, unless the Control Registers are set to simultaneous mode. Longer character string systems can be built by cascading multiple displays together. This is accom plished by creating a five-line bus. This bus consists of CE, RS, BL, Reset, and CLK. The display pins are connected to the corresponding bus line. Thus, all CE pins are connected to the CE bus line. Similarly, bus lines for RS, BL, Reset, and CLK are created. Then D IN is connected to the right- most display. DOUT from this display is connected to the next display. The left-most display receives its D IN from the DOUT of the display to its right. D OUT from the left- most display is not used. Each display may be set to use its internal oscillator, or the displays may be synchronized by setting up one display as the master and the others as slaves. The slaves are set to receive their oscillator input from the master’s oscillator output.
Figure 8. Cascaded ICs
calculated with Equation 4 in Table 3. signifi cantly changing the display brightness. The display uses two independent electrical systems. keep the logic supply clean. LED is also not recommended. above +0.3 V can cause dimming and dot mismatch. and the range of frequencies that need to be suppressed. inputs until VLOGIC has been applied to the display. Table 3. Equations.
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Figure 10. Relative luminous Intensity versus ambient temperature the duty factor. Both values are set in Control Word 0. bright ness as shown in Figure 10. either an external source or the internal source. The 160 bits are organized as 20 columns by 8 rows.