HCMS-39X6 AVAGO | Alldatasheet
Document overview
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Technical content
Features
- Easy to use
- Interfaces directly with microprocessors
- 0.15" character height in 4 and 8 character package
- 0.20" character height in 4 and 8 character package
- Rugged X- and Y-stackable package
- Serial input
- Convenient brightness controls
- Wave solderable
- Low power CMOS technology
- TTL compatible
- 3.3 V operating voltage
Applications
- Telecommunications equipment
- Portable data entry devices
- Computer peripherals
- Medical equipment
- Test equipment
- Business machines
- Avionics
- Industrial controls HCMS-39x6 and HCMS-39x7
3.3 V High Performance CMOS
Figure 1. HCMS-390X package dimensions.
- DIMENSIONS ARE IN mm (INCHES).
- UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
- LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
Figure 2. HCMS-391X Package dimensions.
- DIMENSIONS ARE IN mm (INCHES).
- UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
- LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
Figure 3. HCMS-396X Package dimensions.
- DIMENSIONS ARE IN mm (INCHES).
- UNLESS OTHERWISE SPECIFIED, THE TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
- LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
Figure 4. HCMS-397X Package dimensions.
- DIMENSIONS ARE IN mm (INCHES).
- UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH).
- LEAD MATERIAL: SOLDER PLATED COPPER ALLOY.
1 x 4 0.15" Character HCMS-3906 HCMS-3907 1 x 8 0.15" Character HCMS-3916 HCMS-3917 1 x 4 0.20" Character HCMS-3966 HCMS-3967 1 x 8 0.20" Character HCMS-3976 HCMS-3977 Absolute Maximum Ratings Storage Temperature, T Soldering Temperature [1.59 mm (0.063 in.) below body] A = 25°C[1] Note: 1. For operation in high ambient temperatures, see Appendix A, Thermal Considerations. Recommended Operating Conditions over Temperature Range (-40°C to +85°C) Parameter Symbol Min. Max. Units Logic Supply Voltage[1] VLOGIC 3.1 5.5 V LED Supply Voltage[1] VLED 3.1 5.5 V GNDLED to GNDLOGIC[1] – -0.3 +0.3 V Note: 1. For further description, see Appendix B, Electrical Considerations, “V LOGIC and VLED Considerations”.
Electrical Characteristics over Operating Temperature Range (-40°C to +85°C) TA = 25°C -40 °C < TA < 85°C VLOGIC = 3.3 V 3.0 V < V LOGIC < 5.5 V Parameter Symbol Typ. Max. Min. Max. Units Test Conditions Input Leakage Current I I µAV IN = 0 V to VLOGIC HCMS-390X/396X (4 char) +7.5 -2.5 +50 HCMS-391X/397X (8 char) +15 -5.0 +100 ILOGIC OPERATING I LOGIC (OPT) mA V IN = VLOGIC HCMS-390X/396X (4 char) 0.4 2.5 5 HCMS-391X/397X (8 char) 0.8 5 10 ILOGIC SLEEP[1] ILOGIC (SLP) µAV IN = VLOGIC HCMS-390X/396X (4 char) 5 15 25 HCMS-391X/397X (8 char) 10 30 50 ILED BLANK I LED (BL) mA BL = 0 V HCMS-390X/396X (4 char) 2.0 4.0 4.0 HCMS-391X/397X (8 char) 4.0 8.0 8.0 ILED SLEEP[1] ILED (SLP) µA HCMS-390X/396X (4 char) 7.5 20 50 HCMS-391X/397X (8 char) 15 40 100 pixels ON, average value per pixel HIGH level input voltage V IH 2.4 V 3.0 V < V LOGIC < 5.5 V LOW level input voltage V IL 0.4 V 3.0 V < V LOGIC < 5.5 V HIGH level output voltage V OH 2.4 V 3.0 V < V LOGIC < 5.5 V LOW level output voltage V OL 0.4 V 3.0 V < V LOGIC < 5.5 V Thermal Resistance R θJ-P 70 oC/W Notes: 1. In SLEEP mode, the internal oscillator and reference current for LED drivers are off. 2. Average peak pixel current is measured at the maximum drive current set by Control Register 0. Individual pixels may exceed this value. Optical Characteristics at 25°C ±1°C[1] VLED = 3.3 V, 100% Peak Current, 100% Pulse Width Luminous Intensity per LED [2] Peak Wavelength Dominant Wavelength Character Average (µcd) λPeak (nm) λd[3] (nm) Display Color Min. Typ. Typ. Typ. Red 520 2300 635 624 Green 520 1000 574 572 Notes: 1. Refers to the initial case temperature of the device immediately prior to measurement. 2. Measured with all LEDs illuminated in a digit. 3. Dominant wavelength, λd , is derived from the CIE chromaticity diagram and represents the single wavelength which defines the perceived LED color.
RESET (RST) Sets Control Register bits to logic low. The Dot Register contents are unaffected by the Reset pin. (logic low = reset; logic high = normal operation). DATA IN (D IN) Serial Data input for Dot or Control Register data. Data is entered on the rising edge of the Clock input. DATA OUT (DOUT) Serial Data output for Dot or Control Register data. This pin is used for cascading multiple displays. CLOCK (CLK) Clock input for writing Dot or Control Register data. When Chip Enable is logic low, data is entered on the rising Clock edge. REGISTER SELECT (RS) Selects Dot Register (RS = logic low) or Control Register (RS = logic high) as the destination for serial data entry. The logic level of RS is latched on the falling edge of the Chip Enable input. CHIP ENABLE (CE) This input must be a logic low to write data to the display. When CE returns to logic high and CLK is logic low, data is latched to either the LED output drivers or a Control Register. OSCILLATOR SELECT Selects either an internal or external display oscillator source. (SEL) (logic low = External Display Oscillator; logic high = Internal Display Oscillator). OSCILLATOR (OSC) Output for the Internal Display Oscillator (SEL = logic high) or input for an External Display Oscillator (SEL = logic low). BLANK (BL) Blanks the display when logic high. May be modulated for brightness control. GND LED Ground for LED drivers. GNDLOGIC Ground for logic. VLED Positive supply for LED drivers. VLOGIC Positive supply for logic.
AC Timing Characteristics over Temperature Range (-40 to +85°C) Timing Diagram 4.5 V<V LOGIC < 5.5 V V LOGIC = 3 V
1 Register Select Setup Time to Chip Enable t rss 10 10 ns
2 Register Select Hold Time to Chip Enable t rsh 10 10 ns
3 Rising Clock Edge to Falling Chip Enable Edge t clkce 20 20 ns
4 Chip Enable Setup Time to Rising Clock Edge t ces 35 55 ns
5 Chip Enable Hold Time to Rising Clock Edge t ceh 20 20 ns
6 Data Setup Time to Rising Clock Edge t ds 10 10 ns
7 Data Hold Time after Rising Clock Edge t dh 10 10 ns
8 Rising Clock Edge to D OUT [1] tdout 10 40 10 65 ns
9 Propagation Delay D IN to DOUT
Simultaneous Mode for one IC [1,2] tdoutp 18 30 ns
10 CE Falling Edge to D OUT Valid t cedo 25 45 ns
11 Clock High Time t clkh 80 100 ns
12 Clock Low Time t clkl 80 100 ns
Reset Low Time t rstl 50 50 ns Clock Frequency F cyc 5 4 MHz Internal Display Oscillator Frequency F inosc 80 210 80 210 KHz Internal Refresh Frequency F rf 150 410 150 410 Hz External Display Oscillator Frequency F exosc Prescaler = 1 51.2 1000 51.2 1000 KHz Prescaler = 8 410 8000 410 8000 KHz Notes: 1. Timing specifications increase 0.3 ns per pf of capacitive loading above 15 pF. 2. This parameter is valid for Simultaneous Mode data entry of the Control Register.
groups of 4 characters per IC. uniquely controls a single LED. Table 1. Register Truth Table
- BIT D0 of Control Word 1 must have been previously set to Low for serial mode or High for simultaneous mode.
- Selection of Control Word 1 or Control Word 0 is set by D 7 of the Control Shift Register. The unselected control word retains its previous value.
- Control Word data is loaded Most Significant Bit (D 7) first.
Figure 5. HCMS-39XX write cycle timing diagram. 0 are turned-on or turned-off. stored in Dot Latch location 1. most character being loaded last.
- DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW.
Figure 6. Block diagram for HCMS-39xx.
40 BIT
independent 7-bit control words. Figure 7. Pixel map.
Control Register Data Loading Data is loaded into the Control Register, MSB first, according to the procedure shown in Table 1 and Figure 5. First, RS is brought to logic high and then CE is brought to logic low. Next, each successive rising CLK edge will shift in the data on the D IN pin. Finally, when 8 bits have been loaded, the CE line is brought to logic high. When CLK goes to logic low, new data is copied into the selected control word. Loading data into the Control Register takes place while the previous control word configures the display. Control Word 0 Loading the Control Register with D 7 = Logic low selects Control Word 0 (see Table 2). Bits D0 -D3 adjust the display brightness by pulse width modulating the LED on time, while Bits D 4 -D5 adjusts the display brightness by changing the peak pixel current. Bit D 6 selects normal operation or sleep mode. Sleep mode (Control Word 0, bit D6 = Low) turns off the Internal Display Oscillator and the LED pixel drivers. This mode is used when the IC needs to be powered up, but does not need to be active. Current draw in sleep mode is nearly zero. Data in the Dot Register and Control Words are retained during sleep mode. Control Word 1 Loading the Control Register with D 7 = logic high selects Control Word 1. This Control Word performs two functions: serial/ simultaneous data out mode and external oscillator prescale select (see Table 2).
Table 2. Control Shift Register.
Bit D0 of control word 1 is used to switch the mode of DOUT between serial and simultaneous data entry during Control Register writes. The default mode (logic low) is the serial D OUT mode. In serial mode, DOUT is connected to the last bit (D7) of the Control Shift Register. Storing logic high to bit D0 changes DOUT to simultaneous mode, which affects the Control Register only. In simultaneous mode, D OUT is logically connected to DIN. This arrange- ment allows multiple ICs to have their Control Registers written to simultaneously. For example, for n ICs in the serial mode, n * 8 clock pulses are needed to load the same data in all Control Registers. In the simultaneous mode, n ICs only need 8 clock pulses to load the same data in all Control Registers. The propaga- tion delay from the first IC to the last is n * t DOUTP. External Oscillator Prescaler Bit D1 Bit D1 of Control Word 1 is used to scale the frequency of an external Display Oscillator. When this bit is logic low, the external Display Oscillator directly sets the internal display clock rate. When this bit is logic high, the external oscillator is divided by 8. This scaled frequency then sets the internal display clock rate. It takes 512 cycles of the display clock (or 8 x 512 = 4096 cycles of an external clock with the divide by 8 prescaler) to completely refresh the display once. Using the prescaler bit allows the designer to use a higher external oscillator frequency without extra circuitry. This bit has no affect on the internal Display Oscillator Frequency. Bits D2 -D6 These bits must always be programmed to logic low. Cascaded ICs Figure 8 shows how two ICs are connected within an HCMS-39XX display. The first IC controls the four left-most characters and the second IC controls the four right- most characters. The Dot Registers are connected in series to form a 320-bit dot shift register. The location of pixel 0 has not changed. However, Dot Shift Register bit 0 of IC2 becomes bit 160 of the 320-bit dot shift register. The Control Registers of the two ICs are independent of each other. This means that to adjust the display brightness the same control word must be entered into both ICs, unless the Control Registers are set to simultaneous mode. Longer character string systems can be built by cascading multiple displays together. This is accomplished by creating a five- line bus. This bus consists of CE, RS, BL, Reset, and CLK. The display pins are connected to the corresponding bus line. Thus, all CE pins are connected to the CE bus line. Similarly, bus lines for RS, BL, Reset, and CLK are created. Then D IN is connected to the right-most display. DOUT from this display is connected to the next display. The left-most display receives its D IN from the DOUT of the display to its right. DOUT from the left-most display is not used. Each display may be set to use its internal oscillator, or the displays may be synchronized by setting up one display as the master and the others as slaves. The slaves are set to receive their oscillator input from the master’s oscillator output.
Figure 8. Cascaded ICs.
supply ILED (AVG) continuously. Table 3. Equations. IPIXEL = peak pixel current. below 3.1 V is not recommended.
0.4 V greater than the LED
by the switching LED drivers.
Appendix D. Refresh Circuitry This display driver consists of 20 one-of-eight column decoders and 20 constant current sources, 1 one-of-eight row decoder and eight row sinks, a pulse width modulation control block, a peak current control block, and the circuit to refresh the LEDs. The refresh counters and oscillator are used to synchronize the columns and rows. The 160 bits are organized as 20 columns by 8 rows. The IC illuminates the display by sequentially turning ON each of the 8 row-drivers. To refresh the display once takes 512 oscillator cycles. Because there are eight row drivers, each row driver is selected for 64 (512/8) oscillator cycles. Four cycles are used to briefly blank the display before the following row is switched on. Thus, each row is ON for 60 oscillator cycles out of a possible 64. This corresponds to the maximum LED on time. The temperature of the display will also affect the LED bright- ness as shown in Figure 10. connections are used, the LED ground can vary from -0.3 V to +0.3 V with respect to the logic ground. Voltages below -0.3 V can cause all the dots to be ON. Voltage above +0.3 V can cause dimming and dot mismatch. Using a decoupling capacitor between the power supply and ground will help prevent any supply noise in the frequency range greater than that of the functioning display from interfering with the display’s internal circuitry. The value of the capacitor depends on the series resistance from the ground back to the power supply and the range of frequencies that need to be suppressed. It is also advantageous to use the largest ground plane possible. Electrostatic Discharge The inputs to the ICs are protected against static discharge and input current latch up. However, for best results, standard CMOS handling precautions should be used. Before use, the HCMS-39XX should be stored in antistatic tubes or in conductive material. During assembly, a grounded conductive work area should be used and assembly personnel should wear conductive wrist straps. Lab coats made of synthetic material should be avoided since they are prone to static buildup. Input current latch up is caused when the CMOS inputs are subjected to either a voltage below ground IN < ground) or to a voltage higher than VLOGIC (VIN >V LOGIC) and when a high current is forced into the input. To prevent input current latch up and ESD damage, unused inputs should be connected to either ground or V LOGIC. Voltages should not be applied to the inputs until V LOGIC has been applied to the display. Appendix C. Oscillator The oscillator provides the internal refresh circuitry with a signal that is used to synchronize the columns and rows. This ensures that the right data is in the dot drivers for that row. This signal can be supplied from either an external source or the internal source. A display refresh rate of 100 Hz or faster ensures flicker-free operation. Thus, for an external oscillator the frequency should be greater than or equal to 512 x 100 Hz = 51.2 kHz. Operation above 1 MHz without the prescaler or 8 MHz with the prescaler may cause noticeable pixel-to-pixel mismatch.
Figure 10. Relative luminous Intensity versus ambient temperature. brightness as shown in Figure 10.
For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countrie s. Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved. Obsoletes 5988-7528EN 5989-3185EN May 27, 2006